1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // STMicroelectronics STM32 SPI Controller driver (master mode only)
4 //
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
7
8 #include <linux/bitfield.h>
9 #include <linux/debugfs.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/interrupt.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/of_platform.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/spi/spi.h>
21
22 #define DRIVER_NAME "spi_stm32"
23
24 /* STM32F4 SPI registers */
25 #define STM32F4_SPI_CR1 0x00
26 #define STM32F4_SPI_CR2 0x04
27 #define STM32F4_SPI_SR 0x08
28 #define STM32F4_SPI_DR 0x0C
29 #define STM32F4_SPI_I2SCFGR 0x1C
30
31 /* STM32F4_SPI_CR1 bit fields */
32 #define STM32F4_SPI_CR1_CPHA BIT(0)
33 #define STM32F4_SPI_CR1_CPOL BIT(1)
34 #define STM32F4_SPI_CR1_MSTR BIT(2)
35 #define STM32F4_SPI_CR1_BR_SHIFT 3
36 #define STM32F4_SPI_CR1_BR GENMASK(5, 3)
37 #define STM32F4_SPI_CR1_SPE BIT(6)
38 #define STM32F4_SPI_CR1_LSBFRST BIT(7)
39 #define STM32F4_SPI_CR1_SSI BIT(8)
40 #define STM32F4_SPI_CR1_SSM BIT(9)
41 #define STM32F4_SPI_CR1_RXONLY BIT(10)
42 #define STM32F4_SPI_CR1_DFF BIT(11)
43 #define STM32F4_SPI_CR1_CRCNEXT BIT(12)
44 #define STM32F4_SPI_CR1_CRCEN BIT(13)
45 #define STM32F4_SPI_CR1_BIDIOE BIT(14)
46 #define STM32F4_SPI_CR1_BIDIMODE BIT(15)
47 #define STM32F4_SPI_CR1_BR_MIN 0
48 #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
49
50 /* STM32F4_SPI_CR2 bit fields */
51 #define STM32F4_SPI_CR2_RXDMAEN BIT(0)
52 #define STM32F4_SPI_CR2_TXDMAEN BIT(1)
53 #define STM32F4_SPI_CR2_SSOE BIT(2)
54 #define STM32F4_SPI_CR2_FRF BIT(4)
55 #define STM32F4_SPI_CR2_ERRIE BIT(5)
56 #define STM32F4_SPI_CR2_RXNEIE BIT(6)
57 #define STM32F4_SPI_CR2_TXEIE BIT(7)
58
59 /* STM32F4_SPI_SR bit fields */
60 #define STM32F4_SPI_SR_RXNE BIT(0)
61 #define STM32F4_SPI_SR_TXE BIT(1)
62 #define STM32F4_SPI_SR_CHSIDE BIT(2)
63 #define STM32F4_SPI_SR_UDR BIT(3)
64 #define STM32F4_SPI_SR_CRCERR BIT(4)
65 #define STM32F4_SPI_SR_MODF BIT(5)
66 #define STM32F4_SPI_SR_OVR BIT(6)
67 #define STM32F4_SPI_SR_BSY BIT(7)
68 #define STM32F4_SPI_SR_FRE BIT(8)
69
70 /* STM32F4_SPI_I2SCFGR bit fields */
71 #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11)
72
73 /* STM32F4 SPI Baud Rate min/max divisor */
74 #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN)
75 #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX)
76
77 /* STM32H7 SPI registers */
78 #define STM32H7_SPI_CR1 0x00
79 #define STM32H7_SPI_CR2 0x04
80 #define STM32H7_SPI_CFG1 0x08
81 #define STM32H7_SPI_CFG2 0x0C
82 #define STM32H7_SPI_IER 0x10
83 #define STM32H7_SPI_SR 0x14
84 #define STM32H7_SPI_IFCR 0x18
85 #define STM32H7_SPI_TXDR 0x20
86 #define STM32H7_SPI_RXDR 0x30
87 #define STM32H7_SPI_I2SCFGR 0x50
88
89 /* STM32H7_SPI_CR1 bit fields */
90 #define STM32H7_SPI_CR1_SPE BIT(0)
91 #define STM32H7_SPI_CR1_MASRX BIT(8)
92 #define STM32H7_SPI_CR1_CSTART BIT(9)
93 #define STM32H7_SPI_CR1_CSUSP BIT(10)
94 #define STM32H7_SPI_CR1_HDDIR BIT(11)
95 #define STM32H7_SPI_CR1_SSI BIT(12)
96
97 /* STM32H7_SPI_CR2 bit fields */
98 #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
99 #define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
100
101 /* STM32H7_SPI_CFG1 bit fields */
102 #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
103 #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
104 #define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
105 #define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
106 #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
107 #define STM32H7_SPI_CFG1_MBR_SHIFT 28
108 #define STM32H7_SPI_CFG1_MBR_MIN 0
109 #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
110
111 /* STM32H7_SPI_CFG2 bit fields */
112 #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
113 #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
114 #define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
115 #define STM32H7_SPI_CFG2_MASTER BIT(22)
116 #define STM32H7_SPI_CFG2_LSBFRST BIT(23)
117 #define STM32H7_SPI_CFG2_CPHA BIT(24)
118 #define STM32H7_SPI_CFG2_CPOL BIT(25)
119 #define STM32H7_SPI_CFG2_SSM BIT(26)
120 #define STM32H7_SPI_CFG2_AFCNTR BIT(31)
121
122 /* STM32H7_SPI_IER bit fields */
123 #define STM32H7_SPI_IER_RXPIE BIT(0)
124 #define STM32H7_SPI_IER_TXPIE BIT(1)
125 #define STM32H7_SPI_IER_DXPIE BIT(2)
126 #define STM32H7_SPI_IER_EOTIE BIT(3)
127 #define STM32H7_SPI_IER_TXTFIE BIT(4)
128 #define STM32H7_SPI_IER_OVRIE BIT(6)
129 #define STM32H7_SPI_IER_MODFIE BIT(9)
130 #define STM32H7_SPI_IER_ALL GENMASK(10, 0)
131
132 /* STM32H7_SPI_SR bit fields */
133 #define STM32H7_SPI_SR_RXP BIT(0)
134 #define STM32H7_SPI_SR_TXP BIT(1)
135 #define STM32H7_SPI_SR_EOT BIT(3)
136 #define STM32H7_SPI_SR_OVR BIT(6)
137 #define STM32H7_SPI_SR_MODF BIT(9)
138 #define STM32H7_SPI_SR_SUSP BIT(11)
139 #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
140 #define STM32H7_SPI_SR_RXWNE BIT(15)
141
142 /* STM32H7_SPI_IFCR bit fields */
143 #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
144
145 /* STM32H7_SPI_I2SCFGR bit fields */
146 #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
147
148 /* STM32H7 SPI Master Baud Rate min/max divisor */
149 #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
150 #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
151
152 /* STM32H7 SPI Communication mode */
153 #define STM32H7_SPI_FULL_DUPLEX 0
154 #define STM32H7_SPI_SIMPLEX_TX 1
155 #define STM32H7_SPI_SIMPLEX_RX 2
156 #define STM32H7_SPI_HALF_DUPLEX 3
157
158 /* SPI Communication type */
159 #define SPI_FULL_DUPLEX 0
160 #define SPI_SIMPLEX_TX 1
161 #define SPI_SIMPLEX_RX 2
162 #define SPI_3WIRE_TX 3
163 #define SPI_3WIRE_RX 4
164
165 #define STM32_SPI_AUTOSUSPEND_DELAY 1 /* 1 ms */
166
167 /*
168 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
169 * without fifo buffers.
170 */
171 #define SPI_DMA_MIN_BYTES 16
172
173 /**
174 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
175 * @reg: register offset
176 * @mask: bitfield mask
177 * @shift: left shift
178 */
179 struct stm32_spi_reg {
180 int reg;
181 int mask;
182 int shift;
183 };
184
185 /**
186 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
187 * @en: enable register and SPI enable bit
188 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
189 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
190 * @cpol: clock polarity register and polarity bit
191 * @cpha: clock phase register and phase bit
192 * @lsb_first: LSB transmitted first register and bit
193 * @br: baud rate register and bitfields
194 * @rx: SPI RX data register
195 * @tx: SPI TX data register
196 */
197 struct stm32_spi_regspec {
198 const struct stm32_spi_reg en;
199 const struct stm32_spi_reg dma_rx_en;
200 const struct stm32_spi_reg dma_tx_en;
201 const struct stm32_spi_reg cpol;
202 const struct stm32_spi_reg cpha;
203 const struct stm32_spi_reg lsb_first;
204 const struct stm32_spi_reg br;
205 const struct stm32_spi_reg rx;
206 const struct stm32_spi_reg tx;
207 };
208
209 struct stm32_spi;
210
211 /**
212 * struct stm32_spi_cfg - stm32 compatible configuration data
213 * @regs: registers descriptions
214 * @get_fifo_size: routine to get fifo size
215 * @get_bpw_mask: routine to get bits per word mask
216 * @disable: routine to disable controller
217 * @config: routine to configure controller as SPI Master
218 * @set_bpw: routine to configure registers to for bits per word
219 * @set_mode: routine to configure registers to desired mode
220 * @set_data_idleness: optional routine to configure registers to desired idle
221 * time between frames (if driver has this functionality)
222 * @set_number_of_data: optional routine to configure registers to desired
223 * number of data (if driver has this functionality)
224 * @can_dma: routine to determine if the transfer is eligible for DMA use
225 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
226 * using DMA
227 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
228 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
229 * @transfer_one_irq: routine to configure interrupts for driver
230 * @irq_handler_event: Interrupt handler for SPI controller events
231 * @irq_handler_thread: thread of interrupt handler for SPI controller
232 * @baud_rate_div_min: minimum baud rate divisor
233 * @baud_rate_div_max: maximum baud rate divisor
234 * @has_fifo: boolean to know if fifo is used for driver
235 * @has_startbit: boolean to know if start bit is used to start transfer
236 */
237 struct stm32_spi_cfg {
238 const struct stm32_spi_regspec *regs;
239 int (*get_fifo_size)(struct stm32_spi *spi);
240 int (*get_bpw_mask)(struct stm32_spi *spi);
241 void (*disable)(struct stm32_spi *spi);
242 int (*config)(struct stm32_spi *spi);
243 void (*set_bpw)(struct stm32_spi *spi);
244 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
245 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
246 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
247 void (*transfer_one_dma_start)(struct stm32_spi *spi);
248 void (*dma_rx_cb)(void *data);
249 void (*dma_tx_cb)(void *data);
250 int (*transfer_one_irq)(struct stm32_spi *spi);
251 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
252 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
253 unsigned int baud_rate_div_min;
254 unsigned int baud_rate_div_max;
255 bool has_fifo;
256 };
257
258 /**
259 * struct stm32_spi - private data of the SPI controller
260 * @dev: driver model representation of the controller
261 * @master: controller master interface
262 * @cfg: compatible configuration data
263 * @base: virtual memory area
264 * @clk: hw kernel clock feeding the SPI clock generator
265 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
266 * @lock: prevent I/O concurrent access
267 * @irq: SPI controller interrupt line
268 * @fifo_size: size of the embedded fifo in bytes
269 * @cur_midi: master inter-data idleness in ns
270 * @cur_speed: speed configured in Hz
271 * @cur_half_period: time of a half bit in us
272 * @cur_bpw: number of bits in a single SPI data frame
273 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
274 * @cur_comm: SPI communication mode
275 * @cur_xferlen: current transfer length in bytes
276 * @cur_usedma: boolean to know if dma is used in current transfer
277 * @tx_buf: data to be written, or NULL
278 * @rx_buf: data to be read, or NULL
279 * @tx_len: number of data to be written in bytes
280 * @rx_len: number of data to be read in bytes
281 * @dma_tx: dma channel for TX transfer
282 * @dma_rx: dma channel for RX transfer
283 * @phys_addr: SPI registers physical base address
284 */
285 struct stm32_spi {
286 struct device *dev;
287 struct spi_master *master;
288 const struct stm32_spi_cfg *cfg;
289 void __iomem *base;
290 struct clk *clk;
291 u32 clk_rate;
292 spinlock_t lock; /* prevent I/O concurrent access */
293 int irq;
294 unsigned int fifo_size;
295
296 unsigned int cur_midi;
297 unsigned int cur_speed;
298 unsigned int cur_half_period;
299 unsigned int cur_bpw;
300 unsigned int cur_fthlv;
301 unsigned int cur_comm;
302 unsigned int cur_xferlen;
303 bool cur_usedma;
304
305 const void *tx_buf;
306 void *rx_buf;
307 int tx_len;
308 int rx_len;
309 struct dma_chan *dma_tx;
310 struct dma_chan *dma_rx;
311 dma_addr_t phys_addr;
312 };
313
314 static const struct stm32_spi_regspec stm32f4_spi_regspec = {
315 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE },
316
317 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN },
318 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN },
319
320 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL },
321 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
322 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST },
323 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT },
324
325 .rx = { STM32F4_SPI_DR },
326 .tx = { STM32F4_SPI_DR },
327 };
328
329 static const struct stm32_spi_regspec stm32h7_spi_regspec = {
330 /* SPI data transfer is enabled but spi_ker_ck is idle.
331 * CFG1 and CFG2 registers are write protected when SPE is enabled.
332 */
333 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
334
335 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
336 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
337
338 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
339 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
340 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
341 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
342 STM32H7_SPI_CFG1_MBR_SHIFT },
343
344 .rx = { STM32H7_SPI_RXDR },
345 .tx = { STM32H7_SPI_TXDR },
346 };
347
stm32_spi_set_bits(struct stm32_spi * spi,u32 offset,u32 bits)348 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
349 u32 offset, u32 bits)
350 {
351 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
352 spi->base + offset);
353 }
354
stm32_spi_clr_bits(struct stm32_spi * spi,u32 offset,u32 bits)355 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
356 u32 offset, u32 bits)
357 {
358 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
359 spi->base + offset);
360 }
361
362 /**
363 * stm32h7_spi_get_fifo_size - Return fifo size
364 * @spi: pointer to the spi controller data structure
365 */
stm32h7_spi_get_fifo_size(struct stm32_spi * spi)366 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
367 {
368 unsigned long flags;
369 u32 count = 0;
370
371 spin_lock_irqsave(&spi->lock, flags);
372
373 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
374
375 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
376 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
377
378 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
379
380 spin_unlock_irqrestore(&spi->lock, flags);
381
382 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
383
384 return count;
385 }
386
387 /**
388 * stm32f4_spi_get_bpw_mask - Return bits per word mask
389 * @spi: pointer to the spi controller data structure
390 */
stm32f4_spi_get_bpw_mask(struct stm32_spi * spi)391 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
392 {
393 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
394 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
395 }
396
397 /**
398 * stm32h7_spi_get_bpw_mask - Return bits per word mask
399 * @spi: pointer to the spi controller data structure
400 */
stm32h7_spi_get_bpw_mask(struct stm32_spi * spi)401 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
402 {
403 unsigned long flags;
404 u32 cfg1, max_bpw;
405
406 spin_lock_irqsave(&spi->lock, flags);
407
408 /*
409 * The most significant bit at DSIZE bit field is reserved when the
410 * maximum data size of periperal instances is limited to 16-bit
411 */
412 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
413
414 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
415 max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
416
417 spin_unlock_irqrestore(&spi->lock, flags);
418
419 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
420
421 return SPI_BPW_RANGE_MASK(4, max_bpw);
422 }
423
424 /**
425 * stm32_spi_prepare_mbr - Determine baud rate divisor value
426 * @spi: pointer to the spi controller data structure
427 * @speed_hz: requested speed
428 * @min_div: minimum baud rate divisor
429 * @max_div: maximum baud rate divisor
430 *
431 * Return baud rate divisor value in case of success or -EINVAL
432 */
stm32_spi_prepare_mbr(struct stm32_spi * spi,u32 speed_hz,u32 min_div,u32 max_div)433 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
434 u32 min_div, u32 max_div)
435 {
436 u32 div, mbrdiv;
437
438 /* Ensure spi->clk_rate is even */
439 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
440
441 /*
442 * SPI framework set xfer->speed_hz to master->max_speed_hz if
443 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
444 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
445 * no need to check it there.
446 * However, we need to ensure the following calculations.
447 */
448 if ((div < min_div) || (div > max_div))
449 return -EINVAL;
450
451 /* Determine the first power of 2 greater than or equal to div */
452 if (div & (div - 1))
453 mbrdiv = fls(div);
454 else
455 mbrdiv = fls(div) - 1;
456
457 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
458
459 spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed);
460
461 return mbrdiv - 1;
462 }
463
464 /**
465 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
466 * @spi: pointer to the spi controller data structure
467 * @xfer_len: length of the message to be transferred
468 */
stm32h7_spi_prepare_fthlv(struct stm32_spi * spi,u32 xfer_len)469 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
470 {
471 u32 packet, bpw;
472
473 /* data packet should not exceed 1/2 of fifo space */
474 packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
475
476 /* align packet size with data registers access */
477 bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
478 return DIV_ROUND_UP(packet, bpw);
479 }
480
481 /**
482 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
483 * @spi: pointer to the spi controller data structure
484 *
485 * Read from tx_buf depends on remaining bytes to avoid to read beyond
486 * tx_buf end.
487 */
stm32f4_spi_write_tx(struct stm32_spi * spi)488 static void stm32f4_spi_write_tx(struct stm32_spi *spi)
489 {
490 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
491 STM32F4_SPI_SR_TXE)) {
492 u32 offs = spi->cur_xferlen - spi->tx_len;
493
494 if (spi->cur_bpw == 16) {
495 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
496
497 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
498 spi->tx_len -= sizeof(u16);
499 } else {
500 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
501
502 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
503 spi->tx_len -= sizeof(u8);
504 }
505 }
506
507 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
508 }
509
510 /**
511 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
512 * @spi: pointer to the spi controller data structure
513 *
514 * Read from tx_buf depends on remaining bytes to avoid to read beyond
515 * tx_buf end.
516 */
stm32h7_spi_write_txfifo(struct stm32_spi * spi)517 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
518 {
519 while ((spi->tx_len > 0) &&
520 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
521 STM32H7_SPI_SR_TXP)) {
522 u32 offs = spi->cur_xferlen - spi->tx_len;
523
524 if (spi->tx_len >= sizeof(u32)) {
525 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
526
527 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
528 spi->tx_len -= sizeof(u32);
529 } else if (spi->tx_len >= sizeof(u16)) {
530 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
531
532 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
533 spi->tx_len -= sizeof(u16);
534 } else {
535 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
536
537 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
538 spi->tx_len -= sizeof(u8);
539 }
540 }
541
542 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
543 }
544
545 /**
546 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
547 * @spi: pointer to the spi controller data structure
548 *
549 * Write in rx_buf depends on remaining bytes to avoid to write beyond
550 * rx_buf end.
551 */
stm32f4_spi_read_rx(struct stm32_spi * spi)552 static void stm32f4_spi_read_rx(struct stm32_spi *spi)
553 {
554 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
555 STM32F4_SPI_SR_RXNE)) {
556 u32 offs = spi->cur_xferlen - spi->rx_len;
557
558 if (spi->cur_bpw == 16) {
559 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
560
561 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
562 spi->rx_len -= sizeof(u16);
563 } else {
564 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
565
566 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
567 spi->rx_len -= sizeof(u8);
568 }
569 }
570
571 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
572 }
573
574 /**
575 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
576 * @spi: pointer to the spi controller data structure
577 *
578 * Write in rx_buf depends on remaining bytes to avoid to write beyond
579 * rx_buf end.
580 */
stm32h7_spi_read_rxfifo(struct stm32_spi * spi)581 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi)
582 {
583 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
584 u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
585
586 while ((spi->rx_len > 0) &&
587 ((sr & STM32H7_SPI_SR_RXP) ||
588 ((sr & STM32H7_SPI_SR_EOT) &&
589 ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
590 u32 offs = spi->cur_xferlen - spi->rx_len;
591
592 if ((spi->rx_len >= sizeof(u32)) ||
593 (sr & STM32H7_SPI_SR_RXWNE)) {
594 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
595
596 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
597 spi->rx_len -= sizeof(u32);
598 } else if ((spi->rx_len >= sizeof(u16)) ||
599 (!(sr & STM32H7_SPI_SR_RXWNE) &&
600 (rxplvl >= 2 || spi->cur_bpw > 8))) {
601 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
602
603 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
604 spi->rx_len -= sizeof(u16);
605 } else {
606 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
607
608 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
609 spi->rx_len -= sizeof(u8);
610 }
611
612 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
613 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
614 }
615
616 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
617 __func__, spi->rx_len, sr);
618 }
619
620 /**
621 * stm32_spi_enable - Enable SPI controller
622 * @spi: pointer to the spi controller data structure
623 */
stm32_spi_enable(struct stm32_spi * spi)624 static void stm32_spi_enable(struct stm32_spi *spi)
625 {
626 dev_dbg(spi->dev, "enable controller\n");
627
628 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
629 spi->cfg->regs->en.mask);
630 }
631
632 /**
633 * stm32f4_spi_disable - Disable SPI controller
634 * @spi: pointer to the spi controller data structure
635 */
stm32f4_spi_disable(struct stm32_spi * spi)636 static void stm32f4_spi_disable(struct stm32_spi *spi)
637 {
638 unsigned long flags;
639 u32 sr;
640
641 dev_dbg(spi->dev, "disable controller\n");
642
643 spin_lock_irqsave(&spi->lock, flags);
644
645 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
646 STM32F4_SPI_CR1_SPE)) {
647 spin_unlock_irqrestore(&spi->lock, flags);
648 return;
649 }
650
651 /* Disable interrupts */
652 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
653 STM32F4_SPI_CR2_RXNEIE |
654 STM32F4_SPI_CR2_ERRIE);
655
656 /* Wait until BSY = 0 */
657 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
658 sr, !(sr & STM32F4_SPI_SR_BSY),
659 10, 100000) < 0) {
660 dev_warn(spi->dev, "disabling condition timeout\n");
661 }
662
663 if (spi->cur_usedma && spi->dma_tx)
664 dmaengine_terminate_all(spi->dma_tx);
665 if (spi->cur_usedma && spi->dma_rx)
666 dmaengine_terminate_all(spi->dma_rx);
667
668 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
669
670 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
671 STM32F4_SPI_CR2_RXDMAEN);
672
673 /* Sequence to clear OVR flag */
674 readl_relaxed(spi->base + STM32F4_SPI_DR);
675 readl_relaxed(spi->base + STM32F4_SPI_SR);
676
677 spin_unlock_irqrestore(&spi->lock, flags);
678 }
679
680 /**
681 * stm32h7_spi_disable - Disable SPI controller
682 * @spi: pointer to the spi controller data structure
683 *
684 * RX-Fifo is flushed when SPI controller is disabled.
685 */
stm32h7_spi_disable(struct stm32_spi * spi)686 static void stm32h7_spi_disable(struct stm32_spi *spi)
687 {
688 unsigned long flags;
689 u32 cr1;
690
691 dev_dbg(spi->dev, "disable controller\n");
692
693 spin_lock_irqsave(&spi->lock, flags);
694
695 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
696
697 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
698 spin_unlock_irqrestore(&spi->lock, flags);
699 return;
700 }
701
702 /* Add a delay to make sure that transmission is ended. */
703 if (spi->cur_half_period)
704 udelay(spi->cur_half_period);
705
706 if (spi->cur_usedma && spi->dma_tx)
707 dmaengine_terminate_all(spi->dma_tx);
708 if (spi->cur_usedma && spi->dma_rx)
709 dmaengine_terminate_all(spi->dma_rx);
710
711 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
712
713 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
714 STM32H7_SPI_CFG1_RXDMAEN);
715
716 /* Disable interrupts and clear status flags */
717 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
718 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
719
720 spin_unlock_irqrestore(&spi->lock, flags);
721 }
722
723 /**
724 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
725 * @master: controller master interface
726 * @spi_dev: pointer to the spi device
727 * @transfer: pointer to spi transfer
728 *
729 * If driver has fifo and the current transfer size is greater than fifo size,
730 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
731 */
stm32_spi_can_dma(struct spi_master * master,struct spi_device * spi_dev,struct spi_transfer * transfer)732 static bool stm32_spi_can_dma(struct spi_master *master,
733 struct spi_device *spi_dev,
734 struct spi_transfer *transfer)
735 {
736 unsigned int dma_size;
737 struct stm32_spi *spi = spi_master_get_devdata(master);
738
739 if (spi->cfg->has_fifo)
740 dma_size = spi->fifo_size;
741 else
742 dma_size = SPI_DMA_MIN_BYTES;
743
744 dev_dbg(spi->dev, "%s: %s\n", __func__,
745 (transfer->len > dma_size) ? "true" : "false");
746
747 return (transfer->len > dma_size);
748 }
749
750 /**
751 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
752 * @irq: interrupt line
753 * @dev_id: SPI controller master interface
754 */
stm32f4_spi_irq_event(int irq,void * dev_id)755 static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id)
756 {
757 struct spi_master *master = dev_id;
758 struct stm32_spi *spi = spi_master_get_devdata(master);
759 u32 sr, mask = 0;
760 bool end = false;
761
762 spin_lock(&spi->lock);
763
764 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
765 /*
766 * BSY flag is not handled in interrupt but it is normal behavior when
767 * this flag is set.
768 */
769 sr &= ~STM32F4_SPI_SR_BSY;
770
771 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
772 spi->cur_comm == SPI_3WIRE_TX)) {
773 /* OVR flag shouldn't be handled for TX only mode */
774 sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE;
775 mask |= STM32F4_SPI_SR_TXE;
776 }
777
778 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
779 spi->cur_comm == SPI_SIMPLEX_RX ||
780 spi->cur_comm == SPI_3WIRE_RX)) {
781 /* TXE flag is set and is handled when RXNE flag occurs */
782 sr &= ~STM32F4_SPI_SR_TXE;
783 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR;
784 }
785
786 if (!(sr & mask)) {
787 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
788 spin_unlock(&spi->lock);
789 return IRQ_NONE;
790 }
791
792 if (sr & STM32F4_SPI_SR_OVR) {
793 dev_warn(spi->dev, "Overrun: received value discarded\n");
794
795 /* Sequence to clear OVR flag */
796 readl_relaxed(spi->base + STM32F4_SPI_DR);
797 readl_relaxed(spi->base + STM32F4_SPI_SR);
798
799 /*
800 * If overrun is detected, it means that something went wrong,
801 * so stop the current transfer. Transfer can wait for next
802 * RXNE but DR is already read and end never happens.
803 */
804 end = true;
805 goto end_irq;
806 }
807
808 if (sr & STM32F4_SPI_SR_TXE) {
809 if (spi->tx_buf)
810 stm32f4_spi_write_tx(spi);
811 if (spi->tx_len == 0)
812 end = true;
813 }
814
815 if (sr & STM32F4_SPI_SR_RXNE) {
816 stm32f4_spi_read_rx(spi);
817 if (spi->rx_len == 0)
818 end = true;
819 else if (spi->tx_buf)/* Load data for discontinuous mode */
820 stm32f4_spi_write_tx(spi);
821 }
822
823 end_irq:
824 if (end) {
825 /* Immediately disable interrupts to do not generate new one */
826 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
827 STM32F4_SPI_CR2_TXEIE |
828 STM32F4_SPI_CR2_RXNEIE |
829 STM32F4_SPI_CR2_ERRIE);
830 spin_unlock(&spi->lock);
831 return IRQ_WAKE_THREAD;
832 }
833
834 spin_unlock(&spi->lock);
835 return IRQ_HANDLED;
836 }
837
838 /**
839 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
840 * @irq: interrupt line
841 * @dev_id: SPI controller master interface
842 */
stm32f4_spi_irq_thread(int irq,void * dev_id)843 static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id)
844 {
845 struct spi_master *master = dev_id;
846 struct stm32_spi *spi = spi_master_get_devdata(master);
847
848 spi_finalize_current_transfer(master);
849 stm32f4_spi_disable(spi);
850
851 return IRQ_HANDLED;
852 }
853
854 /**
855 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
856 * @irq: interrupt line
857 * @dev_id: SPI controller master interface
858 */
stm32h7_spi_irq_thread(int irq,void * dev_id)859 static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
860 {
861 struct spi_master *master = dev_id;
862 struct stm32_spi *spi = spi_master_get_devdata(master);
863 u32 sr, ier, mask;
864 unsigned long flags;
865 bool end = false;
866
867 spin_lock_irqsave(&spi->lock, flags);
868
869 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
870 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
871
872 mask = ier;
873 /*
874 * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
875 * SUSP to acknowledge it later. TXC is automatically cleared
876 */
877
878 mask |= STM32H7_SPI_SR_SUSP;
879 /*
880 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
881 * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
882 */
883 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
884 mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
885
886 if (!(sr & mask)) {
887 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
888 sr, ier);
889 spin_unlock_irqrestore(&spi->lock, flags);
890 return IRQ_NONE;
891 }
892
893 if (sr & STM32H7_SPI_SR_SUSP) {
894 static DEFINE_RATELIMIT_STATE(rs,
895 DEFAULT_RATELIMIT_INTERVAL * 10,
896 1);
897 ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
898 if (__ratelimit(&rs))
899 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
900 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
901 stm32h7_spi_read_rxfifo(spi);
902 /*
903 * If communication is suspended while using DMA, it means
904 * that something went wrong, so stop the current transfer
905 */
906 if (spi->cur_usedma)
907 end = true;
908 }
909
910 if (sr & STM32H7_SPI_SR_MODF) {
911 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
912 end = true;
913 }
914
915 if (sr & STM32H7_SPI_SR_OVR) {
916 dev_err(spi->dev, "Overrun: RX data lost\n");
917 end = true;
918 }
919
920 if (sr & STM32H7_SPI_SR_EOT) {
921 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
922 stm32h7_spi_read_rxfifo(spi);
923 if (!spi->cur_usedma ||
924 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX))
925 end = true;
926 }
927
928 if (sr & STM32H7_SPI_SR_TXP)
929 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
930 stm32h7_spi_write_txfifo(spi);
931
932 if (sr & STM32H7_SPI_SR_RXP)
933 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
934 stm32h7_spi_read_rxfifo(spi);
935
936 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
937
938 spin_unlock_irqrestore(&spi->lock, flags);
939
940 if (end) {
941 stm32h7_spi_disable(spi);
942 spi_finalize_current_transfer(master);
943 }
944
945 return IRQ_HANDLED;
946 }
947
948 /**
949 * stm32_spi_prepare_msg - set up the controller to transfer a single message
950 * @master: controller master interface
951 * @msg: pointer to spi message
952 */
stm32_spi_prepare_msg(struct spi_master * master,struct spi_message * msg)953 static int stm32_spi_prepare_msg(struct spi_master *master,
954 struct spi_message *msg)
955 {
956 struct stm32_spi *spi = spi_master_get_devdata(master);
957 struct spi_device *spi_dev = msg->spi;
958 struct device_node *np = spi_dev->dev.of_node;
959 unsigned long flags;
960 u32 clrb = 0, setb = 0;
961
962 /* SPI slave device may need time between data frames */
963 spi->cur_midi = 0;
964 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
965 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
966
967 if (spi_dev->mode & SPI_CPOL)
968 setb |= spi->cfg->regs->cpol.mask;
969 else
970 clrb |= spi->cfg->regs->cpol.mask;
971
972 if (spi_dev->mode & SPI_CPHA)
973 setb |= spi->cfg->regs->cpha.mask;
974 else
975 clrb |= spi->cfg->regs->cpha.mask;
976
977 if (spi_dev->mode & SPI_LSB_FIRST)
978 setb |= spi->cfg->regs->lsb_first.mask;
979 else
980 clrb |= spi->cfg->regs->lsb_first.mask;
981
982 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
983 !!(spi_dev->mode & SPI_CPOL),
984 !!(spi_dev->mode & SPI_CPHA),
985 !!(spi_dev->mode & SPI_LSB_FIRST),
986 !!(spi_dev->mode & SPI_CS_HIGH));
987
988 /* On STM32H7, messages should not exceed a maximum size setted
989 * afterward via the set_number_of_data function. In order to
990 * ensure that, split large messages into several messages
991 */
992 if (spi->cfg->set_number_of_data) {
993 int ret;
994
995 ret = spi_split_transfers_maxsize(master, msg,
996 STM32H7_SPI_TSIZE_MAX,
997 GFP_KERNEL | GFP_DMA);
998 if (ret)
999 return ret;
1000 }
1001
1002 spin_lock_irqsave(&spi->lock, flags);
1003
1004 /* CPOL, CPHA and LSB FIRST bits have common register */
1005 if (clrb || setb)
1006 writel_relaxed(
1007 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1008 ~clrb) | setb,
1009 spi->base + spi->cfg->regs->cpol.reg);
1010
1011 spin_unlock_irqrestore(&spi->lock, flags);
1012
1013 return 0;
1014 }
1015
1016 /**
1017 * stm32f4_spi_dma_tx_cb - dma callback
1018 * @data: pointer to the spi controller data structure
1019 *
1020 * DMA callback is called when the transfer is complete for DMA TX channel.
1021 */
stm32f4_spi_dma_tx_cb(void * data)1022 static void stm32f4_spi_dma_tx_cb(void *data)
1023 {
1024 struct stm32_spi *spi = data;
1025
1026 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1027 spi_finalize_current_transfer(spi->master);
1028 stm32f4_spi_disable(spi);
1029 }
1030 }
1031
1032 /**
1033 * stm32_spi_dma_rx_cb - dma callback
1034 * @data: pointer to the spi controller data structure
1035 *
1036 * DMA callback is called when the transfer is complete for DMA RX channel.
1037 */
stm32_spi_dma_rx_cb(void * data)1038 static void stm32_spi_dma_rx_cb(void *data)
1039 {
1040 struct stm32_spi *spi = data;
1041
1042 spi_finalize_current_transfer(spi->master);
1043 spi->cfg->disable(spi);
1044 }
1045
1046 /**
1047 * stm32_spi_dma_config - configure dma slave channel depending on current
1048 * transfer bits_per_word.
1049 * @spi: pointer to the spi controller data structure
1050 * @dma_conf: pointer to the dma_slave_config structure
1051 * @dir: direction of the dma transfer
1052 */
stm32_spi_dma_config(struct stm32_spi * spi,struct dma_slave_config * dma_conf,enum dma_transfer_direction dir)1053 static void stm32_spi_dma_config(struct stm32_spi *spi,
1054 struct dma_slave_config *dma_conf,
1055 enum dma_transfer_direction dir)
1056 {
1057 enum dma_slave_buswidth buswidth;
1058 u32 maxburst;
1059
1060 if (spi->cur_bpw <= 8)
1061 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1062 else if (spi->cur_bpw <= 16)
1063 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1064 else
1065 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1066
1067 if (spi->cfg->has_fifo) {
1068 /* Valid for DMA Half or Full Fifo threshold */
1069 if (spi->cur_fthlv == 2)
1070 maxburst = 1;
1071 else
1072 maxburst = spi->cur_fthlv;
1073 } else {
1074 maxburst = 1;
1075 }
1076
1077 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1078 dma_conf->direction = dir;
1079 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1080 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1081 dma_conf->src_addr_width = buswidth;
1082 dma_conf->src_maxburst = maxburst;
1083
1084 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1085 buswidth, maxburst);
1086 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1087 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1088 dma_conf->dst_addr_width = buswidth;
1089 dma_conf->dst_maxburst = maxburst;
1090
1091 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1092 buswidth, maxburst);
1093 }
1094 }
1095
1096 /**
1097 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1098 * interrupts
1099 * @spi: pointer to the spi controller data structure
1100 *
1101 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1102 * in progress.
1103 */
stm32f4_spi_transfer_one_irq(struct stm32_spi * spi)1104 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1105 {
1106 unsigned long flags;
1107 u32 cr2 = 0;
1108
1109 /* Enable the interrupts relative to the current communication mode */
1110 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1111 cr2 |= STM32F4_SPI_CR2_TXEIE;
1112 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1113 spi->cur_comm == SPI_SIMPLEX_RX ||
1114 spi->cur_comm == SPI_3WIRE_RX) {
1115 /* In transmit-only mode, the OVR flag is set in the SR register
1116 * since the received data are never read. Therefore set OVR
1117 * interrupt only when rx buffer is available.
1118 */
1119 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE;
1120 } else {
1121 return -EINVAL;
1122 }
1123
1124 spin_lock_irqsave(&spi->lock, flags);
1125
1126 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1127
1128 stm32_spi_enable(spi);
1129
1130 /* starting data transfer when buffer is loaded */
1131 if (spi->tx_buf)
1132 stm32f4_spi_write_tx(spi);
1133
1134 spin_unlock_irqrestore(&spi->lock, flags);
1135
1136 return 1;
1137 }
1138
1139 /**
1140 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1141 * interrupts
1142 * @spi: pointer to the spi controller data structure
1143 *
1144 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1145 * in progress.
1146 */
stm32h7_spi_transfer_one_irq(struct stm32_spi * spi)1147 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1148 {
1149 unsigned long flags;
1150 u32 ier = 0;
1151
1152 /* Enable the interrupts relative to the current communication mode */
1153 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1154 ier |= STM32H7_SPI_IER_DXPIE;
1155 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1156 ier |= STM32H7_SPI_IER_TXPIE;
1157 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1158 ier |= STM32H7_SPI_IER_RXPIE;
1159
1160 /* Enable the interrupts relative to the end of transfer */
1161 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1162 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1163
1164 spin_lock_irqsave(&spi->lock, flags);
1165
1166 stm32_spi_enable(spi);
1167
1168 /* Be sure to have data in fifo before starting data transfer */
1169 if (spi->tx_buf)
1170 stm32h7_spi_write_txfifo(spi);
1171
1172 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1173
1174 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1175
1176 spin_unlock_irqrestore(&spi->lock, flags);
1177
1178 return 1;
1179 }
1180
1181 /**
1182 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1183 * transfer using DMA
1184 * @spi: pointer to the spi controller data structure
1185 */
stm32f4_spi_transfer_one_dma_start(struct stm32_spi * spi)1186 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1187 {
1188 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1189 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1190 spi->cur_comm == SPI_FULL_DUPLEX) {
1191 /*
1192 * In transmit-only mode, the OVR flag is set in the SR register
1193 * since the received data are never read. Therefore set OVR
1194 * interrupt only when rx buffer is available.
1195 */
1196 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1197 }
1198
1199 stm32_spi_enable(spi);
1200 }
1201
1202 /**
1203 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1204 * transfer using DMA
1205 * @spi: pointer to the spi controller data structure
1206 */
stm32h7_spi_transfer_one_dma_start(struct stm32_spi * spi)1207 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1208 {
1209 uint32_t ier = STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1210
1211 /* Enable the interrupts */
1212 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
1213 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
1214
1215 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
1216
1217 stm32_spi_enable(spi);
1218
1219 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1220 }
1221
1222 /**
1223 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1224 * @spi: pointer to the spi controller data structure
1225 * @xfer: pointer to the spi_transfer structure
1226 *
1227 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1228 * in progress.
1229 */
stm32_spi_transfer_one_dma(struct stm32_spi * spi,struct spi_transfer * xfer)1230 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1231 struct spi_transfer *xfer)
1232 {
1233 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1234 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1235 unsigned long flags;
1236
1237 spin_lock_irqsave(&spi->lock, flags);
1238
1239 rx_dma_desc = NULL;
1240 if (spi->rx_buf && spi->dma_rx) {
1241 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1242 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1243
1244 /* Enable Rx DMA request */
1245 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1246 spi->cfg->regs->dma_rx_en.mask);
1247
1248 rx_dma_desc = dmaengine_prep_slave_sg(
1249 spi->dma_rx, xfer->rx_sg.sgl,
1250 xfer->rx_sg.nents,
1251 rx_dma_conf.direction,
1252 DMA_PREP_INTERRUPT);
1253 }
1254
1255 tx_dma_desc = NULL;
1256 if (spi->tx_buf && spi->dma_tx) {
1257 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1258 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1259
1260 tx_dma_desc = dmaengine_prep_slave_sg(
1261 spi->dma_tx, xfer->tx_sg.sgl,
1262 xfer->tx_sg.nents,
1263 tx_dma_conf.direction,
1264 DMA_PREP_INTERRUPT);
1265 }
1266
1267 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1268 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1269 goto dma_desc_error;
1270
1271 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1272 goto dma_desc_error;
1273
1274 if (rx_dma_desc) {
1275 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1276 rx_dma_desc->callback_param = spi;
1277
1278 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1279 dev_err(spi->dev, "Rx DMA submit failed\n");
1280 goto dma_desc_error;
1281 }
1282 /* Enable Rx DMA channel */
1283 dma_async_issue_pending(spi->dma_rx);
1284 }
1285
1286 if (tx_dma_desc) {
1287 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1288 spi->cur_comm == SPI_3WIRE_TX) {
1289 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1290 tx_dma_desc->callback_param = spi;
1291 }
1292
1293 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1294 dev_err(spi->dev, "Tx DMA submit failed\n");
1295 goto dma_submit_error;
1296 }
1297 /* Enable Tx DMA channel */
1298 dma_async_issue_pending(spi->dma_tx);
1299
1300 /* Enable Tx DMA request */
1301 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1302 spi->cfg->regs->dma_tx_en.mask);
1303 }
1304
1305 spi->cfg->transfer_one_dma_start(spi);
1306
1307 spin_unlock_irqrestore(&spi->lock, flags);
1308
1309 return 1;
1310
1311 dma_submit_error:
1312 if (spi->dma_rx)
1313 dmaengine_terminate_all(spi->dma_rx);
1314
1315 dma_desc_error:
1316 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1317 spi->cfg->regs->dma_rx_en.mask);
1318
1319 spin_unlock_irqrestore(&spi->lock, flags);
1320
1321 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1322
1323 spi->cur_usedma = false;
1324 return spi->cfg->transfer_one_irq(spi);
1325 }
1326
1327 /**
1328 * stm32f4_spi_set_bpw - Configure bits per word
1329 * @spi: pointer to the spi controller data structure
1330 */
stm32f4_spi_set_bpw(struct stm32_spi * spi)1331 static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1332 {
1333 if (spi->cur_bpw == 16)
1334 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1335 else
1336 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1337 }
1338
1339 /**
1340 * stm32h7_spi_set_bpw - configure bits per word
1341 * @spi: pointer to the spi controller data structure
1342 */
stm32h7_spi_set_bpw(struct stm32_spi * spi)1343 static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1344 {
1345 u32 bpw, fthlv;
1346 u32 cfg1_clrb = 0, cfg1_setb = 0;
1347
1348 bpw = spi->cur_bpw - 1;
1349
1350 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1351 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
1352
1353 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1354 fthlv = spi->cur_fthlv - 1;
1355
1356 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1357 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
1358
1359 writel_relaxed(
1360 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1361 ~cfg1_clrb) | cfg1_setb,
1362 spi->base + STM32H7_SPI_CFG1);
1363 }
1364
1365 /**
1366 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1367 * @spi: pointer to the spi controller data structure
1368 * @mbrdiv: baud rate divisor value
1369 */
stm32_spi_set_mbr(struct stm32_spi * spi,u32 mbrdiv)1370 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1371 {
1372 u32 clrb = 0, setb = 0;
1373
1374 clrb |= spi->cfg->regs->br.mask;
1375 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1376
1377 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1378 ~clrb) | setb,
1379 spi->base + spi->cfg->regs->br.reg);
1380 }
1381
1382 /**
1383 * stm32_spi_communication_type - return transfer communication type
1384 * @spi_dev: pointer to the spi device
1385 * @transfer: pointer to spi transfer
1386 */
stm32_spi_communication_type(struct spi_device * spi_dev,struct spi_transfer * transfer)1387 static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1388 struct spi_transfer *transfer)
1389 {
1390 unsigned int type = SPI_FULL_DUPLEX;
1391
1392 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1393 /*
1394 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1395 * is forbidden and unvalidated by SPI subsystem so depending
1396 * on the valid buffer, we can determine the direction of the
1397 * transfer.
1398 */
1399 if (!transfer->tx_buf)
1400 type = SPI_3WIRE_RX;
1401 else
1402 type = SPI_3WIRE_TX;
1403 } else {
1404 if (!transfer->tx_buf)
1405 type = SPI_SIMPLEX_RX;
1406 else if (!transfer->rx_buf)
1407 type = SPI_SIMPLEX_TX;
1408 }
1409
1410 return type;
1411 }
1412
1413 /**
1414 * stm32f4_spi_set_mode - configure communication mode
1415 * @spi: pointer to the spi controller data structure
1416 * @comm_type: type of communication to configure
1417 */
stm32f4_spi_set_mode(struct stm32_spi * spi,unsigned int comm_type)1418 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1419 {
1420 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1421 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1422 STM32F4_SPI_CR1_BIDIMODE |
1423 STM32F4_SPI_CR1_BIDIOE);
1424 } else if (comm_type == SPI_FULL_DUPLEX ||
1425 comm_type == SPI_SIMPLEX_RX) {
1426 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1427 STM32F4_SPI_CR1_BIDIMODE |
1428 STM32F4_SPI_CR1_BIDIOE);
1429 } else if (comm_type == SPI_3WIRE_RX) {
1430 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1431 STM32F4_SPI_CR1_BIDIMODE);
1432 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1433 STM32F4_SPI_CR1_BIDIOE);
1434 } else {
1435 return -EINVAL;
1436 }
1437
1438 return 0;
1439 }
1440
1441 /**
1442 * stm32h7_spi_set_mode - configure communication mode
1443 * @spi: pointer to the spi controller data structure
1444 * @comm_type: type of communication to configure
1445 */
stm32h7_spi_set_mode(struct stm32_spi * spi,unsigned int comm_type)1446 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1447 {
1448 u32 mode;
1449 u32 cfg2_clrb = 0, cfg2_setb = 0;
1450
1451 if (comm_type == SPI_3WIRE_RX) {
1452 mode = STM32H7_SPI_HALF_DUPLEX;
1453 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1454 } else if (comm_type == SPI_3WIRE_TX) {
1455 mode = STM32H7_SPI_HALF_DUPLEX;
1456 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1457 } else if (comm_type == SPI_SIMPLEX_RX) {
1458 mode = STM32H7_SPI_SIMPLEX_RX;
1459 } else if (comm_type == SPI_SIMPLEX_TX) {
1460 mode = STM32H7_SPI_SIMPLEX_TX;
1461 } else {
1462 mode = STM32H7_SPI_FULL_DUPLEX;
1463 }
1464
1465 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1466 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
1467
1468 writel_relaxed(
1469 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1470 ~cfg2_clrb) | cfg2_setb,
1471 spi->base + STM32H7_SPI_CFG2);
1472
1473 return 0;
1474 }
1475
1476 /**
1477 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1478 * consecutive data frames in master mode
1479 * @spi: pointer to the spi controller data structure
1480 * @len: transfer len
1481 */
stm32h7_spi_data_idleness(struct stm32_spi * spi,u32 len)1482 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1483 {
1484 u32 cfg2_clrb = 0, cfg2_setb = 0;
1485
1486 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1487 if ((len > 1) && (spi->cur_midi > 0)) {
1488 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
1489 u32 midi = min_t(u32,
1490 DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1491 FIELD_GET(STM32H7_SPI_CFG2_MIDI,
1492 STM32H7_SPI_CFG2_MIDI));
1493
1494
1495 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1496 sck_period_ns, midi, midi * sck_period_ns);
1497 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
1498 }
1499
1500 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1501 ~cfg2_clrb) | cfg2_setb,
1502 spi->base + STM32H7_SPI_CFG2);
1503 }
1504
1505 /**
1506 * stm32h7_spi_number_of_data - configure number of data at current transfer
1507 * @spi: pointer to the spi controller data structure
1508 * @nb_words: transfer length (in words)
1509 */
stm32h7_spi_number_of_data(struct stm32_spi * spi,u32 nb_words)1510 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1511 {
1512 if (nb_words <= STM32H7_SPI_TSIZE_MAX) {
1513 writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
1514 spi->base + STM32H7_SPI_CR2);
1515 } else {
1516 return -EMSGSIZE;
1517 }
1518
1519 return 0;
1520 }
1521
1522 /**
1523 * stm32_spi_transfer_one_setup - common setup to transfer a single
1524 * spi_transfer either using DMA or
1525 * interrupts.
1526 * @spi: pointer to the spi controller data structure
1527 * @spi_dev: pointer to the spi device
1528 * @transfer: pointer to spi transfer
1529 */
stm32_spi_transfer_one_setup(struct stm32_spi * spi,struct spi_device * spi_dev,struct spi_transfer * transfer)1530 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1531 struct spi_device *spi_dev,
1532 struct spi_transfer *transfer)
1533 {
1534 unsigned long flags;
1535 unsigned int comm_type;
1536 int nb_words, ret = 0;
1537 int mbr;
1538
1539 spin_lock_irqsave(&spi->lock, flags);
1540
1541 spi->cur_xferlen = transfer->len;
1542
1543 spi->cur_bpw = transfer->bits_per_word;
1544 spi->cfg->set_bpw(spi);
1545
1546 /* Update spi->cur_speed with real clock speed */
1547 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1548 spi->cfg->baud_rate_div_min,
1549 spi->cfg->baud_rate_div_max);
1550 if (mbr < 0) {
1551 ret = mbr;
1552 goto out;
1553 }
1554
1555 transfer->speed_hz = spi->cur_speed;
1556 stm32_spi_set_mbr(spi, mbr);
1557
1558 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1559 ret = spi->cfg->set_mode(spi, comm_type);
1560 if (ret < 0)
1561 goto out;
1562
1563 spi->cur_comm = comm_type;
1564
1565 if (spi->cfg->set_data_idleness)
1566 spi->cfg->set_data_idleness(spi, transfer->len);
1567
1568 if (spi->cur_bpw <= 8)
1569 nb_words = transfer->len;
1570 else if (spi->cur_bpw <= 16)
1571 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1572 else
1573 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1574
1575 if (spi->cfg->set_number_of_data) {
1576 ret = spi->cfg->set_number_of_data(spi, nb_words);
1577 if (ret < 0)
1578 goto out;
1579 }
1580
1581 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1582 spi->cur_comm);
1583 dev_dbg(spi->dev,
1584 "data frame of %d-bit, data packet of %d data frames\n",
1585 spi->cur_bpw, spi->cur_fthlv);
1586 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1587 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1588 spi->cur_xferlen, nb_words);
1589 dev_dbg(spi->dev, "dma %s\n",
1590 (spi->cur_usedma) ? "enabled" : "disabled");
1591
1592 out:
1593 spin_unlock_irqrestore(&spi->lock, flags);
1594
1595 return ret;
1596 }
1597
1598 /**
1599 * stm32_spi_transfer_one - transfer a single spi_transfer
1600 * @master: controller master interface
1601 * @spi_dev: pointer to the spi device
1602 * @transfer: pointer to spi transfer
1603 *
1604 * It must return 0 if the transfer is finished or 1 if the transfer is still
1605 * in progress.
1606 */
stm32_spi_transfer_one(struct spi_master * master,struct spi_device * spi_dev,struct spi_transfer * transfer)1607 static int stm32_spi_transfer_one(struct spi_master *master,
1608 struct spi_device *spi_dev,
1609 struct spi_transfer *transfer)
1610 {
1611 struct stm32_spi *spi = spi_master_get_devdata(master);
1612 int ret;
1613
1614 spi->tx_buf = transfer->tx_buf;
1615 spi->rx_buf = transfer->rx_buf;
1616 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1617 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1618
1619 spi->cur_usedma = (master->can_dma &&
1620 master->can_dma(master, spi_dev, transfer));
1621
1622 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1623 if (ret) {
1624 dev_err(spi->dev, "SPI transfer setup failed\n");
1625 return ret;
1626 }
1627
1628 if (spi->cur_usedma)
1629 return stm32_spi_transfer_one_dma(spi, transfer);
1630 else
1631 return spi->cfg->transfer_one_irq(spi);
1632 }
1633
1634 /**
1635 * stm32_spi_unprepare_msg - relax the hardware
1636 * @master: controller master interface
1637 * @msg: pointer to the spi message
1638 */
stm32_spi_unprepare_msg(struct spi_master * master,struct spi_message * msg)1639 static int stm32_spi_unprepare_msg(struct spi_master *master,
1640 struct spi_message *msg)
1641 {
1642 struct stm32_spi *spi = spi_master_get_devdata(master);
1643
1644 spi->cfg->disable(spi);
1645
1646 return 0;
1647 }
1648
1649 /**
1650 * stm32f4_spi_config - Configure SPI controller as SPI master
1651 * @spi: pointer to the spi controller data structure
1652 */
stm32f4_spi_config(struct stm32_spi * spi)1653 static int stm32f4_spi_config(struct stm32_spi *spi)
1654 {
1655 unsigned long flags;
1656
1657 spin_lock_irqsave(&spi->lock, flags);
1658
1659 /* Ensure I2SMOD bit is kept cleared */
1660 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1661 STM32F4_SPI_I2SCFGR_I2SMOD);
1662
1663 /*
1664 * - SS input value high
1665 * - transmitter half duplex direction
1666 * - Set the master mode (default Motorola mode)
1667 * - Consider 1 master/n slaves configuration and
1668 * SS input value is determined by the SSI bit
1669 */
1670 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1671 STM32F4_SPI_CR1_BIDIOE |
1672 STM32F4_SPI_CR1_MSTR |
1673 STM32F4_SPI_CR1_SSM);
1674
1675 spin_unlock_irqrestore(&spi->lock, flags);
1676
1677 return 0;
1678 }
1679
1680 /**
1681 * stm32h7_spi_config - Configure SPI controller as SPI master
1682 * @spi: pointer to the spi controller data structure
1683 */
stm32h7_spi_config(struct stm32_spi * spi)1684 static int stm32h7_spi_config(struct stm32_spi *spi)
1685 {
1686 unsigned long flags;
1687
1688 spin_lock_irqsave(&spi->lock, flags);
1689
1690 /* Ensure I2SMOD bit is kept cleared */
1691 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1692 STM32H7_SPI_I2SCFGR_I2SMOD);
1693
1694 /*
1695 * - SS input value high
1696 * - transmitter half duplex direction
1697 * - automatic communication suspend when RX-Fifo is full
1698 */
1699 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI |
1700 STM32H7_SPI_CR1_HDDIR |
1701 STM32H7_SPI_CR1_MASRX);
1702
1703 /*
1704 * - Set the master mode (default Motorola mode)
1705 * - Consider 1 master/n slaves configuration and
1706 * SS input value is determined by the SSI bit
1707 * - keep control of all associated GPIOs
1708 */
1709 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER |
1710 STM32H7_SPI_CFG2_SSM |
1711 STM32H7_SPI_CFG2_AFCNTR);
1712
1713 spin_unlock_irqrestore(&spi->lock, flags);
1714
1715 return 0;
1716 }
1717
1718 static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1719 .regs = &stm32f4_spi_regspec,
1720 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1721 .disable = stm32f4_spi_disable,
1722 .config = stm32f4_spi_config,
1723 .set_bpw = stm32f4_spi_set_bpw,
1724 .set_mode = stm32f4_spi_set_mode,
1725 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start,
1726 .dma_tx_cb = stm32f4_spi_dma_tx_cb,
1727 .dma_rx_cb = stm32_spi_dma_rx_cb,
1728 .transfer_one_irq = stm32f4_spi_transfer_one_irq,
1729 .irq_handler_event = stm32f4_spi_irq_event,
1730 .irq_handler_thread = stm32f4_spi_irq_thread,
1731 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN,
1732 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX,
1733 .has_fifo = false,
1734 };
1735
1736 static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1737 .regs = &stm32h7_spi_regspec,
1738 .get_fifo_size = stm32h7_spi_get_fifo_size,
1739 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1740 .disable = stm32h7_spi_disable,
1741 .config = stm32h7_spi_config,
1742 .set_bpw = stm32h7_spi_set_bpw,
1743 .set_mode = stm32h7_spi_set_mode,
1744 .set_data_idleness = stm32h7_spi_data_idleness,
1745 .set_number_of_data = stm32h7_spi_number_of_data,
1746 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
1747 .dma_rx_cb = stm32_spi_dma_rx_cb,
1748 /*
1749 * dma_tx_cb is not necessary since in case of TX, dma is followed by
1750 * SPI access hence handling is performed within the SPI interrupt
1751 */
1752 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
1753 .irq_handler_thread = stm32h7_spi_irq_thread,
1754 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
1755 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
1756 .has_fifo = true,
1757 };
1758
1759 static const struct of_device_id stm32_spi_of_match[] = {
1760 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1761 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1762 {},
1763 };
1764 MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1765
stm32_spi_probe(struct platform_device * pdev)1766 static int stm32_spi_probe(struct platform_device *pdev)
1767 {
1768 struct spi_master *master;
1769 struct stm32_spi *spi;
1770 struct resource *res;
1771 struct reset_control *rst;
1772 int ret;
1773
1774 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1775 if (!master) {
1776 dev_err(&pdev->dev, "spi master allocation failed\n");
1777 return -ENOMEM;
1778 }
1779 platform_set_drvdata(pdev, master);
1780
1781 spi = spi_master_get_devdata(master);
1782 spi->dev = &pdev->dev;
1783 spi->master = master;
1784 spin_lock_init(&spi->lock);
1785
1786 spi->cfg = (const struct stm32_spi_cfg *)
1787 of_match_device(pdev->dev.driver->of_match_table,
1788 &pdev->dev)->data;
1789
1790 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1791 spi->base = devm_ioremap_resource(&pdev->dev, res);
1792 if (IS_ERR(spi->base))
1793 return PTR_ERR(spi->base);
1794
1795 spi->phys_addr = (dma_addr_t)res->start;
1796
1797 spi->irq = platform_get_irq(pdev, 0);
1798 if (spi->irq <= 0)
1799 return dev_err_probe(&pdev->dev, spi->irq,
1800 "failed to get irq\n");
1801
1802 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1803 spi->cfg->irq_handler_event,
1804 spi->cfg->irq_handler_thread,
1805 IRQF_ONESHOT, pdev->name, master);
1806 if (ret) {
1807 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1808 ret);
1809 return ret;
1810 }
1811
1812 spi->clk = devm_clk_get(&pdev->dev, NULL);
1813 if (IS_ERR(spi->clk)) {
1814 ret = PTR_ERR(spi->clk);
1815 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1816 return ret;
1817 }
1818
1819 ret = clk_prepare_enable(spi->clk);
1820 if (ret) {
1821 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1822 return ret;
1823 }
1824 spi->clk_rate = clk_get_rate(spi->clk);
1825 if (!spi->clk_rate) {
1826 dev_err(&pdev->dev, "clk rate = 0\n");
1827 ret = -EINVAL;
1828 goto err_clk_disable;
1829 }
1830
1831 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
1832 if (rst) {
1833 if (IS_ERR(rst)) {
1834 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
1835 "failed to get reset\n");
1836 goto err_clk_disable;
1837 }
1838
1839 reset_control_assert(rst);
1840 udelay(2);
1841 reset_control_deassert(rst);
1842 }
1843
1844 if (spi->cfg->has_fifo)
1845 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1846
1847 ret = spi->cfg->config(spi);
1848 if (ret) {
1849 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1850 ret);
1851 goto err_clk_disable;
1852 }
1853
1854 master->dev.of_node = pdev->dev.of_node;
1855 master->auto_runtime_pm = true;
1856 master->bus_num = pdev->id;
1857 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
1858 SPI_3WIRE;
1859 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1860 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1861 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1862 master->use_gpio_descriptors = true;
1863 master->prepare_message = stm32_spi_prepare_msg;
1864 master->transfer_one = stm32_spi_transfer_one;
1865 master->unprepare_message = stm32_spi_unprepare_msg;
1866 master->flags = SPI_MASTER_MUST_TX;
1867
1868 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1869 if (IS_ERR(spi->dma_tx)) {
1870 ret = PTR_ERR(spi->dma_tx);
1871 spi->dma_tx = NULL;
1872 if (ret == -EPROBE_DEFER)
1873 goto err_clk_disable;
1874
1875 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1876 } else {
1877 master->dma_tx = spi->dma_tx;
1878 }
1879
1880 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1881 if (IS_ERR(spi->dma_rx)) {
1882 ret = PTR_ERR(spi->dma_rx);
1883 spi->dma_rx = NULL;
1884 if (ret == -EPROBE_DEFER)
1885 goto err_dma_release;
1886
1887 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1888 } else {
1889 master->dma_rx = spi->dma_rx;
1890 }
1891
1892 if (spi->dma_tx || spi->dma_rx)
1893 master->can_dma = stm32_spi_can_dma;
1894
1895 pm_runtime_set_autosuspend_delay(&pdev->dev,
1896 STM32_SPI_AUTOSUSPEND_DELAY);
1897 pm_runtime_use_autosuspend(&pdev->dev);
1898 pm_runtime_set_active(&pdev->dev);
1899 pm_runtime_get_noresume(&pdev->dev);
1900 pm_runtime_enable(&pdev->dev);
1901
1902 ret = spi_register_master(master);
1903 if (ret) {
1904 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1905 ret);
1906 goto err_pm_disable;
1907 }
1908
1909 pm_runtime_mark_last_busy(&pdev->dev);
1910 pm_runtime_put_autosuspend(&pdev->dev);
1911
1912 dev_info(&pdev->dev, "driver initialized\n");
1913
1914 return 0;
1915
1916 err_pm_disable:
1917 pm_runtime_disable(&pdev->dev);
1918 pm_runtime_put_noidle(&pdev->dev);
1919 pm_runtime_set_suspended(&pdev->dev);
1920 pm_runtime_dont_use_autosuspend(&pdev->dev);
1921 err_dma_release:
1922 if (spi->dma_tx)
1923 dma_release_channel(spi->dma_tx);
1924 if (spi->dma_rx)
1925 dma_release_channel(spi->dma_rx);
1926 err_clk_disable:
1927 clk_disable_unprepare(spi->clk);
1928
1929 return ret;
1930 }
1931
stm32_spi_remove(struct platform_device * pdev)1932 static int stm32_spi_remove(struct platform_device *pdev)
1933 {
1934 struct spi_master *master = platform_get_drvdata(pdev);
1935 struct stm32_spi *spi = spi_master_get_devdata(master);
1936
1937 pm_runtime_get_sync(&pdev->dev);
1938
1939 spi_unregister_master(master);
1940 spi->cfg->disable(spi);
1941
1942 pm_runtime_disable(&pdev->dev);
1943 pm_runtime_put_noidle(&pdev->dev);
1944 pm_runtime_set_suspended(&pdev->dev);
1945 pm_runtime_dont_use_autosuspend(&pdev->dev);
1946
1947 if (master->dma_tx)
1948 dma_release_channel(master->dma_tx);
1949 if (master->dma_rx)
1950 dma_release_channel(master->dma_rx);
1951
1952 clk_disable_unprepare(spi->clk);
1953
1954
1955 pinctrl_pm_select_sleep_state(&pdev->dev);
1956
1957 return 0;
1958 }
1959
stm32_spi_runtime_suspend(struct device * dev)1960 static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
1961 {
1962 struct spi_master *master = dev_get_drvdata(dev);
1963 struct stm32_spi *spi = spi_master_get_devdata(master);
1964
1965 clk_disable_unprepare(spi->clk);
1966
1967 return pinctrl_pm_select_sleep_state(dev);
1968 }
1969
stm32_spi_runtime_resume(struct device * dev)1970 static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
1971 {
1972 struct spi_master *master = dev_get_drvdata(dev);
1973 struct stm32_spi *spi = spi_master_get_devdata(master);
1974 int ret;
1975
1976 ret = pinctrl_pm_select_default_state(dev);
1977 if (ret)
1978 return ret;
1979
1980 return clk_prepare_enable(spi->clk);
1981 }
1982
stm32_spi_suspend(struct device * dev)1983 static int __maybe_unused stm32_spi_suspend(struct device *dev)
1984 {
1985 struct spi_master *master = dev_get_drvdata(dev);
1986 int ret;
1987
1988 ret = spi_master_suspend(master);
1989 if (ret)
1990 return ret;
1991
1992 return pm_runtime_force_suspend(dev);
1993 }
1994
stm32_spi_resume(struct device * dev)1995 static int __maybe_unused stm32_spi_resume(struct device *dev)
1996 {
1997 struct spi_master *master = dev_get_drvdata(dev);
1998 struct stm32_spi *spi = spi_master_get_devdata(master);
1999 int ret;
2000
2001 ret = pm_runtime_force_resume(dev);
2002 if (ret)
2003 return ret;
2004
2005 ret = spi_master_resume(master);
2006 if (ret) {
2007 clk_disable_unprepare(spi->clk);
2008 return ret;
2009 }
2010
2011 ret = pm_runtime_get_sync(dev);
2012 if (ret < 0) {
2013 pm_runtime_put_noidle(dev);
2014 dev_err(dev, "Unable to power device:%d\n", ret);
2015 return ret;
2016 }
2017
2018 spi->cfg->config(spi);
2019
2020 pm_runtime_mark_last_busy(dev);
2021 pm_runtime_put_autosuspend(dev);
2022
2023 return 0;
2024 }
2025
2026 static const struct dev_pm_ops stm32_spi_pm_ops = {
2027 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2028 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2029 stm32_spi_runtime_resume, NULL)
2030 };
2031
2032 static struct platform_driver stm32_spi_driver = {
2033 .probe = stm32_spi_probe,
2034 .remove = stm32_spi_remove,
2035 .driver = {
2036 .name = DRIVER_NAME,
2037 .pm = &stm32_spi_pm_ops,
2038 .of_match_table = stm32_spi_of_match,
2039 },
2040 };
2041
2042 module_platform_driver(stm32_spi_driver);
2043
2044 MODULE_ALIAS("platform:" DRIVER_NAME);
2045 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2046 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2047 MODULE_LICENSE("GPL v2");
2048