| /drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | yellow_carp_ppt.c | 788 enum smu_clk_type clk_type, in yellow_carp_get_current_clk_freq()
817 enum smu_clk_type clk_type, in yellow_carp_get_dpm_level_count()
846 enum smu_clk_type clk_type, in yellow_carp_get_dpm_freq_by_index()
890 enum smu_clk_type clk_type) in yellow_carp_clk_dpm_is_enabled()
919 enum smu_clk_type clk_type, in yellow_carp_get_dpm_ultimate_freq()
1029 enum smu_clk_type clk_type, in yellow_carp_set_soft_freq_limited_range()
1075 enum smu_clk_type clk_type, char *buf) in yellow_carp_print_clk_levels()
1127 enum smu_clk_type clk_type, uint32_t mask) in yellow_carp_force_clk_levels()
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| D | smu_v13_0.c | 1009 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v13_0_display_clock_voltage_request() local
1480 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v13_0_get_dpm_ultimate_freq()
1540 enum smu_clk_type clk_type, in smu_v13_0_set_soft_freq_limited_range()
1584 enum smu_clk_type clk_type, in smu_v13_0_set_hard_freq_limited_range()
1744 enum smu_clk_type clk_type, in smu_v13_0_get_dpm_freq_by_index()
1782 enum smu_clk_type clk_type, in smu_v13_0_get_dpm_level_count()
1796 enum smu_clk_type clk_type, in smu_v13_0_set_single_dpm_table()
1834 enum smu_clk_type clk_type, in smu_v13_0_get_dpm_level_range()
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| D | aldebaran_ppt.c | 658 enum smu_clk_type clk_type, in aldebaran_get_current_clk_freq_by_table()
1299 enum smu_clk_type clk_type, in aldebaran_set_soft_freq_limited_range()
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | vangogh_ppt.c | 533 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in vangogh_get_dpm_clk_limited()
577 enum smu_clk_type clk_type, char *buf) in vangogh_print_legacy_clk_levels()
679 enum smu_clk_type clk_type, char *buf) in vangogh_print_clk_levels()
781 enum smu_clk_type clk_type, char *buf) in vangogh_common_print_clk_levels()
856 enum smu_clk_type clk_type) in vangogh_clk_dpm_is_enabled()
888 enum smu_clk_type clk_type, in vangogh_get_dpm_ultimate_freq()
1090 enum smu_clk_type clk_type, in vangogh_set_soft_freq_limited_range()
1172 enum smu_clk_type clk_type, uint32_t mask) in vangogh_force_clk_levels()
1282 enum smu_clk_type clk_type; in vangogh_force_dpm_limit_value() local
1310 enum smu_clk_type clk_type; in vangogh_unforce_dpm_levels() local
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| D | smu_v11_0.c | 1089 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request() local
1732 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v11_0_get_dpm_ultimate_freq()
1792 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range()
1836 enum smu_clk_type clk_type, in smu_v11_0_set_hard_freq_limited_range()
1993 enum smu_clk_type clk_type, in smu_v11_0_get_dpm_freq_by_index()
2031 enum smu_clk_type clk_type, in smu_v11_0_get_dpm_level_count()
2041 enum smu_clk_type clk_type, in smu_v11_0_set_single_dpm_table()
2079 enum smu_clk_type clk_type, in smu_v11_0_get_dpm_level_range()
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| D | cyan_skillfish_ppt.c | 275 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq()
306 enum smu_clk_type clk_type, in cyan_skillfish_print_clk_levels()
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| D | sienna_cichlid_ppt.c | 1006 enum smu_clk_type clk_type, in sienna_cichlid_get_current_clk_freq_by_table()
1056 …ool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in sienna_cichlid_is_support_fine_grained_dpm()
1089 enum smu_clk_type clk_type, char *buf) in sienna_cichlid_print_clk_levels()
1265 enum smu_clk_type clk_type, uint32_t mask) in sienna_cichlid_force_clk_levels()
2032 enum smu_clk_type clk_type, in sienna_cichlid_get_dpm_ultimate_freq()
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| D | navi10_ppt.c | 1194 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table()
1234 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in navi10_is_support_fine_grained_dpm()
1265 enum smu_clk_type clk_type, char *buf) in navi10_print_clk_levels()
1454 enum smu_clk_type clk_type, uint32_t mask) in navi10_force_clk_levels()
1591 enum smu_clk_type clk_type, in navi10_get_clock_by_type_with_latency()
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| D | arcturus_ppt.c | 699 enum smu_clk_type clk_type, in arcturus_get_current_clk_freq_by_table()
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| /drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| D | renoir_ppt.c | 193 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in renoir_get_dpm_clk_limited()
272 enum smu_clk_type clk_type, in renoir_get_dpm_ultimate_freq()
486 enum smu_clk_type clk_type, char *buf) in renoir_print_clk_levels()
688 enum smu_clk_type clk_type; in renoir_force_dpm_limit_value() local
715 enum smu_clk_type clk_type; in renoir_unforce_dpm_levels() local
718 enum smu_clk_type clk_type; in renoir_unforce_dpm_levels() member
789 enum smu_clk_type clk_type, uint32_t mask) in renoir_force_clk_levels()
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| D | smu_v12_0.c | 212 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v12_0_set_soft_freq_limited_range()
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| /drivers/clk/imx/ |
| D | clk-scu.h | 51 u8 clk_type) in imx_clk_scu()
57 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2()
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| D | clk-scu.c | 31 u8 clk_type; member
50 u8 clk_type; member
452 u32 rsrc_id, u8 clk_type) in __imx_clk_scu()
658 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu_alloc_dev()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_pp_smu.c | 114 enum dm_pp_clock_type clk_type, in get_default_clock_levels()
297 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type()
369 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_latency()
393 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_voltage()
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| /drivers/gpu/drm/amd/pm/swsmu/ |
| D | amdgpu_smu.c | 117 enum smu_clk_type clk_type, in smu_set_soft_freq_range()
137 enum smu_clk_type clk_type, in smu_get_dpm_freq_range()
387 enum smu_clk_type clk_type; in smu_restore_dpm_user_profile() local
1895 enum smu_clk_type clk_type, in smu_force_smuclk_levels()
1929 enum smu_clk_type clk_type; in smu_force_ppclk_levels() local
2339 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) in smu_print_smuclk_levels()
2361 enum smu_clk_type clk_type; in smu_print_ppclk_levels() local
2667 enum smu_clk_type clk_type; in smu_get_clock_by_type_with_latency() local
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| D | smu_cmn.c | 502 enum smu_clk_type clk_type) in smu_cmn_clk_dpm_is_enabled()
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| /drivers/nfc/s3fwrn5/ |
| D | nci.h | 44 __u8 clk_type; member
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| /drivers/phy/ |
| D | phy-xgene.c | 534 enum clk_type_t clk_type; /* Input clock selection */ member
705 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type()
759 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core()
1136 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk()
1236 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco()
1253 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata()
1317 enum clk_type_t clk_type, in xgene_phy_hw_initialize()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dm_services_types.h | 82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ argument
254 enum dm_pp_clock_type clk_type; member
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| /drivers/input/ |
| D | evdev.c | 50 enum input_clock_type clk_type; member
178 enum input_clock_type clk_type; in evdev_set_clk_type() local
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_crtc.c | 527 u32 freq, u8 clk_type, u8 clk_src) in amdgpu_atombios_crtc_set_dce_clock()
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| /drivers/clk/zynqmp/ |
| D | clkc.c | 42 enum clk_type { enum
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu10_hwmgr.c | 55 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu10_display_clock_voltage_request() local
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| D | vega12_hwmgr.c | 1547 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega12_display_clock_voltage_request() local
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| /drivers/media/dvb-frontends/ |
| D | mxl5xx.c | 1391 u32 clk_type = 0; in config_ts() local
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