1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "soc15_common.h"
35 #include "smu_v11_0.h"
36 #include "smu11_driver_if_navi10.h"
37 #include "atom.h"
38 #include "navi10_ppt.h"
39 #include "smu_v11_0_pptable.h"
40 #include "smu_v11_0_ppsmc.h"
41 #include "nbio/nbio_2_3_offset.h"
42 #include "nbio/nbio_2_3_sh_mask.h"
43 #include "thm/thm_11_0_2_offset.h"
44 #include "thm/thm_11_0_2_sh_mask.h"
45
46 #include "asic_reg/mp/mp_11_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "smu_11_0_cdr_table.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
72
73 #define SMU_11_0_GFX_BUSY_THRESHOLD 15
74
75 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
79 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
80 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
81 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
82 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
83 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0),
84 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0),
85 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
86 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
89 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
98 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
99 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0),
100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
108 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0),
109 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
110 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
111 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
112 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
113 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0),
114 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
115 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
116 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
117 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
118 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
119 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
120 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
121 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
122 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0),
123 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0),
124 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
125 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
126 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
127 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
128 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
129 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
130 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
131 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
132 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
133 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
134 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
135 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
136 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
137 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
138 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
139 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
140 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange, 0),
141 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
142 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
143 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
146 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
147 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0),
148 };
149
150 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(SCLK, PPCLK_GFXCLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(FCLK, PPCLK_SOCCLK),
155 CLK_MAP(UCLK, PPCLK_UCLK),
156 CLK_MAP(MCLK, PPCLK_UCLK),
157 CLK_MAP(DCLK, PPCLK_DCLK),
158 CLK_MAP(VCLK, PPCLK_VCLK),
159 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
160 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
161 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
162 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
163 };
164
165 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
166 FEA_MAP(DPM_PREFETCHER),
167 FEA_MAP(DPM_GFXCLK),
168 FEA_MAP(DPM_GFX_PACE),
169 FEA_MAP(DPM_UCLK),
170 FEA_MAP(DPM_SOCCLK),
171 FEA_MAP(DPM_MP0CLK),
172 FEA_MAP(DPM_LINK),
173 FEA_MAP(DPM_DCEFCLK),
174 FEA_MAP(MEM_VDDCI_SCALING),
175 FEA_MAP(MEM_MVDD_SCALING),
176 FEA_MAP(DS_GFXCLK),
177 FEA_MAP(DS_SOCCLK),
178 FEA_MAP(DS_LCLK),
179 FEA_MAP(DS_DCEFCLK),
180 FEA_MAP(DS_UCLK),
181 FEA_MAP(GFX_ULV),
182 FEA_MAP(FW_DSTATE),
183 FEA_MAP(GFXOFF),
184 FEA_MAP(BACO),
185 FEA_MAP(VCN_PG),
186 FEA_MAP(JPEG_PG),
187 FEA_MAP(USB_PG),
188 FEA_MAP(RSMU_SMN_CG),
189 FEA_MAP(PPT),
190 FEA_MAP(TDC),
191 FEA_MAP(GFX_EDC),
192 FEA_MAP(APCC_PLUS),
193 FEA_MAP(GTHR),
194 FEA_MAP(ACDC),
195 FEA_MAP(VR0HOT),
196 FEA_MAP(VR1HOT),
197 FEA_MAP(FW_CTF),
198 FEA_MAP(FAN_CONTROL),
199 FEA_MAP(THERMAL),
200 FEA_MAP(GFX_DCS),
201 FEA_MAP(RM),
202 FEA_MAP(LED_DISPLAY),
203 FEA_MAP(GFX_SS),
204 FEA_MAP(OUT_OF_BAND_MONITOR),
205 FEA_MAP(TEMP_DEPENDENT_VMIN),
206 FEA_MAP(MMHUB_PG),
207 FEA_MAP(ATHUB_PG),
208 FEA_MAP(APCC_DFLL),
209 };
210
211 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
212 TAB_MAP(PPTABLE),
213 TAB_MAP(WATERMARKS),
214 TAB_MAP(AVFS),
215 TAB_MAP(AVFS_PSM_DEBUG),
216 TAB_MAP(AVFS_FUSE_OVERRIDE),
217 TAB_MAP(PMSTATUSLOG),
218 TAB_MAP(SMU_METRICS),
219 TAB_MAP(DRIVER_SMU_CONFIG),
220 TAB_MAP(ACTIVITY_MONITOR_COEFF),
221 TAB_MAP(OVERDRIVE),
222 TAB_MAP(I2C_COMMANDS),
223 TAB_MAP(PACE),
224 };
225
226 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
227 PWR_MAP(AC),
228 PWR_MAP(DC),
229 };
230
231 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
239 };
240
241 static const uint8_t navi1x_throttler_map[] = {
242 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
243 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
244 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
245 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
246 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
247 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
248 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
249 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
250 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
251 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
252 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
253 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
254 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
255 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
256 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
257 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
258 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
259 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
260 };
261
262
is_asic_secure(struct smu_context * smu)263 static bool is_asic_secure(struct smu_context *smu)
264 {
265 struct amdgpu_device *adev = smu->adev;
266 bool is_secure = true;
267 uint32_t mp0_fw_intf;
268
269 mp0_fw_intf = RREG32_PCIE(MP0_Public |
270 (smnMP0_FW_INTF & 0xffffffff));
271
272 if (!(mp0_fw_intf & (1 << 19)))
273 is_secure = false;
274
275 return is_secure;
276 }
277
278 static int
navi10_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)279 navi10_get_allowed_feature_mask(struct smu_context *smu,
280 uint32_t *feature_mask, uint32_t num)
281 {
282 struct amdgpu_device *adev = smu->adev;
283
284 if (num > 2)
285 return -EINVAL;
286
287 memset(feature_mask, 0, sizeof(uint32_t) * num);
288
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
290 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
291 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
292 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
293 | FEATURE_MASK(FEATURE_PPT_BIT)
294 | FEATURE_MASK(FEATURE_TDC_BIT)
295 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
296 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
297 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
298 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
299 | FEATURE_MASK(FEATURE_THERMAL_BIT)
300 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
301 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
302 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
303 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
304 | FEATURE_MASK(FEATURE_BACO_BIT)
305 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
306 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
307 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
308 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
309
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312
313 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
315
316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
318
319 if (adev->pm.pp_feature & PP_ULV_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
321
322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
324
325 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
327
328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
330
331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
333
334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
336
337 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
339
340 if (smu->dc_controlled_by_gpio)
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
342
343 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
345
346 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
347 if (!(is_asic_secure(smu) &&
348 (adev->asic_type == CHIP_NAVI10) &&
349 (adev->rev_id == 0)) &&
350 (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
352 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
353 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
354
355 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
356 if (is_asic_secure(smu) &&
357 (adev->asic_type == CHIP_NAVI10) &&
358 (adev->rev_id == 0))
359 *(uint64_t *)feature_mask &=
360 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
361
362 return 0;
363 }
364
navi10_check_bxco_support(struct smu_context * smu)365 static void navi10_check_bxco_support(struct smu_context *smu)
366 {
367 struct smu_table_context *table_context = &smu->smu_table;
368 struct smu_11_0_powerplay_table *powerplay_table =
369 table_context->power_play_table;
370 struct smu_baco_context *smu_baco = &smu->smu_baco;
371 struct amdgpu_device *adev = smu->adev;
372 uint32_t val;
373
374 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
375 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
376 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
377 smu_baco->platform_support =
378 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
379 false;
380 }
381 }
382
navi10_check_powerplay_table(struct smu_context * smu)383 static int navi10_check_powerplay_table(struct smu_context *smu)
384 {
385 struct smu_table_context *table_context = &smu->smu_table;
386 struct smu_11_0_powerplay_table *powerplay_table =
387 table_context->power_play_table;
388
389 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
390 smu->dc_controlled_by_gpio = true;
391
392 navi10_check_bxco_support(smu);
393
394 table_context->thermal_controller_type =
395 powerplay_table->thermal_controller_type;
396
397 /*
398 * Instead of having its own buffer space and get overdrive_table copied,
399 * smu->od_settings just points to the actual overdrive_table
400 */
401 smu->od_settings = &powerplay_table->overdrive_table;
402
403 return 0;
404 }
405
navi10_append_powerplay_table(struct smu_context * smu)406 static int navi10_append_powerplay_table(struct smu_context *smu)
407 {
408 struct amdgpu_device *adev = smu->adev;
409 struct smu_table_context *table_context = &smu->smu_table;
410 PPTable_t *smc_pptable = table_context->driver_pptable;
411 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
412 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
413 int index, ret;
414
415 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
416 smc_dpm_info);
417
418 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
419 (uint8_t **)&smc_dpm_table);
420 if (ret)
421 return ret;
422
423 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
424 smc_dpm_table->table_header.format_revision,
425 smc_dpm_table->table_header.content_revision);
426
427 if (smc_dpm_table->table_header.format_revision != 4) {
428 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
429 return -EINVAL;
430 }
431
432 switch (smc_dpm_table->table_header.content_revision) {
433 case 5: /* nv10 and nv14 */
434 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
435 smc_dpm_table, I2cControllers);
436 break;
437 case 7: /* nv12 */
438 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
439 (uint8_t **)&smc_dpm_table_v4_7);
440 if (ret)
441 return ret;
442 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
443 smc_dpm_table_v4_7, I2cControllers);
444 break;
445 default:
446 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
447 smc_dpm_table->table_header.content_revision);
448 return -EINVAL;
449 }
450
451 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
452 /* TODO: remove it once SMU fw fix it */
453 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
454 }
455
456 return 0;
457 }
458
navi10_store_powerplay_table(struct smu_context * smu)459 static int navi10_store_powerplay_table(struct smu_context *smu)
460 {
461 struct smu_table_context *table_context = &smu->smu_table;
462 struct smu_11_0_powerplay_table *powerplay_table =
463 table_context->power_play_table;
464
465 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
466 sizeof(PPTable_t));
467
468 return 0;
469 }
470
navi10_setup_pptable(struct smu_context * smu)471 static int navi10_setup_pptable(struct smu_context *smu)
472 {
473 int ret = 0;
474
475 ret = smu_v11_0_setup_pptable(smu);
476 if (ret)
477 return ret;
478
479 ret = navi10_store_powerplay_table(smu);
480 if (ret)
481 return ret;
482
483 ret = navi10_append_powerplay_table(smu);
484 if (ret)
485 return ret;
486
487 ret = navi10_check_powerplay_table(smu);
488 if (ret)
489 return ret;
490
491 return ret;
492 }
493
navi10_tables_init(struct smu_context * smu)494 static int navi10_tables_init(struct smu_context *smu)
495 {
496 struct smu_table_context *smu_table = &smu->smu_table;
497 struct smu_table *tables = smu_table->tables;
498
499 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
500 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
501 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t),
504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
505 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
507 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
509 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
511 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
512 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
513 AMDGPU_GEM_DOMAIN_VRAM);
514
515 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t),
516 GFP_KERNEL);
517 if (!smu_table->metrics_table)
518 goto err0_out;
519 smu_table->metrics_time = 0;
520
521 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
522 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
523 if (!smu_table->gpu_metrics_table)
524 goto err1_out;
525
526 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
527 if (!smu_table->watermarks_table)
528 goto err2_out;
529
530 return 0;
531
532 err2_out:
533 kfree(smu_table->gpu_metrics_table);
534 err1_out:
535 kfree(smu_table->metrics_table);
536 err0_out:
537 return -ENOMEM;
538 }
539
navi10_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)540 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
541 MetricsMember_t member,
542 uint32_t *value)
543 {
544 struct smu_table_context *smu_table= &smu->smu_table;
545 SmuMetrics_legacy_t *metrics =
546 (SmuMetrics_legacy_t *)smu_table->metrics_table;
547 int ret = 0;
548
549 mutex_lock(&smu->metrics_lock);
550
551 ret = smu_cmn_get_metrics_table_locked(smu,
552 NULL,
553 false);
554 if (ret) {
555 mutex_unlock(&smu->metrics_lock);
556 return ret;
557 }
558
559 switch (member) {
560 case METRICS_CURR_GFXCLK:
561 *value = metrics->CurrClock[PPCLK_GFXCLK];
562 break;
563 case METRICS_CURR_SOCCLK:
564 *value = metrics->CurrClock[PPCLK_SOCCLK];
565 break;
566 case METRICS_CURR_UCLK:
567 *value = metrics->CurrClock[PPCLK_UCLK];
568 break;
569 case METRICS_CURR_VCLK:
570 *value = metrics->CurrClock[PPCLK_VCLK];
571 break;
572 case METRICS_CURR_DCLK:
573 *value = metrics->CurrClock[PPCLK_DCLK];
574 break;
575 case METRICS_CURR_DCEFCLK:
576 *value = metrics->CurrClock[PPCLK_DCEFCLK];
577 break;
578 case METRICS_AVERAGE_GFXCLK:
579 *value = metrics->AverageGfxclkFrequency;
580 break;
581 case METRICS_AVERAGE_SOCCLK:
582 *value = metrics->AverageSocclkFrequency;
583 break;
584 case METRICS_AVERAGE_UCLK:
585 *value = metrics->AverageUclkFrequency;
586 break;
587 case METRICS_AVERAGE_GFXACTIVITY:
588 *value = metrics->AverageGfxActivity;
589 break;
590 case METRICS_AVERAGE_MEMACTIVITY:
591 *value = metrics->AverageUclkActivity;
592 break;
593 case METRICS_AVERAGE_SOCKETPOWER:
594 *value = metrics->AverageSocketPower << 8;
595 break;
596 case METRICS_TEMPERATURE_EDGE:
597 *value = metrics->TemperatureEdge *
598 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
599 break;
600 case METRICS_TEMPERATURE_HOTSPOT:
601 *value = metrics->TemperatureHotspot *
602 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
603 break;
604 case METRICS_TEMPERATURE_MEM:
605 *value = metrics->TemperatureMem *
606 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
607 break;
608 case METRICS_TEMPERATURE_VRGFX:
609 *value = metrics->TemperatureVrGfx *
610 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
611 break;
612 case METRICS_TEMPERATURE_VRSOC:
613 *value = metrics->TemperatureVrSoc *
614 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
615 break;
616 case METRICS_THROTTLER_STATUS:
617 *value = metrics->ThrottlerStatus;
618 break;
619 case METRICS_CURR_FANSPEED:
620 *value = metrics->CurrFanSpeed;
621 break;
622 default:
623 *value = UINT_MAX;
624 break;
625 }
626
627 mutex_unlock(&smu->metrics_lock);
628
629 return ret;
630 }
631
navi10_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)632 static int navi10_get_smu_metrics_data(struct smu_context *smu,
633 MetricsMember_t member,
634 uint32_t *value)
635 {
636 struct smu_table_context *smu_table= &smu->smu_table;
637 SmuMetrics_t *metrics =
638 (SmuMetrics_t *)smu_table->metrics_table;
639 int ret = 0;
640
641 mutex_lock(&smu->metrics_lock);
642
643 ret = smu_cmn_get_metrics_table_locked(smu,
644 NULL,
645 false);
646 if (ret) {
647 mutex_unlock(&smu->metrics_lock);
648 return ret;
649 }
650
651 switch (member) {
652 case METRICS_CURR_GFXCLK:
653 *value = metrics->CurrClock[PPCLK_GFXCLK];
654 break;
655 case METRICS_CURR_SOCCLK:
656 *value = metrics->CurrClock[PPCLK_SOCCLK];
657 break;
658 case METRICS_CURR_UCLK:
659 *value = metrics->CurrClock[PPCLK_UCLK];
660 break;
661 case METRICS_CURR_VCLK:
662 *value = metrics->CurrClock[PPCLK_VCLK];
663 break;
664 case METRICS_CURR_DCLK:
665 *value = metrics->CurrClock[PPCLK_DCLK];
666 break;
667 case METRICS_CURR_DCEFCLK:
668 *value = metrics->CurrClock[PPCLK_DCEFCLK];
669 break;
670 case METRICS_AVERAGE_GFXCLK:
671 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
672 *value = metrics->AverageGfxclkFrequencyPreDs;
673 else
674 *value = metrics->AverageGfxclkFrequencyPostDs;
675 break;
676 case METRICS_AVERAGE_SOCCLK:
677 *value = metrics->AverageSocclkFrequency;
678 break;
679 case METRICS_AVERAGE_UCLK:
680 *value = metrics->AverageUclkFrequencyPostDs;
681 break;
682 case METRICS_AVERAGE_GFXACTIVITY:
683 *value = metrics->AverageGfxActivity;
684 break;
685 case METRICS_AVERAGE_MEMACTIVITY:
686 *value = metrics->AverageUclkActivity;
687 break;
688 case METRICS_AVERAGE_SOCKETPOWER:
689 *value = metrics->AverageSocketPower << 8;
690 break;
691 case METRICS_TEMPERATURE_EDGE:
692 *value = metrics->TemperatureEdge *
693 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
694 break;
695 case METRICS_TEMPERATURE_HOTSPOT:
696 *value = metrics->TemperatureHotspot *
697 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
698 break;
699 case METRICS_TEMPERATURE_MEM:
700 *value = metrics->TemperatureMem *
701 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
702 break;
703 case METRICS_TEMPERATURE_VRGFX:
704 *value = metrics->TemperatureVrGfx *
705 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
706 break;
707 case METRICS_TEMPERATURE_VRSOC:
708 *value = metrics->TemperatureVrSoc *
709 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
710 break;
711 case METRICS_THROTTLER_STATUS:
712 *value = metrics->ThrottlerStatus;
713 break;
714 case METRICS_CURR_FANSPEED:
715 *value = metrics->CurrFanSpeed;
716 break;
717 default:
718 *value = UINT_MAX;
719 break;
720 }
721
722 mutex_unlock(&smu->metrics_lock);
723
724 return ret;
725 }
726
navi12_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)727 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu,
728 MetricsMember_t member,
729 uint32_t *value)
730 {
731 struct smu_table_context *smu_table= &smu->smu_table;
732 SmuMetrics_NV12_legacy_t *metrics =
733 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
734 int ret = 0;
735
736 mutex_lock(&smu->metrics_lock);
737
738 ret = smu_cmn_get_metrics_table_locked(smu,
739 NULL,
740 false);
741 if (ret) {
742 mutex_unlock(&smu->metrics_lock);
743 return ret;
744 }
745
746 switch (member) {
747 case METRICS_CURR_GFXCLK:
748 *value = metrics->CurrClock[PPCLK_GFXCLK];
749 break;
750 case METRICS_CURR_SOCCLK:
751 *value = metrics->CurrClock[PPCLK_SOCCLK];
752 break;
753 case METRICS_CURR_UCLK:
754 *value = metrics->CurrClock[PPCLK_UCLK];
755 break;
756 case METRICS_CURR_VCLK:
757 *value = metrics->CurrClock[PPCLK_VCLK];
758 break;
759 case METRICS_CURR_DCLK:
760 *value = metrics->CurrClock[PPCLK_DCLK];
761 break;
762 case METRICS_CURR_DCEFCLK:
763 *value = metrics->CurrClock[PPCLK_DCEFCLK];
764 break;
765 case METRICS_AVERAGE_GFXCLK:
766 *value = metrics->AverageGfxclkFrequency;
767 break;
768 case METRICS_AVERAGE_SOCCLK:
769 *value = metrics->AverageSocclkFrequency;
770 break;
771 case METRICS_AVERAGE_UCLK:
772 *value = metrics->AverageUclkFrequency;
773 break;
774 case METRICS_AVERAGE_GFXACTIVITY:
775 *value = metrics->AverageGfxActivity;
776 break;
777 case METRICS_AVERAGE_MEMACTIVITY:
778 *value = metrics->AverageUclkActivity;
779 break;
780 case METRICS_AVERAGE_SOCKETPOWER:
781 *value = metrics->AverageSocketPower << 8;
782 break;
783 case METRICS_TEMPERATURE_EDGE:
784 *value = metrics->TemperatureEdge *
785 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
786 break;
787 case METRICS_TEMPERATURE_HOTSPOT:
788 *value = metrics->TemperatureHotspot *
789 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
790 break;
791 case METRICS_TEMPERATURE_MEM:
792 *value = metrics->TemperatureMem *
793 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
794 break;
795 case METRICS_TEMPERATURE_VRGFX:
796 *value = metrics->TemperatureVrGfx *
797 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
798 break;
799 case METRICS_TEMPERATURE_VRSOC:
800 *value = metrics->TemperatureVrSoc *
801 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
802 break;
803 case METRICS_THROTTLER_STATUS:
804 *value = metrics->ThrottlerStatus;
805 break;
806 case METRICS_CURR_FANSPEED:
807 *value = metrics->CurrFanSpeed;
808 break;
809 default:
810 *value = UINT_MAX;
811 break;
812 }
813
814 mutex_unlock(&smu->metrics_lock);
815
816 return ret;
817 }
818
navi12_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)819 static int navi12_get_smu_metrics_data(struct smu_context *smu,
820 MetricsMember_t member,
821 uint32_t *value)
822 {
823 struct smu_table_context *smu_table= &smu->smu_table;
824 SmuMetrics_NV12_t *metrics =
825 (SmuMetrics_NV12_t *)smu_table->metrics_table;
826 int ret = 0;
827
828 mutex_lock(&smu->metrics_lock);
829
830 ret = smu_cmn_get_metrics_table_locked(smu,
831 NULL,
832 false);
833 if (ret) {
834 mutex_unlock(&smu->metrics_lock);
835 return ret;
836 }
837
838 switch (member) {
839 case METRICS_CURR_GFXCLK:
840 *value = metrics->CurrClock[PPCLK_GFXCLK];
841 break;
842 case METRICS_CURR_SOCCLK:
843 *value = metrics->CurrClock[PPCLK_SOCCLK];
844 break;
845 case METRICS_CURR_UCLK:
846 *value = metrics->CurrClock[PPCLK_UCLK];
847 break;
848 case METRICS_CURR_VCLK:
849 *value = metrics->CurrClock[PPCLK_VCLK];
850 break;
851 case METRICS_CURR_DCLK:
852 *value = metrics->CurrClock[PPCLK_DCLK];
853 break;
854 case METRICS_CURR_DCEFCLK:
855 *value = metrics->CurrClock[PPCLK_DCEFCLK];
856 break;
857 case METRICS_AVERAGE_GFXCLK:
858 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
859 *value = metrics->AverageGfxclkFrequencyPreDs;
860 else
861 *value = metrics->AverageGfxclkFrequencyPostDs;
862 break;
863 case METRICS_AVERAGE_SOCCLK:
864 *value = metrics->AverageSocclkFrequency;
865 break;
866 case METRICS_AVERAGE_UCLK:
867 *value = metrics->AverageUclkFrequencyPostDs;
868 break;
869 case METRICS_AVERAGE_GFXACTIVITY:
870 *value = metrics->AverageGfxActivity;
871 break;
872 case METRICS_AVERAGE_MEMACTIVITY:
873 *value = metrics->AverageUclkActivity;
874 break;
875 case METRICS_AVERAGE_SOCKETPOWER:
876 *value = metrics->AverageSocketPower << 8;
877 break;
878 case METRICS_TEMPERATURE_EDGE:
879 *value = metrics->TemperatureEdge *
880 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
881 break;
882 case METRICS_TEMPERATURE_HOTSPOT:
883 *value = metrics->TemperatureHotspot *
884 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
885 break;
886 case METRICS_TEMPERATURE_MEM:
887 *value = metrics->TemperatureMem *
888 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
889 break;
890 case METRICS_TEMPERATURE_VRGFX:
891 *value = metrics->TemperatureVrGfx *
892 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
893 break;
894 case METRICS_TEMPERATURE_VRSOC:
895 *value = metrics->TemperatureVrSoc *
896 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
897 break;
898 case METRICS_THROTTLER_STATUS:
899 *value = metrics->ThrottlerStatus;
900 break;
901 case METRICS_CURR_FANSPEED:
902 *value = metrics->CurrFanSpeed;
903 break;
904 default:
905 *value = UINT_MAX;
906 break;
907 }
908
909 mutex_unlock(&smu->metrics_lock);
910
911 return ret;
912 }
913
navi1x_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)914 static int navi1x_get_smu_metrics_data(struct smu_context *smu,
915 MetricsMember_t member,
916 uint32_t *value)
917 {
918 struct amdgpu_device *adev = smu->adev;
919 uint32_t smu_version;
920 int ret = 0;
921
922 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
923 if (ret) {
924 dev_err(adev->dev, "Failed to get smu version!\n");
925 return ret;
926 }
927
928 switch (adev->asic_type) {
929 case CHIP_NAVI12:
930 if (smu_version > 0x00341C00)
931 ret = navi12_get_smu_metrics_data(smu, member, value);
932 else
933 ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
934 break;
935 case CHIP_NAVI10:
936 case CHIP_NAVI14:
937 default:
938 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
939 ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
940 ret = navi10_get_smu_metrics_data(smu, member, value);
941 else
942 ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
943 break;
944 }
945
946 return ret;
947 }
948
navi10_allocate_dpm_context(struct smu_context * smu)949 static int navi10_allocate_dpm_context(struct smu_context *smu)
950 {
951 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
952
953 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
954 GFP_KERNEL);
955 if (!smu_dpm->dpm_context)
956 return -ENOMEM;
957
958 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
959
960 return 0;
961 }
962
navi10_init_smc_tables(struct smu_context * smu)963 static int navi10_init_smc_tables(struct smu_context *smu)
964 {
965 int ret = 0;
966
967 ret = navi10_tables_init(smu);
968 if (ret)
969 return ret;
970
971 ret = navi10_allocate_dpm_context(smu);
972 if (ret)
973 return ret;
974
975 return smu_v11_0_init_smc_tables(smu);
976 }
977
navi10_set_default_dpm_table(struct smu_context * smu)978 static int navi10_set_default_dpm_table(struct smu_context *smu)
979 {
980 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
981 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
982 struct smu_11_0_dpm_table *dpm_table;
983 int ret = 0;
984
985 /* socclk dpm table setup */
986 dpm_table = &dpm_context->dpm_tables.soc_table;
987 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
988 ret = smu_v11_0_set_single_dpm_table(smu,
989 SMU_SOCCLK,
990 dpm_table);
991 if (ret)
992 return ret;
993 dpm_table->is_fine_grained =
994 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
995 } else {
996 dpm_table->count = 1;
997 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
998 dpm_table->dpm_levels[0].enabled = true;
999 dpm_table->min = dpm_table->dpm_levels[0].value;
1000 dpm_table->max = dpm_table->dpm_levels[0].value;
1001 }
1002
1003 /* gfxclk dpm table setup */
1004 dpm_table = &dpm_context->dpm_tables.gfx_table;
1005 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1006 ret = smu_v11_0_set_single_dpm_table(smu,
1007 SMU_GFXCLK,
1008 dpm_table);
1009 if (ret)
1010 return ret;
1011 dpm_table->is_fine_grained =
1012 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
1013 } else {
1014 dpm_table->count = 1;
1015 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1016 dpm_table->dpm_levels[0].enabled = true;
1017 dpm_table->min = dpm_table->dpm_levels[0].value;
1018 dpm_table->max = dpm_table->dpm_levels[0].value;
1019 }
1020
1021 /* uclk dpm table setup */
1022 dpm_table = &dpm_context->dpm_tables.uclk_table;
1023 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1024 ret = smu_v11_0_set_single_dpm_table(smu,
1025 SMU_UCLK,
1026 dpm_table);
1027 if (ret)
1028 return ret;
1029 dpm_table->is_fine_grained =
1030 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
1031 } else {
1032 dpm_table->count = 1;
1033 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1034 dpm_table->dpm_levels[0].enabled = true;
1035 dpm_table->min = dpm_table->dpm_levels[0].value;
1036 dpm_table->max = dpm_table->dpm_levels[0].value;
1037 }
1038
1039 /* vclk dpm table setup */
1040 dpm_table = &dpm_context->dpm_tables.vclk_table;
1041 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1042 ret = smu_v11_0_set_single_dpm_table(smu,
1043 SMU_VCLK,
1044 dpm_table);
1045 if (ret)
1046 return ret;
1047 dpm_table->is_fine_grained =
1048 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
1049 } else {
1050 dpm_table->count = 1;
1051 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1052 dpm_table->dpm_levels[0].enabled = true;
1053 dpm_table->min = dpm_table->dpm_levels[0].value;
1054 dpm_table->max = dpm_table->dpm_levels[0].value;
1055 }
1056
1057 /* dclk dpm table setup */
1058 dpm_table = &dpm_context->dpm_tables.dclk_table;
1059 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1060 ret = smu_v11_0_set_single_dpm_table(smu,
1061 SMU_DCLK,
1062 dpm_table);
1063 if (ret)
1064 return ret;
1065 dpm_table->is_fine_grained =
1066 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
1067 } else {
1068 dpm_table->count = 1;
1069 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1070 dpm_table->dpm_levels[0].enabled = true;
1071 dpm_table->min = dpm_table->dpm_levels[0].value;
1072 dpm_table->max = dpm_table->dpm_levels[0].value;
1073 }
1074
1075 /* dcefclk dpm table setup */
1076 dpm_table = &dpm_context->dpm_tables.dcef_table;
1077 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1078 ret = smu_v11_0_set_single_dpm_table(smu,
1079 SMU_DCEFCLK,
1080 dpm_table);
1081 if (ret)
1082 return ret;
1083 dpm_table->is_fine_grained =
1084 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
1085 } else {
1086 dpm_table->count = 1;
1087 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1088 dpm_table->dpm_levels[0].enabled = true;
1089 dpm_table->min = dpm_table->dpm_levels[0].value;
1090 dpm_table->max = dpm_table->dpm_levels[0].value;
1091 }
1092
1093 /* pixelclk dpm table setup */
1094 dpm_table = &dpm_context->dpm_tables.pixel_table;
1095 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1096 ret = smu_v11_0_set_single_dpm_table(smu,
1097 SMU_PIXCLK,
1098 dpm_table);
1099 if (ret)
1100 return ret;
1101 dpm_table->is_fine_grained =
1102 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
1103 } else {
1104 dpm_table->count = 1;
1105 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1106 dpm_table->dpm_levels[0].enabled = true;
1107 dpm_table->min = dpm_table->dpm_levels[0].value;
1108 dpm_table->max = dpm_table->dpm_levels[0].value;
1109 }
1110
1111 /* displayclk dpm table setup */
1112 dpm_table = &dpm_context->dpm_tables.display_table;
1113 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1114 ret = smu_v11_0_set_single_dpm_table(smu,
1115 SMU_DISPCLK,
1116 dpm_table);
1117 if (ret)
1118 return ret;
1119 dpm_table->is_fine_grained =
1120 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
1121 } else {
1122 dpm_table->count = 1;
1123 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1124 dpm_table->dpm_levels[0].enabled = true;
1125 dpm_table->min = dpm_table->dpm_levels[0].value;
1126 dpm_table->max = dpm_table->dpm_levels[0].value;
1127 }
1128
1129 /* phyclk dpm table setup */
1130 dpm_table = &dpm_context->dpm_tables.phy_table;
1131 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1132 ret = smu_v11_0_set_single_dpm_table(smu,
1133 SMU_PHYCLK,
1134 dpm_table);
1135 if (ret)
1136 return ret;
1137 dpm_table->is_fine_grained =
1138 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
1139 } else {
1140 dpm_table->count = 1;
1141 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1142 dpm_table->dpm_levels[0].enabled = true;
1143 dpm_table->min = dpm_table->dpm_levels[0].value;
1144 dpm_table->max = dpm_table->dpm_levels[0].value;
1145 }
1146
1147 return 0;
1148 }
1149
navi10_dpm_set_vcn_enable(struct smu_context * smu,bool enable)1150 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1151 {
1152 int ret = 0;
1153
1154 if (enable) {
1155 /* vcn dpm on is a prerequisite for vcn power gate messages */
1156 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1157 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
1158 if (ret)
1159 return ret;
1160 }
1161 } else {
1162 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1163 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
1164 if (ret)
1165 return ret;
1166 }
1167 }
1168
1169 return ret;
1170 }
1171
navi10_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)1172 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1173 {
1174 int ret = 0;
1175
1176 if (enable) {
1177 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1178 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
1179 if (ret)
1180 return ret;
1181 }
1182 } else {
1183 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1184 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
1185 if (ret)
1186 return ret;
1187 }
1188 }
1189
1190 return ret;
1191 }
1192
navi10_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1193 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
1194 enum smu_clk_type clk_type,
1195 uint32_t *value)
1196 {
1197 MetricsMember_t member_type;
1198 int clk_id = 0;
1199
1200 clk_id = smu_cmn_to_asic_specific_index(smu,
1201 CMN2ASIC_MAPPING_CLK,
1202 clk_type);
1203 if (clk_id < 0)
1204 return clk_id;
1205
1206 switch (clk_id) {
1207 case PPCLK_GFXCLK:
1208 member_type = METRICS_CURR_GFXCLK;
1209 break;
1210 case PPCLK_UCLK:
1211 member_type = METRICS_CURR_UCLK;
1212 break;
1213 case PPCLK_SOCCLK:
1214 member_type = METRICS_CURR_SOCCLK;
1215 break;
1216 case PPCLK_VCLK:
1217 member_type = METRICS_CURR_VCLK;
1218 break;
1219 case PPCLK_DCLK:
1220 member_type = METRICS_CURR_DCLK;
1221 break;
1222 case PPCLK_DCEFCLK:
1223 member_type = METRICS_CURR_DCEFCLK;
1224 break;
1225 default:
1226 return -EINVAL;
1227 }
1228
1229 return navi1x_get_smu_metrics_data(smu,
1230 member_type,
1231 value);
1232 }
1233
navi10_is_support_fine_grained_dpm(struct smu_context * smu,enum smu_clk_type clk_type)1234 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1235 {
1236 PPTable_t *pptable = smu->smu_table.driver_pptable;
1237 DpmDescriptor_t *dpm_desc = NULL;
1238 uint32_t clk_index = 0;
1239
1240 clk_index = smu_cmn_to_asic_specific_index(smu,
1241 CMN2ASIC_MAPPING_CLK,
1242 clk_type);
1243 dpm_desc = &pptable->DpmDescriptor[clk_index];
1244
1245 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1246 return dpm_desc->SnapToDiscrete == 0;
1247 }
1248
navi10_od_feature_is_supported(struct smu_11_0_overdrive_table * od_table,enum SMU_11_0_ODFEATURE_CAP cap)1249 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
1250 {
1251 return od_table->cap[cap];
1252 }
1253
navi10_od_setting_get_range(struct smu_11_0_overdrive_table * od_table,enum SMU_11_0_ODSETTING_ID setting,uint32_t * min,uint32_t * max)1254 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
1255 enum SMU_11_0_ODSETTING_ID setting,
1256 uint32_t *min, uint32_t *max)
1257 {
1258 if (min)
1259 *min = od_table->min[setting];
1260 if (max)
1261 *max = od_table->max[setting];
1262 }
1263
navi10_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1264 static int navi10_print_clk_levels(struct smu_context *smu,
1265 enum smu_clk_type clk_type, char *buf)
1266 {
1267 uint16_t *curve_settings;
1268 int i, levels, size = 0, ret = 0;
1269 uint32_t cur_value = 0, value = 0, count = 0;
1270 uint32_t freq_values[3] = {0};
1271 uint32_t mark_index = 0;
1272 struct smu_table_context *table_context = &smu->smu_table;
1273 uint32_t gen_speed, lane_width;
1274 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1275 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1276 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1277 OverDriveTable_t *od_table =
1278 (OverDriveTable_t *)table_context->overdrive_table;
1279 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1280 uint32_t min_value, max_value;
1281
1282 smu_cmn_get_sysfs_buf(&buf, &size);
1283
1284 switch (clk_type) {
1285 case SMU_GFXCLK:
1286 case SMU_SCLK:
1287 case SMU_SOCCLK:
1288 case SMU_MCLK:
1289 case SMU_UCLK:
1290 case SMU_FCLK:
1291 case SMU_VCLK:
1292 case SMU_DCLK:
1293 case SMU_DCEFCLK:
1294 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1295 if (ret)
1296 return size;
1297
1298 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1299 if (ret)
1300 return size;
1301
1302 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1303 for (i = 0; i < count; i++) {
1304 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1305 if (ret)
1306 return size;
1307
1308 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1309 cur_value == value ? "*" : "");
1310 }
1311 } else {
1312 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1313 if (ret)
1314 return size;
1315 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1316 if (ret)
1317 return size;
1318
1319 freq_values[1] = cur_value;
1320 mark_index = cur_value == freq_values[0] ? 0 :
1321 cur_value == freq_values[2] ? 2 : 1;
1322
1323 levels = 3;
1324 if (mark_index != 1) {
1325 levels = 2;
1326 freq_values[1] = freq_values[2];
1327 }
1328
1329 for (i = 0; i < levels; i++) {
1330 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1331 i == mark_index ? "*" : "");
1332 }
1333 }
1334 break;
1335 case SMU_PCIE:
1336 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1337 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1338 for (i = 0; i < NUM_LINK_LEVELS; i++)
1339 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1340 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1341 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1342 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1343 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1344 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1345 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1346 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1347 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1348 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1349 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1350 pptable->LclkFreq[i],
1351 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1352 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1353 "*" : "");
1354 break;
1355 case SMU_OD_SCLK:
1356 if (!smu->od_enabled || !od_table || !od_settings)
1357 break;
1358 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1359 break;
1360 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1361 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1362 od_table->GfxclkFmin, od_table->GfxclkFmax);
1363 break;
1364 case SMU_OD_MCLK:
1365 if (!smu->od_enabled || !od_table || !od_settings)
1366 break;
1367 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1368 break;
1369 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1370 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax);
1371 break;
1372 case SMU_OD_VDDC_CURVE:
1373 if (!smu->od_enabled || !od_table || !od_settings)
1374 break;
1375 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1376 break;
1377 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
1378 for (i = 0; i < 3; i++) {
1379 switch (i) {
1380 case 0:
1381 curve_settings = &od_table->GfxclkFreq1;
1382 break;
1383 case 1:
1384 curve_settings = &od_table->GfxclkFreq2;
1385 break;
1386 case 2:
1387 curve_settings = &od_table->GfxclkFreq3;
1388 break;
1389 default:
1390 break;
1391 }
1392 size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n",
1393 i, curve_settings[0],
1394 curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1395 }
1396 break;
1397 case SMU_OD_RANGE:
1398 if (!smu->od_enabled || !od_table || !od_settings)
1399 break;
1400 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1401
1402 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1403 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1404 &min_value, NULL);
1405 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1406 NULL, &max_value);
1407 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1408 min_value, max_value);
1409 }
1410
1411 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1412 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1413 &min_value, &max_value);
1414 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1415 min_value, max_value);
1416 }
1417
1418 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1419 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1420 &min_value, &max_value);
1421 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1422 min_value, max_value);
1423 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1424 &min_value, &max_value);
1425 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1426 min_value, max_value);
1427 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1428 &min_value, &max_value);
1429 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1430 min_value, max_value);
1431 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1432 &min_value, &max_value);
1433 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1434 min_value, max_value);
1435 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1436 &min_value, &max_value);
1437 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1438 min_value, max_value);
1439 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1440 &min_value, &max_value);
1441 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1442 min_value, max_value);
1443 }
1444
1445 break;
1446 default:
1447 break;
1448 }
1449
1450 return size;
1451 }
1452
navi10_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1453 static int navi10_force_clk_levels(struct smu_context *smu,
1454 enum smu_clk_type clk_type, uint32_t mask)
1455 {
1456
1457 int ret = 0, size = 0;
1458 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1459
1460 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1461 soft_max_level = mask ? (fls(mask) - 1) : 0;
1462
1463 switch (clk_type) {
1464 case SMU_GFXCLK:
1465 case SMU_SCLK:
1466 case SMU_SOCCLK:
1467 case SMU_MCLK:
1468 case SMU_UCLK:
1469 case SMU_FCLK:
1470 /* There is only 2 levels for fine grained DPM */
1471 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1472 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1473 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1474 }
1475
1476 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1477 if (ret)
1478 return size;
1479
1480 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1481 if (ret)
1482 return size;
1483
1484 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1485 if (ret)
1486 return size;
1487 break;
1488 case SMU_DCEFCLK:
1489 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1490 break;
1491
1492 default:
1493 break;
1494 }
1495
1496 return size;
1497 }
1498
navi10_populate_umd_state_clk(struct smu_context * smu)1499 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1500 {
1501 struct smu_11_0_dpm_context *dpm_context =
1502 smu->smu_dpm.dpm_context;
1503 struct smu_11_0_dpm_table *gfx_table =
1504 &dpm_context->dpm_tables.gfx_table;
1505 struct smu_11_0_dpm_table *mem_table =
1506 &dpm_context->dpm_tables.uclk_table;
1507 struct smu_11_0_dpm_table *soc_table =
1508 &dpm_context->dpm_tables.soc_table;
1509 struct smu_umd_pstate_table *pstate_table =
1510 &smu->pstate_table;
1511 struct amdgpu_device *adev = smu->adev;
1512 uint32_t sclk_freq;
1513
1514 pstate_table->gfxclk_pstate.min = gfx_table->min;
1515 switch (adev->asic_type) {
1516 case CHIP_NAVI10:
1517 switch (adev->pdev->revision) {
1518 case 0xf0: /* XTX */
1519 case 0xc0:
1520 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1521 break;
1522 case 0xf1: /* XT */
1523 case 0xc1:
1524 sclk_freq = NAVI10_PEAK_SCLK_XT;
1525 break;
1526 default: /* XL */
1527 sclk_freq = NAVI10_PEAK_SCLK_XL;
1528 break;
1529 }
1530 break;
1531 case CHIP_NAVI14:
1532 switch (adev->pdev->revision) {
1533 case 0xc7: /* XT */
1534 case 0xf4:
1535 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1536 break;
1537 case 0xc1: /* XTM */
1538 case 0xf2:
1539 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1540 break;
1541 case 0xc3: /* XLM */
1542 case 0xf3:
1543 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1544 break;
1545 case 0xc5: /* XTX */
1546 case 0xf6:
1547 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1548 break;
1549 default: /* XL */
1550 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1551 break;
1552 }
1553 break;
1554 case CHIP_NAVI12:
1555 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1556 break;
1557 default:
1558 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1559 break;
1560 }
1561 pstate_table->gfxclk_pstate.peak = sclk_freq;
1562
1563 pstate_table->uclk_pstate.min = mem_table->min;
1564 pstate_table->uclk_pstate.peak = mem_table->max;
1565
1566 pstate_table->socclk_pstate.min = soc_table->min;
1567 pstate_table->socclk_pstate.peak = soc_table->max;
1568
1569 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1570 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1571 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1572 pstate_table->gfxclk_pstate.standard =
1573 NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1574 pstate_table->uclk_pstate.standard =
1575 NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1576 pstate_table->socclk_pstate.standard =
1577 NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1578 } else {
1579 pstate_table->gfxclk_pstate.standard =
1580 pstate_table->gfxclk_pstate.min;
1581 pstate_table->uclk_pstate.standard =
1582 pstate_table->uclk_pstate.min;
1583 pstate_table->socclk_pstate.standard =
1584 pstate_table->socclk_pstate.min;
1585 }
1586
1587 return 0;
1588 }
1589
navi10_get_clock_by_type_with_latency(struct smu_context * smu,enum smu_clk_type clk_type,struct pp_clock_levels_with_latency * clocks)1590 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1591 enum smu_clk_type clk_type,
1592 struct pp_clock_levels_with_latency *clocks)
1593 {
1594 int ret = 0, i = 0;
1595 uint32_t level_count = 0, freq = 0;
1596
1597 switch (clk_type) {
1598 case SMU_GFXCLK:
1599 case SMU_DCEFCLK:
1600 case SMU_SOCCLK:
1601 case SMU_MCLK:
1602 case SMU_UCLK:
1603 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1604 if (ret)
1605 return ret;
1606
1607 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1608 clocks->num_levels = level_count;
1609
1610 for (i = 0; i < level_count; i++) {
1611 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1612 if (ret)
1613 return ret;
1614
1615 clocks->data[i].clocks_in_khz = freq * 1000;
1616 clocks->data[i].latency_in_us = 0;
1617 }
1618 break;
1619 default:
1620 break;
1621 }
1622
1623 return ret;
1624 }
1625
navi10_pre_display_config_changed(struct smu_context * smu)1626 static int navi10_pre_display_config_changed(struct smu_context *smu)
1627 {
1628 int ret = 0;
1629 uint32_t max_freq = 0;
1630
1631 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1632 if (ret)
1633 return ret;
1634
1635 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1636 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1637 if (ret)
1638 return ret;
1639 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1640 if (ret)
1641 return ret;
1642 }
1643
1644 return ret;
1645 }
1646
navi10_display_config_changed(struct smu_context * smu)1647 static int navi10_display_config_changed(struct smu_context *smu)
1648 {
1649 int ret = 0;
1650
1651 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1652 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1653 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1654 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1655 smu->display_config->num_display,
1656 NULL);
1657 if (ret)
1658 return ret;
1659 }
1660
1661 return ret;
1662 }
1663
navi10_is_dpm_running(struct smu_context * smu)1664 static bool navi10_is_dpm_running(struct smu_context *smu)
1665 {
1666 int ret = 0;
1667 uint32_t feature_mask[2];
1668 uint64_t feature_enabled;
1669
1670 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1671 if (ret)
1672 return false;
1673
1674 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1675
1676 return !!(feature_enabled & SMC_DPM_FEATURE);
1677 }
1678
navi10_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1679 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1680 uint32_t *speed)
1681 {
1682 int ret = 0;
1683
1684 if (!speed)
1685 return -EINVAL;
1686
1687 switch (smu_v11_0_get_fan_control_mode(smu)) {
1688 case AMD_FAN_CTRL_AUTO:
1689 ret = navi10_get_smu_metrics_data(smu,
1690 METRICS_CURR_FANSPEED,
1691 speed);
1692 break;
1693 default:
1694 ret = smu_v11_0_get_fan_speed_rpm(smu,
1695 speed);
1696 break;
1697 }
1698
1699 return ret;
1700 }
1701
navi10_get_fan_parameters(struct smu_context * smu)1702 static int navi10_get_fan_parameters(struct smu_context *smu)
1703 {
1704 PPTable_t *pptable = smu->smu_table.driver_pptable;
1705
1706 smu->fan_max_rpm = pptable->FanMaximumRpm;
1707
1708 return 0;
1709 }
1710
navi10_get_power_profile_mode(struct smu_context * smu,char * buf)1711 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1712 {
1713 DpmActivityMonitorCoeffInt_t activity_monitor;
1714 uint32_t i, size = 0;
1715 int16_t workload_type = 0;
1716 static const char *profile_name[] = {
1717 "BOOTUP_DEFAULT",
1718 "3D_FULL_SCREEN",
1719 "POWER_SAVING",
1720 "VIDEO",
1721 "VR",
1722 "COMPUTE",
1723 "CUSTOM"};
1724 static const char *title[] = {
1725 "PROFILE_INDEX(NAME)",
1726 "CLOCK_TYPE(NAME)",
1727 "FPS",
1728 "MinFreqType",
1729 "MinActiveFreqType",
1730 "MinActiveFreq",
1731 "BoosterFreqType",
1732 "BoosterFreq",
1733 "PD_Data_limit_c",
1734 "PD_Data_error_coeff",
1735 "PD_Data_error_rate_coeff"};
1736 int result = 0;
1737
1738 if (!buf)
1739 return -EINVAL;
1740
1741 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1742 title[0], title[1], title[2], title[3], title[4], title[5],
1743 title[6], title[7], title[8], title[9], title[10]);
1744
1745 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1746 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1747 workload_type = smu_cmn_to_asic_specific_index(smu,
1748 CMN2ASIC_MAPPING_WORKLOAD,
1749 i);
1750 if (workload_type < 0)
1751 return -EINVAL;
1752
1753 result = smu_cmn_update_table(smu,
1754 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1755 (void *)(&activity_monitor), false);
1756 if (result) {
1757 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1758 return result;
1759 }
1760
1761 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1762 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1763
1764 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1765 " ",
1766 0,
1767 "GFXCLK",
1768 activity_monitor.Gfx_FPS,
1769 activity_monitor.Gfx_MinFreqStep,
1770 activity_monitor.Gfx_MinActiveFreqType,
1771 activity_monitor.Gfx_MinActiveFreq,
1772 activity_monitor.Gfx_BoosterFreqType,
1773 activity_monitor.Gfx_BoosterFreq,
1774 activity_monitor.Gfx_PD_Data_limit_c,
1775 activity_monitor.Gfx_PD_Data_error_coeff,
1776 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1777
1778 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1779 " ",
1780 1,
1781 "SOCCLK",
1782 activity_monitor.Soc_FPS,
1783 activity_monitor.Soc_MinFreqStep,
1784 activity_monitor.Soc_MinActiveFreqType,
1785 activity_monitor.Soc_MinActiveFreq,
1786 activity_monitor.Soc_BoosterFreqType,
1787 activity_monitor.Soc_BoosterFreq,
1788 activity_monitor.Soc_PD_Data_limit_c,
1789 activity_monitor.Soc_PD_Data_error_coeff,
1790 activity_monitor.Soc_PD_Data_error_rate_coeff);
1791
1792 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1793 " ",
1794 2,
1795 "MEMLK",
1796 activity_monitor.Mem_FPS,
1797 activity_monitor.Mem_MinFreqStep,
1798 activity_monitor.Mem_MinActiveFreqType,
1799 activity_monitor.Mem_MinActiveFreq,
1800 activity_monitor.Mem_BoosterFreqType,
1801 activity_monitor.Mem_BoosterFreq,
1802 activity_monitor.Mem_PD_Data_limit_c,
1803 activity_monitor.Mem_PD_Data_error_coeff,
1804 activity_monitor.Mem_PD_Data_error_rate_coeff);
1805 }
1806
1807 return size;
1808 }
1809
navi10_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1810 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1811 {
1812 DpmActivityMonitorCoeffInt_t activity_monitor;
1813 int workload_type, ret = 0;
1814
1815 smu->power_profile_mode = input[size];
1816
1817 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1818 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1819 return -EINVAL;
1820 }
1821
1822 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1823
1824 ret = smu_cmn_update_table(smu,
1825 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1826 (void *)(&activity_monitor), false);
1827 if (ret) {
1828 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1829 return ret;
1830 }
1831
1832 switch (input[0]) {
1833 case 0: /* Gfxclk */
1834 activity_monitor.Gfx_FPS = input[1];
1835 activity_monitor.Gfx_MinFreqStep = input[2];
1836 activity_monitor.Gfx_MinActiveFreqType = input[3];
1837 activity_monitor.Gfx_MinActiveFreq = input[4];
1838 activity_monitor.Gfx_BoosterFreqType = input[5];
1839 activity_monitor.Gfx_BoosterFreq = input[6];
1840 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1841 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1842 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1843 break;
1844 case 1: /* Socclk */
1845 activity_monitor.Soc_FPS = input[1];
1846 activity_monitor.Soc_MinFreqStep = input[2];
1847 activity_monitor.Soc_MinActiveFreqType = input[3];
1848 activity_monitor.Soc_MinActiveFreq = input[4];
1849 activity_monitor.Soc_BoosterFreqType = input[5];
1850 activity_monitor.Soc_BoosterFreq = input[6];
1851 activity_monitor.Soc_PD_Data_limit_c = input[7];
1852 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1853 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1854 break;
1855 case 2: /* Memlk */
1856 activity_monitor.Mem_FPS = input[1];
1857 activity_monitor.Mem_MinFreqStep = input[2];
1858 activity_monitor.Mem_MinActiveFreqType = input[3];
1859 activity_monitor.Mem_MinActiveFreq = input[4];
1860 activity_monitor.Mem_BoosterFreqType = input[5];
1861 activity_monitor.Mem_BoosterFreq = input[6];
1862 activity_monitor.Mem_PD_Data_limit_c = input[7];
1863 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1864 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1865 break;
1866 }
1867
1868 ret = smu_cmn_update_table(smu,
1869 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1870 (void *)(&activity_monitor), true);
1871 if (ret) {
1872 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1873 return ret;
1874 }
1875 }
1876
1877 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1878 workload_type = smu_cmn_to_asic_specific_index(smu,
1879 CMN2ASIC_MAPPING_WORKLOAD,
1880 smu->power_profile_mode);
1881 if (workload_type < 0)
1882 return -EINVAL;
1883 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1884 1 << workload_type, NULL);
1885
1886 return ret;
1887 }
1888
navi10_notify_smc_display_config(struct smu_context * smu)1889 static int navi10_notify_smc_display_config(struct smu_context *smu)
1890 {
1891 struct smu_clocks min_clocks = {0};
1892 struct pp_display_clock_request clock_req;
1893 int ret = 0;
1894
1895 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1896 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1897 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1898
1899 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1900 clock_req.clock_type = amd_pp_dcef_clock;
1901 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1902
1903 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1904 if (!ret) {
1905 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1906 ret = smu_cmn_send_smc_msg_with_param(smu,
1907 SMU_MSG_SetMinDeepSleepDcefclk,
1908 min_clocks.dcef_clock_in_sr/100,
1909 NULL);
1910 if (ret) {
1911 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1912 return ret;
1913 }
1914 }
1915 } else {
1916 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1917 }
1918 }
1919
1920 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1921 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1922 if (ret) {
1923 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1924 return ret;
1925 }
1926 }
1927
1928 return 0;
1929 }
1930
navi10_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1931 static int navi10_set_watermarks_table(struct smu_context *smu,
1932 struct pp_smu_wm_range_sets *clock_ranges)
1933 {
1934 Watermarks_t *table = smu->smu_table.watermarks_table;
1935 int ret = 0;
1936 int i;
1937
1938 if (clock_ranges) {
1939 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1940 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1941 return -EINVAL;
1942
1943 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1944 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1945 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1946 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1947 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1948 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1949 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1950 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1951 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1952
1953 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1954 clock_ranges->reader_wm_sets[i].wm_inst;
1955 }
1956
1957 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1958 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1959 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1960 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1961 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1962 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1963 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1964 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1965 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1966
1967 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1968 clock_ranges->writer_wm_sets[i].wm_inst;
1969 }
1970
1971 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1972 }
1973
1974 /* pass data to smu controller */
1975 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1976 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1977 ret = smu_cmn_write_watermarks_table(smu);
1978 if (ret) {
1979 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1980 return ret;
1981 }
1982 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1983 }
1984
1985 return 0;
1986 }
1987
navi10_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1988 static int navi10_read_sensor(struct smu_context *smu,
1989 enum amd_pp_sensors sensor,
1990 void *data, uint32_t *size)
1991 {
1992 int ret = 0;
1993 struct smu_table_context *table_context = &smu->smu_table;
1994 PPTable_t *pptable = table_context->driver_pptable;
1995
1996 if(!data || !size)
1997 return -EINVAL;
1998
1999 mutex_lock(&smu->sensor_lock);
2000 switch (sensor) {
2001 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
2002 *(uint32_t *)data = pptable->FanMaximumRpm;
2003 *size = 4;
2004 break;
2005 case AMDGPU_PP_SENSOR_MEM_LOAD:
2006 ret = navi1x_get_smu_metrics_data(smu,
2007 METRICS_AVERAGE_MEMACTIVITY,
2008 (uint32_t *)data);
2009 *size = 4;
2010 break;
2011 case AMDGPU_PP_SENSOR_GPU_LOAD:
2012 ret = navi1x_get_smu_metrics_data(smu,
2013 METRICS_AVERAGE_GFXACTIVITY,
2014 (uint32_t *)data);
2015 *size = 4;
2016 break;
2017 case AMDGPU_PP_SENSOR_GPU_POWER:
2018 ret = navi1x_get_smu_metrics_data(smu,
2019 METRICS_AVERAGE_SOCKETPOWER,
2020 (uint32_t *)data);
2021 *size = 4;
2022 break;
2023 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2024 ret = navi1x_get_smu_metrics_data(smu,
2025 METRICS_TEMPERATURE_HOTSPOT,
2026 (uint32_t *)data);
2027 *size = 4;
2028 break;
2029 case AMDGPU_PP_SENSOR_EDGE_TEMP:
2030 ret = navi1x_get_smu_metrics_data(smu,
2031 METRICS_TEMPERATURE_EDGE,
2032 (uint32_t *)data);
2033 *size = 4;
2034 break;
2035 case AMDGPU_PP_SENSOR_MEM_TEMP:
2036 ret = navi1x_get_smu_metrics_data(smu,
2037 METRICS_TEMPERATURE_MEM,
2038 (uint32_t *)data);
2039 *size = 4;
2040 break;
2041 case AMDGPU_PP_SENSOR_GFX_MCLK:
2042 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
2043 *(uint32_t *)data *= 100;
2044 *size = 4;
2045 break;
2046 case AMDGPU_PP_SENSOR_GFX_SCLK:
2047 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
2048 *(uint32_t *)data *= 100;
2049 *size = 4;
2050 break;
2051 case AMDGPU_PP_SENSOR_VDDGFX:
2052 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2053 *size = 4;
2054 break;
2055 default:
2056 ret = -EOPNOTSUPP;
2057 break;
2058 }
2059 mutex_unlock(&smu->sensor_lock);
2060
2061 return ret;
2062 }
2063
navi10_get_uclk_dpm_states(struct smu_context * smu,uint32_t * clocks_in_khz,uint32_t * num_states)2064 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2065 {
2066 uint32_t num_discrete_levels = 0;
2067 uint16_t *dpm_levels = NULL;
2068 uint16_t i = 0;
2069 struct smu_table_context *table_context = &smu->smu_table;
2070 PPTable_t *driver_ppt = NULL;
2071
2072 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2073 return -EINVAL;
2074
2075 driver_ppt = table_context->driver_pptable;
2076 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
2077 dpm_levels = driver_ppt->FreqTableUclk;
2078
2079 if (num_discrete_levels == 0 || dpm_levels == NULL)
2080 return -EINVAL;
2081
2082 *num_states = num_discrete_levels;
2083 for (i = 0; i < num_discrete_levels; i++) {
2084 /* convert to khz */
2085 *clocks_in_khz = (*dpm_levels) * 1000;
2086 clocks_in_khz++;
2087 dpm_levels++;
2088 }
2089
2090 return 0;
2091 }
2092
navi10_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2093 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
2094 struct smu_temperature_range *range)
2095 {
2096 struct smu_table_context *table_context = &smu->smu_table;
2097 struct smu_11_0_powerplay_table *powerplay_table =
2098 table_context->power_play_table;
2099 PPTable_t *pptable = smu->smu_table.driver_pptable;
2100
2101 if (!range)
2102 return -EINVAL;
2103
2104 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2105
2106 range->max = pptable->TedgeLimit *
2107 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2108 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
2109 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2110 range->hotspot_crit_max = pptable->ThotspotLimit *
2111 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2112 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2113 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2114 range->mem_crit_max = pptable->TmemLimit *
2115 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2116 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
2117 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2118 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2119
2120 return 0;
2121 }
2122
navi10_display_disable_memory_clock_switch(struct smu_context * smu,bool disable_memory_clock_switch)2123 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
2124 bool disable_memory_clock_switch)
2125 {
2126 int ret = 0;
2127 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2128 (struct smu_11_0_max_sustainable_clocks *)
2129 smu->smu_table.max_sustainable_clocks;
2130 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2131 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2132
2133 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2134 return 0;
2135
2136 if(disable_memory_clock_switch)
2137 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2138 else
2139 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2140
2141 if(!ret)
2142 smu->disable_uclk_switch = disable_memory_clock_switch;
2143
2144 return ret;
2145 }
2146
navi10_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)2147 static int navi10_get_power_limit(struct smu_context *smu,
2148 uint32_t *current_power_limit,
2149 uint32_t *default_power_limit,
2150 uint32_t *max_power_limit)
2151 {
2152 struct smu_11_0_powerplay_table *powerplay_table =
2153 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
2154 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2155 PPTable_t *pptable = smu->smu_table.driver_pptable;
2156 uint32_t power_limit, od_percent;
2157
2158 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
2159 /* the last hope to figure out the ppt limit */
2160 if (!pptable) {
2161 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
2162 return -EINVAL;
2163 }
2164 power_limit =
2165 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2166 }
2167
2168 if (current_power_limit)
2169 *current_power_limit = power_limit;
2170 if (default_power_limit)
2171 *default_power_limit = power_limit;
2172
2173 if (max_power_limit) {
2174 if (smu->od_enabled &&
2175 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2176 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2177
2178 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
2179
2180 power_limit *= (100 + od_percent);
2181 power_limit /= 100;
2182 }
2183
2184 *max_power_limit = power_limit;
2185 }
2186
2187 return 0;
2188 }
2189
navi10_update_pcie_parameters(struct smu_context * smu,uint32_t pcie_gen_cap,uint32_t pcie_width_cap)2190 static int navi10_update_pcie_parameters(struct smu_context *smu,
2191 uint32_t pcie_gen_cap,
2192 uint32_t pcie_width_cap)
2193 {
2194 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2195 PPTable_t *pptable = smu->smu_table.driver_pptable;
2196 uint32_t smu_pcie_arg;
2197 int ret, i;
2198
2199 /* lclk dpm table setup */
2200 for (i = 0; i < MAX_PCIE_CONF; i++) {
2201 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2202 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2203 }
2204
2205 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2206 smu_pcie_arg = (i << 16) |
2207 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
2208 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
2209 pptable->PcieLaneCount[i] : pcie_width_cap);
2210 ret = smu_cmn_send_smc_msg_with_param(smu,
2211 SMU_MSG_OverridePcieParameters,
2212 smu_pcie_arg,
2213 NULL);
2214
2215 if (ret)
2216 return ret;
2217
2218 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
2219 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2220 if (pptable->PcieLaneCount[i] > pcie_width_cap)
2221 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2222 }
2223
2224 return 0;
2225 }
2226
navi10_dump_od_table(struct smu_context * smu,OverDriveTable_t * od_table)2227 static inline void navi10_dump_od_table(struct smu_context *smu,
2228 OverDriveTable_t *od_table)
2229 {
2230 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
2231 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
2232 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
2233 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
2234 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
2235 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
2236 }
2237
navi10_od_setting_check_range(struct smu_context * smu,struct smu_11_0_overdrive_table * od_table,enum SMU_11_0_ODSETTING_ID setting,uint32_t value)2238 static int navi10_od_setting_check_range(struct smu_context *smu,
2239 struct smu_11_0_overdrive_table *od_table,
2240 enum SMU_11_0_ODSETTING_ID setting,
2241 uint32_t value)
2242 {
2243 if (value < od_table->min[setting]) {
2244 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2245 return -EINVAL;
2246 }
2247 if (value > od_table->max[setting]) {
2248 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2249 return -EINVAL;
2250 }
2251 return 0;
2252 }
2253
navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context * smu,uint16_t * voltage,uint32_t freq)2254 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2255 uint16_t *voltage,
2256 uint32_t freq)
2257 {
2258 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2259 uint32_t value = 0;
2260 int ret;
2261
2262 ret = smu_cmn_send_smc_msg_with_param(smu,
2263 SMU_MSG_GetVoltageByDpm,
2264 param,
2265 &value);
2266 if (ret) {
2267 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2268 return ret;
2269 }
2270
2271 *voltage = (uint16_t)value;
2272
2273 return 0;
2274 }
2275
navi10_baco_enter(struct smu_context * smu)2276 static int navi10_baco_enter(struct smu_context *smu)
2277 {
2278 struct amdgpu_device *adev = smu->adev;
2279
2280 /*
2281 * This aims the case below:
2282 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded
2283 *
2284 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To
2285 * make that possible, PMFW needs to acknowledge the dstate transition
2286 * process for both gfx(function 0) and audio(function 1) function of
2287 * the ASIC.
2288 *
2289 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the
2290 * device representing the audio function of the ASIC. And that means
2291 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still
2292 * possible runpm suspend kicked on the ASIC. However without the dstate
2293 * transition notification from audio function, pmfw cannot handle the
2294 * BACO in/exit correctly. And that will cause driver hang on runpm
2295 * resuming.
2296 *
2297 * To address this, we revert to legacy message way(driver masters the
2298 * timing for BACO in/exit) on sound driver missing.
2299 */
2300 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2301 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2302 else
2303 return smu_v11_0_baco_enter(smu);
2304 }
2305
navi10_baco_exit(struct smu_context * smu)2306 static int navi10_baco_exit(struct smu_context *smu)
2307 {
2308 struct amdgpu_device *adev = smu->adev;
2309
2310 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2311 /* Wait for PMFW handling for the Dstate change */
2312 msleep(10);
2313 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2314 } else {
2315 return smu_v11_0_baco_exit(smu);
2316 }
2317 }
2318
navi10_set_default_od_settings(struct smu_context * smu)2319 static int navi10_set_default_od_settings(struct smu_context *smu)
2320 {
2321 OverDriveTable_t *od_table =
2322 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2323 OverDriveTable_t *boot_od_table =
2324 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2325 OverDriveTable_t *user_od_table =
2326 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2327 int ret = 0;
2328
2329 /*
2330 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2331 * - either they already have the default OD settings got during cold bootup
2332 * - or they have some user customized OD settings which cannot be overwritten
2333 */
2334 if (smu->adev->in_suspend)
2335 return 0;
2336
2337 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false);
2338 if (ret) {
2339 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2340 return ret;
2341 }
2342
2343 if (!boot_od_table->GfxclkVolt1) {
2344 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2345 &boot_od_table->GfxclkVolt1,
2346 boot_od_table->GfxclkFreq1);
2347 if (ret)
2348 return ret;
2349 }
2350
2351 if (!boot_od_table->GfxclkVolt2) {
2352 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2353 &boot_od_table->GfxclkVolt2,
2354 boot_od_table->GfxclkFreq2);
2355 if (ret)
2356 return ret;
2357 }
2358
2359 if (!boot_od_table->GfxclkVolt3) {
2360 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2361 &boot_od_table->GfxclkVolt3,
2362 boot_od_table->GfxclkFreq3);
2363 if (ret)
2364 return ret;
2365 }
2366
2367 navi10_dump_od_table(smu, boot_od_table);
2368
2369 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2370 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2371
2372 return 0;
2373 }
2374
navi10_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2375 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2376 int i;
2377 int ret = 0;
2378 struct smu_table_context *table_context = &smu->smu_table;
2379 OverDriveTable_t *od_table;
2380 struct smu_11_0_overdrive_table *od_settings;
2381 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2382 uint16_t *freq_ptr, *voltage_ptr;
2383 od_table = (OverDriveTable_t *)table_context->overdrive_table;
2384
2385 if (!smu->od_enabled) {
2386 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2387 return -EINVAL;
2388 }
2389
2390 if (!smu->od_settings) {
2391 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2392 return -ENOENT;
2393 }
2394
2395 od_settings = smu->od_settings;
2396
2397 switch (type) {
2398 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2399 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2400 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2401 return -ENOTSUPP;
2402 }
2403 if (!table_context->overdrive_table) {
2404 dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2405 return -EINVAL;
2406 }
2407 for (i = 0; i < size; i += 2) {
2408 if (i + 2 > size) {
2409 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2410 return -EINVAL;
2411 }
2412 switch (input[i]) {
2413 case 0:
2414 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2415 freq_ptr = &od_table->GfxclkFmin;
2416 if (input[i + 1] > od_table->GfxclkFmax) {
2417 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2418 input[i + 1],
2419 od_table->GfxclkFmin);
2420 return -EINVAL;
2421 }
2422 break;
2423 case 1:
2424 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2425 freq_ptr = &od_table->GfxclkFmax;
2426 if (input[i + 1] < od_table->GfxclkFmin) {
2427 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2428 input[i + 1],
2429 od_table->GfxclkFmax);
2430 return -EINVAL;
2431 }
2432 break;
2433 default:
2434 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2435 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2436 return -EINVAL;
2437 }
2438 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2439 if (ret)
2440 return ret;
2441 *freq_ptr = input[i + 1];
2442 }
2443 break;
2444 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2445 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2446 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2447 return -ENOTSUPP;
2448 }
2449 if (size < 2) {
2450 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2451 return -EINVAL;
2452 }
2453 if (input[0] != 1) {
2454 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2455 dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2456 return -EINVAL;
2457 }
2458 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2459 if (ret)
2460 return ret;
2461 od_table->UclkFmax = input[1];
2462 break;
2463 case PP_OD_RESTORE_DEFAULT_TABLE:
2464 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2465 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2466 return -EINVAL;
2467 }
2468 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2469 break;
2470 case PP_OD_COMMIT_DPM_TABLE:
2471 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2472 navi10_dump_od_table(smu, od_table);
2473 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2474 if (ret) {
2475 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2476 return ret;
2477 }
2478 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2479 smu->user_dpm_profile.user_od = true;
2480
2481 if (!memcmp(table_context->user_overdrive_table,
2482 table_context->boot_overdrive_table,
2483 sizeof(OverDriveTable_t)))
2484 smu->user_dpm_profile.user_od = false;
2485 }
2486 break;
2487 case PP_OD_EDIT_VDDC_CURVE:
2488 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2489 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2490 return -ENOTSUPP;
2491 }
2492 if (size < 3) {
2493 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2494 return -EINVAL;
2495 }
2496 if (!od_table) {
2497 dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2498 return -EINVAL;
2499 }
2500
2501 switch (input[0]) {
2502 case 0:
2503 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2504 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2505 freq_ptr = &od_table->GfxclkFreq1;
2506 voltage_ptr = &od_table->GfxclkVolt1;
2507 break;
2508 case 1:
2509 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2510 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2511 freq_ptr = &od_table->GfxclkFreq2;
2512 voltage_ptr = &od_table->GfxclkVolt2;
2513 break;
2514 case 2:
2515 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2516 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2517 freq_ptr = &od_table->GfxclkFreq3;
2518 voltage_ptr = &od_table->GfxclkVolt3;
2519 break;
2520 default:
2521 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2522 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2523 return -EINVAL;
2524 }
2525 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2526 if (ret)
2527 return ret;
2528 // Allow setting zero to disable the OverDrive VDDC curve
2529 if (input[2] != 0) {
2530 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2531 if (ret)
2532 return ret;
2533 *freq_ptr = input[1];
2534 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2535 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2536 } else {
2537 // If setting 0, disable all voltage curve settings
2538 od_table->GfxclkVolt1 = 0;
2539 od_table->GfxclkVolt2 = 0;
2540 od_table->GfxclkVolt3 = 0;
2541 }
2542 navi10_dump_od_table(smu, od_table);
2543 break;
2544 default:
2545 return -ENOSYS;
2546 }
2547 return ret;
2548 }
2549
navi10_run_btc(struct smu_context * smu)2550 static int navi10_run_btc(struct smu_context *smu)
2551 {
2552 int ret = 0;
2553
2554 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2555 if (ret)
2556 dev_err(smu->adev->dev, "RunBtc failed!\n");
2557
2558 return ret;
2559 }
2560
navi10_need_umc_cdr_workaround(struct smu_context * smu)2561 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
2562 {
2563 struct amdgpu_device *adev = smu->adev;
2564
2565 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2566 return false;
2567
2568 if (adev->asic_type == CHIP_NAVI10 ||
2569 adev->asic_type == CHIP_NAVI14)
2570 return true;
2571
2572 return false;
2573 }
2574
navi10_umc_hybrid_cdr_workaround(struct smu_context * smu)2575 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2576 {
2577 uint32_t uclk_count, uclk_min, uclk_max;
2578 int ret = 0;
2579
2580 /* This workaround can be applied only with uclk dpm enabled */
2581 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2582 return 0;
2583
2584 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2585 if (ret)
2586 return ret;
2587
2588 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2589 if (ret)
2590 return ret;
2591
2592 /*
2593 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2594 * This workaround is needed only when the max uclk frequency
2595 * not greater than that.
2596 */
2597 if (uclk_max > 0x2EE)
2598 return 0;
2599
2600 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2601 if (ret)
2602 return ret;
2603
2604 /* Force UCLK out of the highest DPM */
2605 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2606 if (ret)
2607 return ret;
2608
2609 /* Revert the UCLK Hardmax */
2610 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2611 if (ret)
2612 return ret;
2613
2614 /*
2615 * In this case, SMU already disabled dummy pstate during enablement
2616 * of UCLK DPM, we have to re-enabled it.
2617 */
2618 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2619 }
2620
navi10_set_dummy_pstates_table_location(struct smu_context * smu)2621 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu)
2622 {
2623 struct smu_table_context *smu_table = &smu->smu_table;
2624 struct smu_table *dummy_read_table =
2625 &smu_table->dummy_read_1_table;
2626 char *dummy_table = dummy_read_table->cpu_addr;
2627 int ret = 0;
2628 uint32_t i;
2629
2630 for (i = 0; i < 0x40000; i += 0x1000 * 2) {
2631 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000);
2632 dummy_table += 0x1000;
2633 memcpy(dummy_table, &DbiPrbs7[0], 0x1000);
2634 dummy_table += 0x1000;
2635 }
2636
2637 amdgpu_asic_flush_hdp(smu->adev, NULL);
2638
2639 ret = smu_cmn_send_smc_msg_with_param(smu,
2640 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
2641 upper_32_bits(dummy_read_table->mc_address),
2642 NULL);
2643 if (ret)
2644 return ret;
2645
2646 return smu_cmn_send_smc_msg_with_param(smu,
2647 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
2648 lower_32_bits(dummy_read_table->mc_address),
2649 NULL);
2650 }
2651
navi10_run_umc_cdr_workaround(struct smu_context * smu)2652 static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
2653 {
2654 struct amdgpu_device *adev = smu->adev;
2655 uint8_t umc_fw_greater_than_v136 = false;
2656 uint8_t umc_fw_disable_cdr = false;
2657 uint32_t pmfw_version;
2658 uint32_t param;
2659 int ret = 0;
2660
2661 if (!navi10_need_umc_cdr_workaround(smu))
2662 return 0;
2663
2664 ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
2665 if (ret) {
2666 dev_err(adev->dev, "Failed to get smu version!\n");
2667 return ret;
2668 }
2669
2670 /*
2671 * The messages below are only supported by Navi10 42.53.0 and later
2672 * PMFWs and Navi14 53.29.0 and later PMFWs.
2673 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
2674 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
2675 * - PPSMC_MSG_GetUMCFWWA
2676 */
2677 if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) ||
2678 ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) {
2679 ret = smu_cmn_send_smc_msg_with_param(smu,
2680 SMU_MSG_GET_UMC_FW_WA,
2681 0,
2682 ¶m);
2683 if (ret)
2684 return ret;
2685
2686 /* First bit indicates if the UMC f/w is above v137 */
2687 umc_fw_greater_than_v136 = param & 0x1;
2688
2689 /* Second bit indicates if hybrid-cdr is disabled */
2690 umc_fw_disable_cdr = param & 0x2;
2691
2692 /* w/a only allowed if UMC f/w is <= 136 */
2693 if (umc_fw_greater_than_v136)
2694 return 0;
2695
2696 if (umc_fw_disable_cdr) {
2697 if (adev->asic_type == CHIP_NAVI10)
2698 return navi10_umc_hybrid_cdr_workaround(smu);
2699 } else {
2700 return navi10_set_dummy_pstates_table_location(smu);
2701 }
2702 } else {
2703 if (adev->asic_type == CHIP_NAVI10)
2704 return navi10_umc_hybrid_cdr_workaround(smu);
2705 }
2706
2707 return 0;
2708 }
2709
navi10_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)2710 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
2711 void **table)
2712 {
2713 struct smu_table_context *smu_table = &smu->smu_table;
2714 struct gpu_metrics_v1_3 *gpu_metrics =
2715 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2716 SmuMetrics_legacy_t metrics;
2717 int ret = 0;
2718
2719 mutex_lock(&smu->metrics_lock);
2720
2721 ret = smu_cmn_get_metrics_table_locked(smu,
2722 NULL,
2723 true);
2724 if (ret) {
2725 mutex_unlock(&smu->metrics_lock);
2726 return ret;
2727 }
2728
2729 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t));
2730
2731 mutex_unlock(&smu->metrics_lock);
2732
2733 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2734
2735 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2736 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2737 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2738 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2739 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2740 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2741
2742 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2743 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2744
2745 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2746
2747 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2748 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2749 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2750
2751 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2752 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2753 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2754 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2755 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2756
2757 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2758 gpu_metrics->indep_throttle_status =
2759 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2760 navi1x_throttler_map);
2761
2762 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2763
2764 gpu_metrics->pcie_link_width =
2765 smu_v11_0_get_current_pcie_link_width(smu);
2766 gpu_metrics->pcie_link_speed =
2767 smu_v11_0_get_current_pcie_link_speed(smu);
2768
2769 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2770
2771 if (metrics.CurrGfxVoltageOffset)
2772 gpu_metrics->voltage_gfx =
2773 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2774 if (metrics.CurrMemVidOffset)
2775 gpu_metrics->voltage_mem =
2776 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2777 if (metrics.CurrSocVoltageOffset)
2778 gpu_metrics->voltage_soc =
2779 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2780
2781 *table = (void *)gpu_metrics;
2782
2783 return sizeof(struct gpu_metrics_v1_3);
2784 }
2785
navi10_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2786 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
2787 struct i2c_msg *msg, int num_msgs)
2788 {
2789 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
2790 struct smu_table_context *smu_table = &adev->smu.smu_table;
2791 struct smu_table *table = &smu_table->driver_table;
2792 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2793 int i, j, r, c;
2794 u16 dir;
2795
2796 req = kzalloc(sizeof(*req), GFP_KERNEL);
2797 if (!req)
2798 return -ENOMEM;
2799
2800 req->I2CcontrollerPort = 0;
2801 req->I2CSpeed = I2C_SPEED_FAST_400K;
2802 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2803 dir = msg[0].flags & I2C_M_RD;
2804
2805 for (c = i = 0; i < num_msgs; i++) {
2806 for (j = 0; j < msg[i].len; j++, c++) {
2807 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2808
2809 if (!(msg[i].flags & I2C_M_RD)) {
2810 /* write */
2811 cmd->Cmd = I2C_CMD_WRITE;
2812 cmd->RegisterAddr = msg[i].buf[j];
2813 }
2814
2815 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2816 /* The direction changes.
2817 */
2818 dir = msg[i].flags & I2C_M_RD;
2819 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2820 }
2821
2822 req->NumCmds++;
2823
2824 /*
2825 * Insert STOP if we are at the last byte of either last
2826 * message for the transaction or the client explicitly
2827 * requires a STOP at this particular message.
2828 */
2829 if ((j == msg[i].len - 1) &&
2830 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2831 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2832 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2833 }
2834 }
2835 }
2836 mutex_lock(&adev->smu.mutex);
2837 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2838 mutex_unlock(&adev->smu.mutex);
2839 if (r)
2840 goto fail;
2841
2842 for (c = i = 0; i < num_msgs; i++) {
2843 if (!(msg[i].flags & I2C_M_RD)) {
2844 c += msg[i].len;
2845 continue;
2846 }
2847 for (j = 0; j < msg[i].len; j++, c++) {
2848 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2849
2850 msg[i].buf[j] = cmd->Data;
2851 }
2852 }
2853 r = num_msgs;
2854 fail:
2855 kfree(req);
2856 return r;
2857 }
2858
navi10_i2c_func(struct i2c_adapter * adap)2859 static u32 navi10_i2c_func(struct i2c_adapter *adap)
2860 {
2861 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2862 }
2863
2864
2865 static const struct i2c_algorithm navi10_i2c_algo = {
2866 .master_xfer = navi10_i2c_xfer,
2867 .functionality = navi10_i2c_func,
2868 };
2869
2870 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = {
2871 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2872 .max_read_len = MAX_SW_I2C_COMMANDS,
2873 .max_write_len = MAX_SW_I2C_COMMANDS,
2874 .max_comb_1st_msg_len = 2,
2875 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2876 };
2877
navi10_i2c_control_init(struct smu_context * smu,struct i2c_adapter * control)2878 static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2879 {
2880 struct amdgpu_device *adev = to_amdgpu_device(control);
2881 int res;
2882
2883 control->owner = THIS_MODULE;
2884 control->class = I2C_CLASS_HWMON;
2885 control->dev.parent = &adev->pdev->dev;
2886 control->algo = &navi10_i2c_algo;
2887 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2888 control->quirks = &navi10_i2c_control_quirks;
2889
2890 res = i2c_add_adapter(control);
2891 if (res)
2892 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2893
2894 return res;
2895 }
2896
navi10_i2c_control_fini(struct smu_context * smu,struct i2c_adapter * control)2897 static void navi10_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2898 {
2899 i2c_del_adapter(control);
2900 }
2901
navi10_get_gpu_metrics(struct smu_context * smu,void ** table)2902 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
2903 void **table)
2904 {
2905 struct smu_table_context *smu_table = &smu->smu_table;
2906 struct gpu_metrics_v1_3 *gpu_metrics =
2907 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2908 SmuMetrics_t metrics;
2909 int ret = 0;
2910
2911 mutex_lock(&smu->metrics_lock);
2912
2913 ret = smu_cmn_get_metrics_table_locked(smu,
2914 NULL,
2915 true);
2916 if (ret) {
2917 mutex_unlock(&smu->metrics_lock);
2918 return ret;
2919 }
2920
2921 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
2922
2923 mutex_unlock(&smu->metrics_lock);
2924
2925 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2926
2927 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2928 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2929 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2930 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2931 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2932 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2933
2934 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2935 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2936
2937 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2938
2939 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
2940 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2941 else
2942 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2943
2944 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2945 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2946
2947 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2948 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2949 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2950 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2951 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2952
2953 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2954 gpu_metrics->indep_throttle_status =
2955 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2956 navi1x_throttler_map);
2957
2958 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2959
2960 gpu_metrics->pcie_link_width = metrics.PcieWidth;
2961 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
2962
2963 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2964
2965 if (metrics.CurrGfxVoltageOffset)
2966 gpu_metrics->voltage_gfx =
2967 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2968 if (metrics.CurrMemVidOffset)
2969 gpu_metrics->voltage_mem =
2970 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2971 if (metrics.CurrSocVoltageOffset)
2972 gpu_metrics->voltage_soc =
2973 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2974
2975 *table = (void *)gpu_metrics;
2976
2977 return sizeof(struct gpu_metrics_v1_3);
2978 }
2979
navi12_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)2980 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
2981 void **table)
2982 {
2983 struct smu_table_context *smu_table = &smu->smu_table;
2984 struct gpu_metrics_v1_3 *gpu_metrics =
2985 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2986 SmuMetrics_NV12_legacy_t metrics;
2987 int ret = 0;
2988
2989 mutex_lock(&smu->metrics_lock);
2990
2991 ret = smu_cmn_get_metrics_table_locked(smu,
2992 NULL,
2993 true);
2994 if (ret) {
2995 mutex_unlock(&smu->metrics_lock);
2996 return ret;
2997 }
2998
2999 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t));
3000
3001 mutex_unlock(&smu->metrics_lock);
3002
3003 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3004
3005 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3006 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3007 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3008 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3009 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3010 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3011
3012 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3013 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3014
3015 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3016
3017 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
3018 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3019 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
3020
3021 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3022 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3023 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3024 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3025
3026 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3027 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3028 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3029 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3030 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3031
3032 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3033 gpu_metrics->indep_throttle_status =
3034 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3035 navi1x_throttler_map);
3036
3037 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3038
3039 gpu_metrics->pcie_link_width =
3040 smu_v11_0_get_current_pcie_link_width(smu);
3041 gpu_metrics->pcie_link_speed =
3042 smu_v11_0_get_current_pcie_link_speed(smu);
3043
3044 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3045
3046 if (metrics.CurrGfxVoltageOffset)
3047 gpu_metrics->voltage_gfx =
3048 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3049 if (metrics.CurrMemVidOffset)
3050 gpu_metrics->voltage_mem =
3051 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3052 if (metrics.CurrSocVoltageOffset)
3053 gpu_metrics->voltage_soc =
3054 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3055
3056 *table = (void *)gpu_metrics;
3057
3058 return sizeof(struct gpu_metrics_v1_3);
3059 }
3060
navi12_get_gpu_metrics(struct smu_context * smu,void ** table)3061 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
3062 void **table)
3063 {
3064 struct smu_table_context *smu_table = &smu->smu_table;
3065 struct gpu_metrics_v1_3 *gpu_metrics =
3066 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3067 SmuMetrics_NV12_t metrics;
3068 int ret = 0;
3069
3070 mutex_lock(&smu->metrics_lock);
3071
3072 ret = smu_cmn_get_metrics_table_locked(smu,
3073 NULL,
3074 true);
3075 if (ret) {
3076 mutex_unlock(&smu->metrics_lock);
3077 return ret;
3078 }
3079
3080 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
3081
3082 mutex_unlock(&smu->metrics_lock);
3083
3084 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3085
3086 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3087 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3088 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3089 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3090 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3091 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3092
3093 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3094 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3095
3096 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3097
3098 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3099 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3100 else
3101 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3102
3103 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3104 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3105
3106 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3107 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3108 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3109 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3110
3111 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3112 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3113 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3114 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3115 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3116
3117 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3118 gpu_metrics->indep_throttle_status =
3119 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3120 navi1x_throttler_map);
3121
3122 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3123
3124 gpu_metrics->pcie_link_width = metrics.PcieWidth;
3125 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3126
3127 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3128
3129 if (metrics.CurrGfxVoltageOffset)
3130 gpu_metrics->voltage_gfx =
3131 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3132 if (metrics.CurrMemVidOffset)
3133 gpu_metrics->voltage_mem =
3134 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3135 if (metrics.CurrSocVoltageOffset)
3136 gpu_metrics->voltage_soc =
3137 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3138
3139 *table = (void *)gpu_metrics;
3140
3141 return sizeof(struct gpu_metrics_v1_3);
3142 }
3143
navi1x_get_gpu_metrics(struct smu_context * smu,void ** table)3144 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
3145 void **table)
3146 {
3147 struct amdgpu_device *adev = smu->adev;
3148 uint32_t smu_version;
3149 int ret = 0;
3150
3151 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3152 if (ret) {
3153 dev_err(adev->dev, "Failed to get smu version!\n");
3154 return ret;
3155 }
3156
3157 switch (adev->asic_type) {
3158 case CHIP_NAVI12:
3159 if (smu_version > 0x00341C00)
3160 ret = navi12_get_gpu_metrics(smu, table);
3161 else
3162 ret = navi12_get_legacy_gpu_metrics(smu, table);
3163 break;
3164 case CHIP_NAVI10:
3165 case CHIP_NAVI14:
3166 default:
3167 if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
3168 ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00))
3169 ret = navi10_get_gpu_metrics(smu, table);
3170 else
3171 ret =navi10_get_legacy_gpu_metrics(smu, table);
3172 break;
3173 }
3174
3175 return ret;
3176 }
3177
navi10_enable_mgpu_fan_boost(struct smu_context * smu)3178 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
3179 {
3180 struct smu_table_context *table_context = &smu->smu_table;
3181 PPTable_t *smc_pptable = table_context->driver_pptable;
3182 struct amdgpu_device *adev = smu->adev;
3183 uint32_t param = 0;
3184
3185 /* Navi12 does not support this */
3186 if (adev->asic_type == CHIP_NAVI12)
3187 return 0;
3188
3189 /*
3190 * Skip the MGpuFanBoost setting for those ASICs
3191 * which do not support it
3192 */
3193 if (!smc_pptable->MGpuFanBoostLimitRpm)
3194 return 0;
3195
3196 /* Workaround for WS SKU */
3197 if (adev->pdev->device == 0x7312 &&
3198 adev->pdev->revision == 0)
3199 param = 0xD188;
3200
3201 return smu_cmn_send_smc_msg_with_param(smu,
3202 SMU_MSG_SetMGpuFanBoostLimitRpm,
3203 param,
3204 NULL);
3205 }
3206
navi10_post_smu_init(struct smu_context * smu)3207 static int navi10_post_smu_init(struct smu_context *smu)
3208 {
3209 struct amdgpu_device *adev = smu->adev;
3210 int ret = 0;
3211
3212 if (amdgpu_sriov_vf(adev))
3213 return 0;
3214
3215 ret = navi10_run_umc_cdr_workaround(smu);
3216 if (ret) {
3217 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
3218 return ret;
3219 }
3220
3221 if (!smu->dc_controlled_by_gpio) {
3222 /*
3223 * For Navi1X, manually switch it to AC mode as PMFW
3224 * may boot it with DC mode.
3225 */
3226 ret = smu_v11_0_set_power_source(smu,
3227 adev->pm.ac_power ?
3228 SMU_POWER_SOURCE_AC :
3229 SMU_POWER_SOURCE_DC);
3230 if (ret) {
3231 dev_err(adev->dev, "Failed to switch to %s mode!\n",
3232 adev->pm.ac_power ? "AC" : "DC");
3233 return ret;
3234 }
3235 }
3236
3237 return ret;
3238 }
3239
3240 static const struct pptable_funcs navi10_ppt_funcs = {
3241 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3242 .set_default_dpm_table = navi10_set_default_dpm_table,
3243 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
3244 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
3245 .i2c_init = navi10_i2c_control_init,
3246 .i2c_fini = navi10_i2c_control_fini,
3247 .print_clk_levels = navi10_print_clk_levels,
3248 .force_clk_levels = navi10_force_clk_levels,
3249 .populate_umd_state_clk = navi10_populate_umd_state_clk,
3250 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
3251 .pre_display_config_changed = navi10_pre_display_config_changed,
3252 .display_config_changed = navi10_display_config_changed,
3253 .notify_smc_display_config = navi10_notify_smc_display_config,
3254 .is_dpm_running = navi10_is_dpm_running,
3255 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3256 .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
3257 .get_power_profile_mode = navi10_get_power_profile_mode,
3258 .set_power_profile_mode = navi10_set_power_profile_mode,
3259 .set_watermarks_table = navi10_set_watermarks_table,
3260 .read_sensor = navi10_read_sensor,
3261 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
3262 .set_performance_level = smu_v11_0_set_performance_level,
3263 .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
3264 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
3265 .get_power_limit = navi10_get_power_limit,
3266 .update_pcie_parameters = navi10_update_pcie_parameters,
3267 .init_microcode = smu_v11_0_init_microcode,
3268 .load_microcode = smu_v11_0_load_microcode,
3269 .fini_microcode = smu_v11_0_fini_microcode,
3270 .init_smc_tables = navi10_init_smc_tables,
3271 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3272 .init_power = smu_v11_0_init_power,
3273 .fini_power = smu_v11_0_fini_power,
3274 .check_fw_status = smu_v11_0_check_fw_status,
3275 .setup_pptable = navi10_setup_pptable,
3276 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3277 .check_fw_version = smu_v11_0_check_fw_version,
3278 .write_pptable = smu_cmn_write_pptable,
3279 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3280 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3281 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3282 .system_features_control = smu_v11_0_system_features_control,
3283 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3284 .send_smc_msg = smu_cmn_send_smc_msg,
3285 .init_display_count = smu_v11_0_init_display_count,
3286 .set_allowed_mask = smu_v11_0_set_allowed_mask,
3287 .get_enabled_mask = smu_cmn_get_enabled_mask,
3288 .feature_is_enabled = smu_cmn_feature_is_enabled,
3289 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3290 .notify_display_change = smu_v11_0_notify_display_change,
3291 .set_power_limit = smu_v11_0_set_power_limit,
3292 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3293 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3294 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3295 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
3296 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3297 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3298 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3299 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3300 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3301 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3302 .gfx_off_control = smu_v11_0_gfx_off_control,
3303 .register_irq_handler = smu_v11_0_register_irq_handler,
3304 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3305 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3306 .baco_is_support = smu_v11_0_baco_is_support,
3307 .baco_get_state = smu_v11_0_baco_get_state,
3308 .baco_set_state = smu_v11_0_baco_set_state,
3309 .baco_enter = navi10_baco_enter,
3310 .baco_exit = navi10_baco_exit,
3311 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3312 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3313 .set_default_od_settings = navi10_set_default_od_settings,
3314 .od_edit_dpm_table = navi10_od_edit_dpm_table,
3315 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3316 .run_btc = navi10_run_btc,
3317 .set_power_source = smu_v11_0_set_power_source,
3318 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3319 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3320 .get_gpu_metrics = navi1x_get_gpu_metrics,
3321 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
3322 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3323 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3324 .get_fan_parameters = navi10_get_fan_parameters,
3325 .post_init = navi10_post_smu_init,
3326 .interrupt_work = smu_v11_0_interrupt_work,
3327 .set_mp1_state = smu_cmn_set_mp1_state,
3328 };
3329
navi10_set_ppt_funcs(struct smu_context * smu)3330 void navi10_set_ppt_funcs(struct smu_context *smu)
3331 {
3332 smu->ppt_funcs = &navi10_ppt_funcs;
3333 smu->message_map = navi10_message_map;
3334 smu->clock_map = navi10_clk_map;
3335 smu->feature_map = navi10_feature_mask_map;
3336 smu->table_map = navi10_table_map;
3337 smu->pwr_src_map = navi10_pwr_src_map;
3338 smu->workload_map = navi10_workload_map;
3339 }
3340