/arch/mips/sgi-ip22/ |
D | ip22-nvram.c | 36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \ 37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ 38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \ 40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \ 41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) 45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \ 46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \ 47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \ 48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); }) 64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd() [all …]
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/arch/arm/mach-s3c/ |
D | pm-core-s3c24xx.h | 20 unsigned long tmp = __raw_readl(S3C2410_CLKCON); in s3c_pm_debug_init_uart() 39 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); in s3c_pm_arch_prepare_irqs() 40 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); in s3c_pm_arch_prepare_irqs() 41 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); in s3c_pm_arch_prepare_irqs() 71 __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs() 72 __raw_readl(S3C2410_EINTPEND)); in s3c_pm_arch_show_resume_irqs() 74 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs() 77 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), in s3c_pm_arch_show_resume_irqs()
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D | pm-gpio.c | 29 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save() 30 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save() 36 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume() 37 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume() 66 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_2bit_save() 67 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_2bit_save() 68 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); in samsung_gpio_pm_2bit_save() 123 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_2bit_resume() 124 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_2bit_resume() 194 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_4bit_save() [all …]
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D | cpufreq-utils-s3c24xx.c | 48 refval = __raw_readl(S3C2410_REFRESH); in s3c2410_cpufreq_setrefresh() 67 return __raw_readl(S3C2440_CAMDIVN); in s3c2440_read_camdivn() 78 return __raw_readl(S3C2410_CLKDIVN); in s3c24xx_read_clkdivn() 88 return __raw_readl(S3C2410_MPLLCON); in s3c24xx_read_mpllcon()
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D | simtec-pm.c | 51 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30; in pm_simtec_init() 52 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28; in pm_simtec_init() 53 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK); in pm_simtec_init()
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D | pm-s3c2410.c | 34 S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); in s3c2410_pm_prepare() 35 S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); in s3c2410_pm_prepare() 45 calc += __raw_readl(base+ptr); in s3c2410_pm_prepare() 61 calc += __raw_readl(base+ptr); in s3c2410_pm_prepare() 90 tmp = __raw_readl(S3C2410_GSTATUS2); in s3c2410_pm_resume()
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/arch/arm/mach-pxa/ |
D | smemc.c | 22 msc[0] = __raw_readl(MSC0); in pxa3xx_smemc_suspend() 23 msc[1] = __raw_readl(MSC1); in pxa3xx_smemc_suspend() 24 sxcnfg = __raw_readl(SXCNFG); in pxa3xx_smemc_suspend() 25 memclkcfg = __raw_readl(MEMCLKCFG); in pxa3xx_smemc_suspend() 26 csadrcfg[0] = __raw_readl(CSADRCFG0); in pxa3xx_smemc_suspend() 27 csadrcfg[1] = __raw_readl(CSADRCFG1); in pxa3xx_smemc_suspend() 28 csadrcfg[2] = __raw_readl(CSADRCFG2); in pxa3xx_smemc_suspend() 29 csadrcfg[3] = __raw_readl(CSADRCFG3); in pxa3xx_smemc_suspend()
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/arch/sh/boards/mach-dreamcast/ |
D | rtc.c | 39 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday() 40 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday() 42 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday() 43 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday() 71 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday() 72 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday() 74 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday() 75 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
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/arch/mips/loongson32/common/ |
D | irq.c | 28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack() 37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask() 46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack() 48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack() 57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask() 68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype() 70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype() 74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype() 76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype() 80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype() [all …]
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/arch/mips/alchemy/common/ |
D | usb.c | 102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl() 103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl() 131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control() 139 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control() 148 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control() 153 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ohci_control() 168 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ehci_control() 173 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_ehci_control() 180 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control() 185 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control() [all …]
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/arch/arm/mach-mmp/ |
D | pm-mmp2.c | 47 data |= __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake() 52 data = ~data & __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake() 68 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_disable() 84 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_enable() 105 val = __raw_readl(MPMU_PLL2_CTRL1); in pm_mpmu_clk_enable() 116 idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG); in mmp2_pm_enter_lowpower_mode() 117 apcr = __raw_readl(MPMU_PCR_PJ); in mmp2_pm_enter_lowpower_mode() 162 temp = __raw_readl(MMP2_ICU_INT4_MASK); in mmp2_pm_enter() 168 temp = __raw_readl(APMU_SRAM_PWR_DWN); in mmp2_pm_enter() 237 __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8)); in mmp2_pm_init() [all …]
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D | pm-pxa910.c | 112 awucrm |= __raw_readl(MPMU_AWUCRM); in pxa910_set_wake() 116 apcr = ~apcr & __raw_readl(MPMU_APCR); in pxa910_set_wake() 121 awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM); in pxa910_set_wake() 125 apcr |= __raw_readl(MPMU_APCR); in pxa910_set_wake() 136 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter_lowpower_mode() 137 apcr = __raw_readl(MPMU_APCR); in pxa910_pm_enter_lowpower_mode() 192 reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT)); in pxa910_pm_enter() 196 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter() 215 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter() 262 __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30), in pxa910_pm_init() [all …]
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/arch/mips/pci/ |
D | ops-tx4927.c | 69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr() 80 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) in check_abort() 82 if (__raw_readl(&pcicptr->pcistatus) in check_abort() 84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort() 110 return __raw_readl(&pcicptr->g2pcfgdata); in icd_readl() 230 __raw_readl(&pcicptr->pciid) >> 16, in tx4927_pcic_setup() 231 __raw_readl(&pcicptr->pciid) & 0xffff, in tx4927_pcic_setup() 232 __raw_readl(&pcicptr->pciccrev) & 0xff, in tx4927_pcic_setup() 239 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup() 307 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup() [all …]
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D | pci-ar724x.c | 60 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); in ar724x_pci_check_link() 86 data = __raw_readl(base + (where & ~3)); in ar724x_pci_local_write() 108 __raw_readl(base + (where & ~3)); in ar724x_pci_local_write() 128 data = __raw_readl(base + (where & ~3)); in ar724x_pci_read() 197 data = __raw_readl(base + (where & ~3)); in ar724x_pci_write() 219 __raw_readl(base + (where & ~3)); in ar724x_pci_write() 238 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & in ar724x_pci_irq_handler() 239 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_handler() 261 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask() 265 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask() [all …]
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/arch/arm/mach-cns3xxx/ |
D | pm.c | 17 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en() 26 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis() 35 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up() 47 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_down() 57 u32 reg = __raw_readl(PM_SOFT_RST_REG); in cns3xxx_pwr_soft_rst_force() 105 u32 reg = __raw_readl(PM_CLK_CTRL_REG); in cns3xxx_cpu_clock()
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/arch/mips/ralink/ |
D | mt7621.c | 40 if (__raw_readl(dm) != __raw_readl(dm + size)) in mt7621_addr_wraparound_test() 43 return __raw_readl(dm) == __raw_readl(dm + size); in mt7621_addr_wraparound_test() 72 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0); in mt7621_get_soc_name0() 77 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1); in mt7621_get_soc_name1() 99 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV); in mt7621_get_soc_rev()
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/arch/sh/kernel/cpu/sh4a/ |
D | ubc.c | 50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all() 59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all() 69 if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE) in sh4a_ubc_active_mask() 77 return __raw_readl(UBC_CCMFR); in sh4a_ubc_triggered_mask() 82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask() 121 (void)__raw_readl(UBC_CRR(i)); in sh4a_ubc_init()
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D | smp-shx3.c | 34 x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ in ipi_interrupt_handler() 51 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_smp_setup() 91 if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu() 94 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu() 103 return __raw_readl(0xff000048); /* CPIDR */ in shx3_smp_processor_id() 118 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_update_boot_vector()
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D | clock-sh7770.c | 21 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; in master_clk_init() 30 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); in module_clk_recalc() 40 int idx = (__raw_readl(FRQCR) & 0x000f); in bus_clk_recalc() 50 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); in cpu_clk_recalc()
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D | clock-sh7780.c | 24 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init() 33 int idx = (__raw_readl(FRQCR) & 0x0003); in module_clk_recalc() 43 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); in bus_clk_recalc() 53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); in cpu_clk_recalc() 76 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007); in shyway_clk_recalc()
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/arch/arm/mach-davinci/ |
D | pm.c | 51 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend() 58 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend() 64 val = __raw_readl(pm_config.deepsleep_reg); in davinci_pm_suspend() 75 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend() 80 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend() 88 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend() 96 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
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/arch/mips/ath79/ |
D | clock.c | 105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init() 131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init() 165 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); in ar933x_clocks_init() 178 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); in ar933x_clocks_init() 253 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); in ar934x_clocks_init() 257 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); in ar934x_clocks_init() 265 pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); in ar934x_clocks_init() 280 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); in ar934x_clocks_init() 284 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); in ar934x_clocks_init() 292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init() [all …]
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/arch/sh/kernel/cpu/sh3/ |
D | probe.c | 30 data0 = __raw_readl(addr0); in cpu_probe() 32 data1 = __raw_readl(addr1); in cpu_probe() 36 data0 = __raw_readl(addr0); in cpu_probe() 39 data1 = __raw_readl(addr1); in cpu_probe() 42 data3 = __raw_readl(addr0); in cpu_probe()
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/arch/arm/mach-lpc32xx/ |
D | common.c | 27 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2)); in lpc32xx_get_uid() 43 savedval1 = __raw_readl(iramptr1); in lpc32xx_return_iram() 44 savedval2 = __raw_readl(iramptr2); in lpc32xx_return_iram() 48 if (__raw_readl(iramptr1) == savedval2 + 1) in lpc32xx_return_iram() 67 u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); in lpc32xx_set_phy_interface_mode()
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/arch/arm/mach-s5pv210/ |
D | pm.c | 78 return __raw_readl(S5P_EINT_WAKEUP_MASK); in s5pv210_read_eint_wakeup_mask() 117 tmp = __raw_readl(S5P_SLEEP_CFG); in s5pv210_pm_prepare() 122 tmp = __raw_readl(S5P_PWR_CFG); in s5pv210_pm_prepare() 128 tmp = __raw_readl(S5P_OTHERS); in s5pv210_pm_prepare() 167 __raw_readl(S5P_WAKEUP_STAT)); in s5pv210_suspend_enter()
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