1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
5 * Copyright (C) 2015 John Crispin <john@phrozen.org>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/sys_soc.h>
12 #include <linux/memblock.h>
13
14 #include <asm/bootinfo.h>
15 #include <asm/mipsregs.h>
16 #include <asm/smp-ops.h>
17 #include <asm/mips-cps.h>
18 #include <asm/mach-ralink/ralink_regs.h>
19 #include <asm/mach-ralink/mt7621.h>
20
21 #include "common.h"
22
23 #define MT7621_MEM_TEST_PATTERN 0xaa5555aa
24
25 static u32 detect_magic __initdata;
26 static struct ralink_soc_info *soc_info_ptr;
27
mips_cpc_default_phys_base(void)28 phys_addr_t mips_cpc_default_phys_base(void)
29 {
30 panic("Cannot detect cpc address");
31 }
32
mt7621_addr_wraparound_test(phys_addr_t size)33 static bool __init mt7621_addr_wraparound_test(phys_addr_t size)
34 {
35 void *dm = (void *)KSEG1ADDR(&detect_magic);
36
37 if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)
38 return true;
39 __raw_writel(MT7621_MEM_TEST_PATTERN, dm);
40 if (__raw_readl(dm) != __raw_readl(dm + size))
41 return false;
42 __raw_writel(~MT7621_MEM_TEST_PATTERN, dm);
43 return __raw_readl(dm) == __raw_readl(dm + size);
44 }
45
mt7621_memory_detect(void)46 static void __init mt7621_memory_detect(void)
47 {
48 phys_addr_t size;
49
50 for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {
51 if (mt7621_addr_wraparound_test(size)) {
52 memblock_add(MT7621_LOWMEM_BASE, size);
53 return;
54 }
55 }
56
57 memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
58 memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
59 }
60
ralink_of_remap(void)61 void __init ralink_of_remap(void)
62 {
63 rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
64 rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
65
66 if (!rt_sysc_membase || !rt_memc_membase)
67 panic("Failed to remap core resources");
68 }
69
mt7621_get_soc_name0(void)70 static unsigned int __init mt7621_get_soc_name0(void)
71 {
72 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
73 }
74
mt7621_get_soc_name1(void)75 static unsigned int __init mt7621_get_soc_name1(void)
76 {
77 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1);
78 }
79
mt7621_soc_valid(void)80 static bool __init mt7621_soc_valid(void)
81 {
82 if (mt7621_get_soc_name0() == MT7621_CHIP_NAME0 &&
83 mt7621_get_soc_name1() == MT7621_CHIP_NAME1)
84 return true;
85 else
86 return false;
87 }
88
mt7621_get_soc_id(void)89 static const char __init *mt7621_get_soc_id(void)
90 {
91 if (mt7621_soc_valid())
92 return "MT7621";
93 else
94 return "invalid";
95 }
96
mt7621_get_soc_rev(void)97 static unsigned int __init mt7621_get_soc_rev(void)
98 {
99 return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV);
100 }
101
mt7621_get_soc_ver(void)102 static unsigned int __init mt7621_get_soc_ver(void)
103 {
104 return (mt7621_get_soc_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
105 }
106
mt7621_get_soc_eco(void)107 static unsigned int __init mt7621_get_soc_eco(void)
108 {
109 return (mt7621_get_soc_rev() & CHIP_REV_ECO_MASK);
110 }
111
mt7621_get_soc_revision(void)112 static const char __init *mt7621_get_soc_revision(void)
113 {
114 if (mt7621_get_soc_rev() == 1 && mt7621_get_soc_eco() == 1)
115 return "E2";
116 else
117 return "E1";
118 }
119
mt7621_soc_dev_init(void)120 static int __init mt7621_soc_dev_init(void)
121 {
122 struct soc_device *soc_dev;
123 struct soc_device_attribute *soc_dev_attr;
124
125 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
126 if (!soc_dev_attr)
127 return -ENOMEM;
128
129 soc_dev_attr->soc_id = "mt7621";
130 soc_dev_attr->family = "Ralink";
131 soc_dev_attr->revision = mt7621_get_soc_revision();
132
133 soc_dev_attr->data = soc_info_ptr;
134
135 soc_dev = soc_device_register(soc_dev_attr);
136 if (IS_ERR(soc_dev)) {
137 kfree(soc_dev_attr);
138 return PTR_ERR(soc_dev);
139 }
140
141 return 0;
142 }
143 device_initcall(mt7621_soc_dev_init);
144
prom_soc_init(struct ralink_soc_info * soc_info)145 void __init prom_soc_init(struct ralink_soc_info *soc_info)
146 {
147 /* Early detection of CMP support */
148 mips_cm_probe();
149 mips_cpc_probe();
150
151 if (mips_cps_numiocu(0)) {
152 /*
153 * mips_cm_probe() wipes out bootloader
154 * config for CM regions and we have to configure them
155 * again. This SoC cannot talk to pamlbus devices
156 * witout proper iocu region set up.
157 *
158 * FIXME: it would be better to do this with values
159 * from DT, but we need this very early because
160 * without this we cannot talk to pretty much anything
161 * including serial.
162 */
163 write_gcr_reg0_base(MT7621_PALMBUS_BASE);
164 write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
165 CM_GCR_REGn_MASK_CMTGT_IOCU0);
166 __sync();
167 }
168
169 if (mt7621_soc_valid())
170 soc_info->compatible = "mediatek,mt7621-soc";
171 else
172 panic("mt7621: unknown SoC, n0:%08x n1:%08x\n",
173 mt7621_get_soc_name0(),
174 mt7621_get_soc_name1());
175 ralink_soc = MT762X_SOC_MT7621AT;
176
177 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
178 "MediaTek %s ver:%u eco:%u",
179 mt7621_get_soc_id(),
180 mt7621_get_soc_ver(),
181 mt7621_get_soc_eco());
182
183 soc_info->mem_detect = mt7621_memory_detect;
184
185 soc_info_ptr = soc_info;
186
187 if (!register_cps_smp_ops())
188 return;
189 if (!register_cmp_smp_ops())
190 return;
191 if (!register_vsmp_smp_ops())
192 return;
193 }
194