/arch/arm/mach-omap2/ |
D | cm33xx.c | 94 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument 96 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); in _clkctrl_idlest() 110 static bool _is_module_ready(u16 inst, u16 clkctrl_offs) in _is_module_ready() argument 114 v = _clkctrl_idlest(inst, clkctrl_offs); in _is_module_ready() 229 static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, in am33xx_cm_wait_module_ready() argument 234 omap_test_timeout(_is_module_ready(inst, clkctrl_offs), in am33xx_cm_wait_module_ready() 252 static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, in am33xx_cm_wait_module_idle() argument 257 omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) == in am33xx_cm_wait_module_idle() 274 u16 clkctrl_offs) in am33xx_cm_module_enable() argument 278 v = am33xx_cm_read_reg(inst, clkctrl_offs); in am33xx_cm_module_enable() [all …]
|
D | cm.h | 60 void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); 61 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs); 62 u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs); 71 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); 72 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs); 73 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);
|
D | omap_hwmod_81xx_data.c | 178 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, 205 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, 247 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL, 284 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, 305 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, 326 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, 364 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, 401 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, 421 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, 493 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, [all …]
|
D | cminst44xx.c | 85 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument 87 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); in _clkctrl_idlest() 102 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) in _is_module_ready() argument 106 v = _clkctrl_idlest(part, inst, clkctrl_offs); in _is_module_ready() 274 static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, in omap4_cminst_wait_module_ready() argument 279 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), in omap4_cminst_wait_module_ready() 297 static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, in omap4_cminst_wait_module_idle() argument 302 omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) == in omap4_cminst_wait_module_idle() 319 u16 clkctrl_offs) in omap4_cminst_module_enable() argument 323 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); in omap4_cminst_module_enable() [all …]
|
D | cm_common.c | 131 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_module_enable() argument 139 cm_ll_data->module_enable(mode, part, inst, clkctrl_offs); in omap_cm_module_enable() 153 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_module_disable() argument 161 cm_ll_data->module_disable(part, inst, clkctrl_offs); in omap_cm_module_disable() 165 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_xlate_clkctrl() argument 172 return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs); in omap_cm_xlate_clkctrl()
|
D | omap_hwmod.c | 771 oh->prcm.omap4.clkctrl_offs); in _omap4_xlate_clkctrl() 1021 if (oh->prcm.omap4.clkctrl_offs) in _omap4_has_clkctrl_clock() 1024 if (!oh->prcm.omap4.clkctrl_offs && in _omap4_has_clkctrl_clock() 1079 oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); in _omap4_enable_module() 1110 oh->prcm.omap4.clkctrl_offs, 0); in _omap4_wait_target_disable() 1669 oh->prcm.omap4.clkctrl_offs); in _omap4_disable_module() 2747 oh->prcm.omap4.clkctrl_offs, 0); in _omap4_wait_target_ready()
|
D | omap_hwmod.h | 377 u16 clkctrl_offs; member
|