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Searched refs:config1 (Results 1 – 24 of 24) sorted by relevance

/arch/powerpc/platforms/83xx/
Dsuspend.c62 u32 config1; member
124 u32 reg_cfg1 = in_be32(&pmc_regs->config1); in mpc83xx_change_state()
134 out_be32(&pmc_regs->config1, reg_cfg1); in mpc83xx_change_state()
186 out_be32(&pmc_regs->config1, in mpc83xx_suspend_enter()
187 in_be32(&pmc_regs->config1) | PMCCR1_PME_EN); in mpc83xx_suspend_enter()
207 out_be32(&pmc_regs->config1, in mpc83xx_suspend_enter()
208 in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
214 out_be32(&pmc_regs->config1, in mpc83xx_suspend_enter()
215 in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
229 out_be32(&pmc_regs->config1, in mpc83xx_suspend_enter()
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/arch/mips/cavium-octeon/executive/
Dcvmx-pko.c311 union cvmx_pko_reg_queue_ptrs1 config1; in cvmx_pko_shutdown() local
312 config1.u64 = 0; in cvmx_pko_shutdown()
313 config1.s.qid7 = queue >> 7; in cvmx_pko_shutdown()
314 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); in cvmx_pko_shutdown()
347 union cvmx_pko_reg_queue_ptrs1 config1; in cvmx_pko_config_port() local
439 config1.u64 = 0; in cvmx_pko_config_port()
440 config1.s.idx3 = queue >> 3; in cvmx_pko_config_port()
441 config1.s.qid7 = (base_queue + queue) >> 7; in cvmx_pko_config_port()
543 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); in cvmx_pko_config_port()
/arch/mips/mm/
Dc-octeon.c170 unsigned int config1; in probe_octeon() local
174 config1 = read_c0_config1(); in probe_octeon()
178 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
179 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
180 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_octeon()
198 c->icache.linesz = 2 << ((config1 >> 19) & 7); in probe_octeon()
Dsc-mips.c186 unsigned int config1, config2; in mips_sc_probe() local
203 config1 = read_c0_config1(); in mips_sc_probe()
204 if (!(config1 & MIPS_CONF_M)) in mips_sc_probe()
Dc-r4k.c1111 unsigned long config1; in probe_pcache() local
1278 config1 = read_c0_config1(); in probe_pcache()
1279 lsize = (config1 >> 19) & 7; in probe_pcache()
1284 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_pcache()
1285 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_pcache()
1291 lsize = (config1 >> 10) & 7; in probe_pcache()
1296 c->dcache.sets = 64 << ((config1 >> 13) & 7); in probe_pcache()
1297 c->dcache.ways = 1 + ((config1 >> 7) & 7); in probe_pcache()
1331 config1 = read_c0_config1(); in probe_pcache()
1333 lsize = (config1 >> 19) & 7; in probe_pcache()
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/arch/x86/events/intel/
Duncore_nhmex.c372 reg1->config = event->attr.config1; in nhmex_bbox_hw_config()
457 reg1->config = event->attr.config1; in nhmex_sbox_hw_config()
674 u64 config1 = reg1->config; in nhmex_mbox_get_constraint() local
687 __BITS_VALUE(config1, i, 32))) in nhmex_mbox_get_constraint()
726 config1 = nhmex_mbox_alter_er(event, idx[0], false); in nhmex_mbox_get_constraint()
781 if (event->attr.config1 & ~er->valid_mask) in nhmex_mbox_hw_config()
798 reg1->config = event->attr.config1; in nhmex_mbox_hw_config()
986 u64 config1; in nhmex_rbox_get_constraint() local
993 config1 = reg1->config; in nhmex_rbox_get_constraint()
1016 !((er->config ^ config1) & mask)) { in nhmex_rbox_get_constraint()
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Duncore_snbep.c1027 reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx); in snbep_cbox_hw_config()
1082 u64 mask, config1 = reg1->config; in snbep_pcu_get_constraint() local
1092 !((config1 ^ er->config) & mask)) { in snbep_pcu_get_constraint()
1095 er->config |= config1 & mask; in snbep_pcu_get_constraint()
1103 config1 = snbep_pcu_alter_er(event, idx, false); in snbep_pcu_get_constraint()
1138 reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8)); in snbep_pcu_hw_config()
1193 reg1->config = event->attr.config1; in snbep_qpi_hw_config()
1753 reg1->config = event->attr.config1 & ivbep_cbox_filter_mask(idx); in ivbep_cbox_hw_config()
2181 reg1->config = event->attr.config1 & knl_cha_filter_mask(idx); in knl_cha_hw_config()
2592 reg1->config = event->attr.config1 & HSWEP_U_MSR_PMON_BOX_FILTER_MASK; in hswep_ubox_hw_config()
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Duncore.h132 u64 config, config1, config2; member
Duncore.c184 (er->config1 == reg1->config && er->config2 == reg2->config)) { in uncore_get_constraint()
186 er->config1 = reg1->config; in uncore_get_constraint()
Dcore.c3790 if (event->attr.config1 || event->attr.config2) in intel_pmu_hw_config()
/arch/powerpc/perf/
Dhv-gpci.c43 EVENT_DEFINE_RANGE_FORMAT(secondary_index, config1, 0, 15);
45 EVENT_DEFINE_RANGE_FORMAT(counter_info_version, config1, 16, 23);
47 EVENT_DEFINE_RANGE_FORMAT(length, config1, 24, 31);
49 EVENT_DEFINE_RANGE_FORMAT(offset, config1, 32, 63);
Dhv-24x7.c191 EVENT_DEFINE_RANGE_FORMAT(lpar, config1, 0, 15);
194 EVENT_DEFINE_RANGE(reserved2, config1, 16, 63);
1416 event->attr.config1, in h_24x7_event_init()
Disa207-common.c608 val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) & in isa207_compute_mmcr()
Dcore-book3s.c965 &cpuhw->avalues[i][0], event[i]->attr.config1)) in power_check_constraints()
1001 event[i]->attr.config1); in power_check_constraints()
/arch/mips/kernel/
Dcpu-probe.c462 unsigned int config1; in decode_config1() local
464 config1 = read_c0_config1(); in decode_config1()
466 if (config1 & MIPS_CONF1_MD) in decode_config1()
468 if (config1 & MIPS_CONF1_PC) in decode_config1()
470 if (config1 & MIPS_CONF1_WR) in decode_config1()
472 if (config1 & MIPS_CONF1_CA) in decode_config1()
474 if (config1 & MIPS_CONF1_EP) in decode_config1()
476 if (config1 & MIPS_CONF1_FP) { in decode_config1()
481 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; in decode_config1()
486 return config1 & MIPS_CONF_M; in decode_config1()
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/arch/powerpc/include/asm/
Dmpc52xx.h73 u32 config1; /* SDRAM + 0x08 */ member
/arch/mips/include/asm/
Dkvm_host.h660 __BUILD_KVM_RW_HW(config1, 32, MIPS_CP0_CONFIG, 1)
685 __BUILD_KVM_SET_SAVED(config1, 32, MIPS_CP0_CONFIG, 1)
Dmipsregs.h2918 __BUILD_SET_GC0(config1) in __BUILD_SET_C0()
/arch/x86/events/amd/
Diommu.c227 hwc->conf1 = event->attr.config1; in perf_iommu_event_init()
/arch/arm/mach-imx/
Dmmdc.c348 val = event->attr.config1; in mmdc_pmu_event_start()
/arch/x86/events/
Dcore.c169 if (event->attr.config1 & ~er->valid_mask) in x86_pmu_extra_regs()
176 reg->config = event->attr.config1; in x86_pmu_extra_regs()
388 attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result]; in set_ext_hw_attr()
/arch/arm64/kvm/
Dpmu-emul.c657 attr.config1 |= PERF_ATTR_CFG1_KVM_PMU_CHAINED; in kvm_pmu_create_perf_event()
/arch/arm64/kernel/
Dperf_event.c298 return event->attr.config1 & 0x1; in armv8pmu_event_is_64bit()
/arch/s390/kernel/
Dperf_cpum_sf.c839 if (attr->config1 & PERF_CPUM_SF_FULL_BLOCKS) in __hw_perf_event_init()