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Searched refs:cpu_logical_map (Results 1 – 25 of 65) sorted by relevance

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/arch/mips/loongson64/
Dsmp.c128 csr_mail_send(startargs[3], cpu_logical_map(cpu), 3); in csr_ipi_write_buf()
129 csr_mail_send(startargs[2], cpu_logical_map(cpu), 2); in csr_ipi_write_buf()
130 csr_mail_send(startargs[1], cpu_logical_map(cpu), 1); in csr_ipi_write_buf()
131 csr_mail_send(startargs[0], cpu_logical_map(cpu), 0); in csr_ipi_write_buf()
139 action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); in legacy_ipi_read_clear()
141 loongson3_ipi_write32(action, ipi_clear0_regs[cpu_logical_map(cpu)]); in legacy_ipi_read_clear()
153 loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); in legacy_ipi_write_enable()
158 loongson3_ipi_write64(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); in legacy_ipi_clear_buf()
175 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); in legacy_ipi_write_buf()
177 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); in legacy_ipi_write_buf()
[all …]
/arch/arm/common/
DbL_switcher.c69 ib_mpidr = cpu_logical_map(smp_processor_id()); in bL_do_switch()
159 BUG_ON(cpu_logical_map(this_cpu) != ob_mpidr); in bL_switch_to()
165 ib_mpidr = cpu_logical_map(that_cpu); in bL_switch_to()
227 cpu_logical_map(this_cpu) = ib_mpidr; in bL_switch_to()
228 cpu_logical_map(that_cpu) = ob_mpidr; in bL_switch_to()
428 cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0); in bL_switcher_halve_cpus()
429 cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 1); in bL_switcher_halve_cpus()
454 cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 1); in bL_switcher_halve_cpus()
461 cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(j), 1); in bL_switcher_halve_cpus()
484 cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0); in bL_switcher_halve_cpus()
[all …]
/arch/arm/mach-berlin/
Dplatsmp.c38 val &= ~BIT(cpu_logical_map(cpu)); in berlin_perform_reset_cpu()
40 val |= BIT(cpu_logical_map(cpu)); in berlin_perform_reset_cpu()
112 val &= ~BIT(cpu_logical_map(cpu)); in berlin_cpu_kill()
/arch/arm/mach-tegra/
Dplatsmp.c44 cpu = cpu_logical_map(cpu); in tegra20_boot_secondary()
75 cpu = cpu_logical_map(cpu); in tegra30_boot_secondary()
133 cpu = cpu_logical_map(cpu); in tegra114_boot_secondary()
Dpm.c80 cpu = cpu_logical_map(cpu); in restore_cpu_complex()
104 cpu = cpu_logical_map(cpu); in suspend_cpu_complex()
115 int phy_cpu_id = cpu_logical_map(smp_processor_id()); in tegra_pm_clear_cpu_in_lp2()
128 int phy_cpu_id = cpu_logical_map(smp_processor_id()); in tegra_pm_set_cpu_in_lp2()
/arch/arm/mach-shmobile/
Dsmp-r8a7779.c32 cpu = cpu_logical_map(cpu); in r8a7779_boot_secondary()
57 cpu = cpu_logical_map(cpu); in r8a7779_platform_cpu_kill()
Dplatsmp.c24 shmobile_smp_mpidr[cpu] = cpu_logical_map(cpu); in shmobile_smp_hook()
/arch/arm/mach-highbank/
Dsysregs.h29 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_set_core_pwr()
38 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_clear_core_pwr()
/arch/arm/include/asm/
Dsmp_plat.h73 #define cpu_logical_map(cpu) __cpu_logical_map[cpu] macro
84 if (cpu_logical_map(cpu) == mpidr) in get_logical_index()
/arch/arm/kernel/
Dpsci_smp.c48 return psci_ops.cpu_on(cpu_logical_map(cpu), in psci_boot_secondary()
92 err = psci_ops.affinity_info(cpu_logical_map(cpu), 0); in psci_cpu_kill()
Ddevtree.c181 cpu_logical_map(i) = tmp_map[i]; in arm_dt_init_cpu_maps()
182 pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i)); in arm_dt_init_cpu_maps()
188 return phys_id == cpu_logical_map(cpu); in arch_match_cpu_phys_id()
Dsmp_scu.c78 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0); in scu_set_power_mode_internal()
115 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0); in scu_get_cpu_power_mode()
Dsuspend.c23 u32 __mpidr = cpu_logical_map(smp_processor_id()); in cpu_suspend()
58 u32 __mpidr = cpu_logical_map(smp_processor_id()); in cpu_suspend()
/arch/arm/mach-imx/
Dsrc.c126 cpu = cpu_logical_map(cpu); in imx_enable_cpu()
148 cpu = cpu_logical_map(cpu); in imx_set_cpu_jump()
155 cpu = cpu_logical_map(cpu); in imx_get_cpu_arg()
161 cpu = cpu_logical_map(cpu); in imx_set_cpu_arg()
/arch/arm64/kernel/
Dpsci.c42 int err = psci_ops.cpu_on(cpu_logical_map(cpu), pa_secondary_entry); in cpu_psci_cpu_boot()
96 err = psci_ops.affinity_info(cpu_logical_map(cpu), 0); in cpu_psci_cpu_kill()
Dsetup.c99 return phys_id == cpu_logical_map(cpu); in arch_match_cpu_phys_id()
118 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); in smp_build_mpidr_hash()
291 u64 cpu_logical_map(unsigned int cpu) in cpu_logical_map() function
/arch/mips/cavium-octeon/
Dsmp.c101 int coreid = cpu_logical_map(cpu); in octeon_send_ipi_single()
213 cpu_logical_map(cpu)); in octeon_boot_secondary()
217 octeon_processor_boot = cpu_logical_map(cpu); in octeon_boot_secondary()
306 int coreid = cpu_logical_map(cpu); in octeon_cpu_die()
364 int coreid = cpu_logical_map(cpu); in octeon_update_boot_vector()
/arch/arm/mach-bcm/
Dplatsmp-brcmstb.c86 base += (cpu_logical_map(cpu) * 4); in pwr_ctrl_get_base()
132 val |= BIT(cpu_logical_map(cpu)); in cpu_rst_cfg_set()
134 val &= ~BIT(cpu_logical_map(cpu)); in cpu_rst_cfg_set()
140 const int reg_ofs = cpu_logical_map(cpu) * 8; in cpu_set_boot_addr()
/arch/arm/mach-milbeaut/
Dplatsmp.c30 mpidr = cpu_logical_map(l_cpu); in m10v_boot_secondary()
80 mpidr = cpu_logical_map(l_cpu); in m10v_cpu_kill()
/arch/mips/include/asm/mach-loongson64/
Dtopology.h7 #define cpu_to_node(cpu) (cpu_logical_map(cpu) >> 2)
/arch/arm64/include/asm/
Dsmp_plat.h39 if (cpu_logical_map(cpu) == mpidr) in get_logical_index()
/arch/parisc/include/asm/
Dsmp.h28 #define cpu_logical_map(cpu) (cpu) macro
/arch/arm/mach-exynos/
Dplatsmp.c51 u32 mpidr = cpu_logical_map(cpu); in platform_do_lowpower()
320 u32 mpidr = cpu_logical_map(cpu); in exynos_boot_secondary()
425 u32 mpidr = cpu_logical_map(cpu); in exynos_cpu_die()
/arch/xtensa/include/asm/
Dsmp.h15 #define cpu_logical_map(cpu) (cpu) macro
/arch/arm/mach-alpine/
Dplatsmp.c28 return alpine_cpu_wakeup(cpu_logical_map(cpu), (uint32_t)addr); in alpine_boot_secondary()

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