| /arch/x86/events/ |
| D | probe.c | 46 if (rdmsrl_safe(msr[bit].msr, &val)) in perf_msr_probe()
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| D | core.c | 261 ret = rdmsrl_safe(reg, &val); in check_hw_exists()
275 ret = rdmsrl_safe(reg, &val); in check_hw_exists()
306 if (rdmsrl_safe(reg, &val)) in check_hw_exists()
310 ret |= rdmsrl_safe(reg, &val_new); in check_hw_exists()
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| D | rapl.c | 607 if (rdmsrl_safe(rm->msr_power_unit, &msr_rapl_power_unit_bits)) in rapl_check_hw_unit()
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| /arch/x86/kernel/ |
| D | smpboot.c | 1853 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en); in turbo_disabled()
1864 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq); in slv_set_max_freq_ratio()
1868 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); in slv_set_max_freq_ratio()
1907 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); in knl_set_max_freq_ratio()
1913 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); in knl_set_max_freq_ratio()
1945 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); in skx_set_max_freq_ratio()
1951 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios); in skx_set_max_freq_ratio()
1955 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts); in skx_set_max_freq_ratio()
1975 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); in core_set_max_freq_ratio()
1979 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); in core_set_max_freq_ratio()
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| /arch/x86/kernel/cpu/mce/ |
| D | intel.c | 494 if (rdmsrl_safe(MSR_PPIN_CTL, &val)) in intel_ppin_init()
505 rdmsrl_safe(MSR_PPIN_CTL, &val); in intel_ppin_init()
526 if (rdmsrl_safe(MSR_ERROR_CONTROL, &error_control)) in intel_imc_init()
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| /arch/x86/lib/ |
| D | msr.c | 44 err = rdmsrl_safe(msr, &val); in msr_read()
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| /arch/x86/kernel/cpu/ |
| D | amd.c | 481 if (rdmsrl_safe(MSR_AMD_PPIN_CTL, &val)) in amd_detect_ppin()
491 rdmsrl_safe(MSR_AMD_PPIN_CTL, &val); in amd_detect_ppin()
644 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { in bsp_init_amd()
949 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { in init_amd_bd()
977 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { in init_spectral_chicken()
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| D | feat_ctl.c | 112 if (rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr)) { in init_ia32_feat_ctl()
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| D | intel.c | 583 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { in init_cpuid_fault()
593 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) in init_intel_misc_features()
1027 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl)) in split_lock_verify_msr()
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| D | hygon.c | 236 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { in bsp_init_hygon()
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| /arch/x86/power/ |
| D | cpu.c | 126 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, in __save_processor_state()
439 msr_array[i].valid = !rdmsrl_safe(msr_id[j], &dummy); in msr_build_context()
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| /arch/x86/include/asm/ |
| D | msr.h | 290 static inline int rdmsrl_safe(unsigned int msr, unsigned long long *p) in rdmsrl_safe() function
377 return rdmsrl_safe(msr_no, q); in rdmsrl_safe_on_cpu()
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| D | apic.h | 126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) in apic_is_x2apic_enabled()
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| D | paravirt.h | 236 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) in rdmsrl_safe() function
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| /arch/x86/events/amd/ |
| D | power.c | 275 if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &max_cu_acc_power)) { in amd_power_pmu_init()
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| /arch/x86/kvm/vmx/ |
| D | sgx.c | 409 rdmsrl_safe(MSR_IA32_SGXLEPUBKEYHASH0, &sgx_pubkey_hash[0])) { in setup_default_sgx_lepubkeyhash()
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| D | vmx.c | 2397 rdmsrl_safe(MSR_IA32_FEAT_CTL, &msr) ? 0xdeadbeef : msr); in kvm_cpu_vmxon()
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| /arch/x86/kvm/ |
| D | x86.c | 380 ret = rdmsrl_safe(msr, &val); in kvm_probe_user_return_msr()
421 rdmsrl_safe(kvm_uret_msrs_list[i], &value); in kvm_user_return_msr_cpu_online()
1571 rdmsrl_safe(msr->index, &msr->data); in kvm_get_msr_feature()
11431 rdmsrl_safe(MSR_EFER, &host_efer); in kvm_arch_hardware_setup()
12493 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) in kvm_spec_ctrl_test_value()
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| /arch/x86/events/intel/ |
| D | core.c | 4799 if (rdmsrl_safe(msr, &val_old)) in check_msr()
4811 rdmsrl_safe(msr, &val_new)) in check_msr()
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