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Searched refs:read_sysreg (Results 1 – 25 of 50) sorted by relevance

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/arch/arm64/include/asm/
Darch_timer.h70 return read_sysreg(cntp_tval_el0); in arch_timer_read_cntp_tval_el0()
75 return read_sysreg(cntv_tval_el0); in arch_timer_read_cntv_tval_el0()
80 return read_sysreg(cntpct_el0); in arch_timer_read_cntpct_el0()
85 return read_sysreg(cntvct_el0); in arch_timer_read_cntvct_el0()
136 return read_sysreg(cntp_ctl_el0); in arch_timer_reg_read_cp15()
143 return read_sysreg(cntv_ctl_el0); in arch_timer_reg_read_cp15()
154 return read_sysreg(cntfrq_el0); in arch_timer_get_cntfrq()
159 return read_sysreg(cntkctl_el1); in arch_timer_get_cntkctl()
183 cnt = read_sysreg(cntpct_el0); in __arch_counter_get_cntpct()
203 cnt = read_sysreg(cntvct_el0); in __arch_counter_get_cntvct()
Ddcc.h20 return read_sysreg(mdccsr_el0); in __dcc_getstatus()
25 char c = read_sysreg(dbgdtrrx_el0); in __dcc_getchar()
Ddaifflags.h45 flags = read_sysreg(daif); in local_daif_save_flags()
72 (read_sysreg(daif) & (PSR_I_BIT | PSR_F_BIT)) != (PSR_I_BIT | PSR_F_BIT)); in local_daif_restore()
Dvirt.h110 return read_sysreg(CurrentEL) == CurrentEL_EL2; in is_kernel_in_hyp_mode()
Dcpuidle.h34 c->daif_bits = read_sysreg(daif); \
Dhardirq.h42 ___hcr = read_sysreg(hcr_el2); \
Defi.h56 ((void)((state_flags) = read_sysreg(daif)))
Dcache.h124 u64 clidr = read_sysreg(clidr_el1); in read_cpuid_effective_cachetype()
/arch/arm64/kvm/hyp/include/hyp/
Dsysreg-sr.h21 ctxt_sys_reg(ctxt, MDSCR_EL1) = read_sysreg(mdscr_el1); in __sysreg_save_common_state()
26 ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0); in __sysreg_save_user_state()
27 ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0); in __sysreg_save_user_state()
42 ctxt_sys_reg(ctxt, CSSELR_EL1) = read_sysreg(csselr_el1); in __sysreg_save_el1_state()
58 ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1); in __sysreg_save_el1_state()
65 ctxt_sys_reg(ctxt, SP_EL1) = read_sysreg(sp_el1); in __sysreg_save_el1_state()
190 vcpu->arch.ctxt.spsr_abt = read_sysreg(spsr_abt); in __sysreg32_save_state()
191 vcpu->arch.ctxt.spsr_und = read_sysreg(spsr_und); in __sysreg32_save_state()
192 vcpu->arch.ctxt.spsr_irq = read_sysreg(spsr_irq); in __sysreg32_save_state()
193 vcpu->arch.ctxt.spsr_fiq = read_sysreg(spsr_fiq); in __sysreg32_save_state()
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Dswitch.h60 __vcpu_sys_reg(vcpu, FPEXC32_EL2) = read_sysreg(fpexc32_el2); in __fpsimd_save_fpexc32()
96 vcpu->arch.mdcr_el2_host = read_sysreg(mdcr_el2); in __activate_traps_common()
129 vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE; in ___deactivate_traps()
195 if (!(read_sysreg(hcr_el2) & HCR_RW)) in kvm_hyp_handle_fpsimd()
250 val = read_sysreg(hcr_el2); in kvm_hyp_handle_ptrauth()
408 unsigned long elr_el2 = read_sysreg(elr_el2); in __kvm_unexpected_el2_exception()
Ddebug-sr.h18 #define read_debug(r,n) read_sysreg(r##n##_el1)
97 aa64dfr0 = read_sysreg(id_aa64dfr0_el1); in __debug_save_state()
106 ctxt_sys_reg(ctxt, MDCCINT_EL1) = read_sysreg(mdccint_el1); in __debug_save_state()
115 aa64dfr0 = read_sysreg(id_aa64dfr0_el1); in __debug_restore_state()
Dfault.h67 hpfar = read_sysreg(hpfar_el2); in __get_fault_info()
/arch/arm64/kernel/
Dentry-common.c250 if (system_uses_irq_prio_masking() && read_sysreg(daif)) in arm64_preempt_schedule_irq()
297 __panic_unhandled(regs, desc, read_sysreg(esr_el1)); \
314 reg = read_sysreg(mdscr_el1); in cortex_a76_erratum_1463225_svc_handler()
357 unsigned long far = read_sysreg(far_el1); in el1_abort()
368 unsigned long far = read_sysreg(far_el1); in el1_pc()
397 unsigned long far = read_sysreg(far_el1); in el1_dbg()
416 unsigned long esr = read_sysreg(esr_el1); in el1h_64_sync_handler()
483 unsigned long esr = read_sysreg(esr_el1); in el1h_64_error_handler()
493 unsigned long far = read_sysreg(far_el1); in el0_da()
503 unsigned long far = read_sysreg(far_el1); in el0_ia()
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Dsdei.c250 u64 elr = read_sysreg(elr_el1); in do_sdei_event()
251 u32 kernel_mode = read_sysreg(CurrentEL) | 1; /* +SPSel */ in do_sdei_event()
252 unsigned long vbar = read_sysreg(vbar_el1); in do_sdei_event()
267 if (elr != read_sysreg(elr_el1)) { in do_sdei_event()
Dcrash_core.c16 return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; in get_tcr_el1_t1sz()
Dirq.c119 WARN_ON(read_sysreg(daif) & PSR_A_BIT); in init_IRQ()
Dmte.c304 BUG_ON(read_sysreg(ttbr0_el1) & TTBR_CNP_BIT); in mte_cpu_setup()
305 BUG_ON(read_sysreg(ttbr1_el1) & TTBR_CNP_BIT); in mte_cpu_setup()
321 rgsr = (read_sysreg(CNTVCT_EL0) & SYS_RGSR_EL1_SEED_MASK) << in mte_cpu_setup()
/arch/arm/include/asm/
Darch_gicv3.h48 return read_sysreg(a32); \
75 u32 irqstat = read_sysreg(ICC_IAR1); in gic_read_iar()
90 return read_sysreg(ICC_CTLR); in gic_read_ctlr()
106 return read_sysreg(ICC_SRE); in gic_read_sre()
122 return read_sysreg(ICC_PMR); in gic_read_pmr()
132 return read_sysreg(ICC_RPR); in gic_read_rpr()
/arch/arm64/kvm/hyp/nvhe/
Dtimer-sr.c27 val = read_sysreg(cnthctl_el2); in __timer_disable_traps()
44 val = read_sysreg(cnthctl_el2); in __timer_enable_traps()
Ddebug-sr.c114 return read_sysreg(mdcr_el2); in __kvm_get_mdcr_el2()
/arch/arm64/kvm/hyp/vhe/
Ddebug-sr.c25 return read_sysreg(mdcr_el2); in __kvm_get_mdcr_el2()
Dswitch.c42 val = read_sysreg(cpacr_el1); in __activate_traps()
228 read_sysreg(hpfar_el2), par, vcpu); in __hyp_call_panic()
/arch/arm/include/asm/vdso/
Dcp15.h24 #define read_sysreg(...) __read_sysreg(__VA_ARGS__) macro
/arch/arm64/kvm/
Dpmu.c69 return read_sysreg(pmevtyper##idx##_el0)
118 return read_sysreg(pmccfiltr_el0); in kvm_vcpu_pmu_read_evtype_direct()
/arch/arm64/kvm/hyp/
Dvgic-v2-cpuif-proxy.c23 return !!(read_sysreg(SCTLR_EL1) & SCTLR_ELx_EE); in __is_be()

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