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Searched refs:regval (Results 1 – 12 of 12) sorted by relevance

/arch/arm/mach-omap2/
Domap_phy_internal.c58 u32 regval; in am35x_musb_reset() local
61 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
63 regval |= AM35XX_USBOTGSS_SW_RST; in am35x_musb_reset()
64 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
66 regval &= ~AM35XX_USBOTGSS_SW_RST; in am35x_musb_reset()
67 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
69 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
112 u32 regval; in am35x_musb_clear_irq() local
114 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35x_musb_clear_irq()
115 regval |= AM35XX_USBOTGSS_INT_CLR; in am35x_musb_clear_irq()
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/arch/arm64/kvm/
Dvgic-sys-reg-v3.c23 val = p->regval; in access_gic_ctlr()
81 p->regval = val; in access_gic_ctlr()
94 vmcr.pmr = (p->regval & ICC_PMR_EL1_MASK) >> ICC_PMR_EL1_SHIFT; in access_gic_pmr()
97 p->regval = (vmcr.pmr << ICC_PMR_EL1_SHIFT) & ICC_PMR_EL1_MASK; in access_gic_pmr()
110 vmcr.bpr = (p->regval & ICC_BPR0_EL1_MASK) >> in access_gic_bpr0()
114 p->regval = (vmcr.bpr << ICC_BPR0_EL1_SHIFT) & in access_gic_bpr0()
127 p->regval = 0; in access_gic_bpr1()
132 vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >> in access_gic_bpr1()
136 p->regval = (vmcr.abpr << ICC_BPR1_EL1_SHIFT) & in access_gic_bpr1()
141 p->regval = min((vmcr.bpr + 1), 7U); in access_gic_bpr1()
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Dsys_regs.c152 val |= (p->regval & (mask >> shift)) << shift; in access_vm_reg()
169 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift; in access_actlr()
220 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); in access_gic_sgi()
232 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; in access_gic_sre()
277 p->regval = (1 << 3); in trap_oslsr_el1()
289 p->regval = read_sysreg(dbgauthstatus_el1); in trap_dbgauthstatus_el1()
326 vcpu_write_sys_reg(vcpu, p->regval, r->reg); in trap_debug_regs()
329 p->regval = vcpu_read_sys_reg(vcpu, r->reg); in trap_debug_regs()
332 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); in trap_debug_regs()
357 val |= (p->regval & (mask >> shift)) << shift; in reg_to_dbg()
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Dsys_regs.h26 u64 regval; member
112 p->regval = 0; in read_zero()
/arch/mips/loongson2ef/lemote-2f/
Dclock.c37 int regval; in loongson2_cpu_set_rate() local
45 regval = readl(LOONGSON_CHIPCFG); in loongson2_cpu_set_rate()
46 regval = (regval & ~0x7) | (pos->driver_data - 1); in loongson2_cpu_set_rate()
47 writel(regval, LOONGSON_CHIPCFG); in loongson2_cpu_set_rate()
/arch/sparc/include/asm/
Dturbosparc.h106 static inline void turbosparc_set_ccreg(unsigned long regval) in turbosparc_set_ccreg() argument
110 : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS) in turbosparc_set_ccreg()
116 unsigned long regval; in turbosparc_get_ccreg() local
119 : "=r" (regval) in turbosparc_get_ccreg()
121 return regval; in turbosparc_get_ccreg()
Dviking.h147 static inline void viking_set_bpreg(unsigned long regval) in viking_set_bpreg() argument
151 : "r" (regval), "i" (ASI_M_ACTION) in viking_set_bpreg()
157 unsigned long regval; in viking_get_bpreg() local
160 : "=r" (regval) in viking_get_bpreg()
162 return regval; in viking_get_bpreg()
Dpgtsrmmu.h120 void srmmu_set_mmureg(unsigned long regval);
/arch/sparc/kernel/
Dauxio_32.c88 unsigned char regval; in set_auxio() local
95 regval = sbus_readb(auxio_register); in set_auxio()
96 sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M, in set_auxio()
Dauxio_64.c35 u8 regval, newval; in __auxio_rmw() local
39 regval = (ebus ? in __auxio_rmw()
42 newval = regval | bits_on; in __auxio_rmw()
/arch/arm/mach-omap1/
Dclock.c229 u16 regval; in omap1_clk_set_rate_dsp_domain() local
237 regval = __raw_readw(DSP_CKCTL); in omap1_clk_set_rate_dsp_domain()
238 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_dsp_domain()
239 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_dsp_domain()
240 __raw_writew(regval, DSP_CKCTL); in omap1_clk_set_rate_dsp_domain()
259 u16 regval; in omap1_clk_set_rate_ckctl_arm() local
267 regval = omap_readw(ARM_CKCTL); in omap1_clk_set_rate_ckctl_arm()
268 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_ckctl_arm()
269 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_ckctl_arm()
270 regval = verify_ckctl_value(regval); in omap1_clk_set_rate_ckctl_arm()
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/arch/arm64/kvm/hyp/nvhe/
Dsys_regs.c251 p->regval = 0; in pvm_access_raz_wi()
297 p->regval = read_id_reg(vcpu, r); in pvm_access_id_aarch64()
307 p->regval = ICC_SRE_EL1_DIB | ICC_SRE_EL1_DFB | ICC_SRE_EL1_SRE; in pvm_gic_read_sre()
567 params.regval = vcpu_get_reg(vcpu, Rt); in kvm_handle_pvm_sysreg()
586 vcpu_set_reg(vcpu, Rt, params.regval); in kvm_handle_pvm_sysreg()