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Searched refs:rsvd_check (Results 1 – 3 of 3) sorted by relevance

/arch/x86/kvm/mmu/
Dspte.h290 static inline u64 get_rsvd_bits(struct rsvd_bits_validate *rsvd_check, u64 pte, in get_rsvd_bits() argument
295 return rsvd_check->rsvd_bits_mask[bit7][level-1]; in get_rsvd_bits()
298 static inline bool __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, in __is_rsvd_bits_set() argument
301 return pte & get_rsvd_bits(rsvd_check, pte, level); in __is_rsvd_bits_set()
304 static inline bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, in __is_bad_mt_xwr() argument
307 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f); in __is_bad_mt_xwr()
310 static __always_inline bool is_rsvd_spte(struct rsvd_bits_validate *rsvd_check, in is_rsvd_spte() argument
313 return __is_bad_mt_xwr(rsvd_check, spte) || in is_rsvd_spte()
314 __is_rsvd_bits_set(rsvd_check, spte, level); in is_rsvd_spte()
Dmmu.c3769 struct rsvd_bits_validate *rsvd_check; in get_mmio_spte() local
3798 rsvd_check = &vcpu->arch.mmu->shadow_zero_check; in get_mmio_spte()
3801 reserved |= is_rsvd_spte(rsvd_check, sptes[level], level); in get_mmio_spte()
3809 get_rsvd_bits(rsvd_check, sptes[level], level)); in get_mmio_spte()
4242 __reset_rsvds_bits_mask(struct rsvd_bits_validate *rsvd_check, in __reset_rsvds_bits_mask() argument
4250 rsvd_check->bad_mt_xwr = 0; in __reset_rsvds_bits_mask()
4274 rsvd_check->rsvd_bits_mask[0][1] = 0; in __reset_rsvds_bits_mask()
4275 rsvd_check->rsvd_bits_mask[0][0] = 0; in __reset_rsvds_bits_mask()
4276 rsvd_check->rsvd_bits_mask[1][0] = in __reset_rsvds_bits_mask()
4277 rsvd_check->rsvd_bits_mask[0][0]; in __reset_rsvds_bits_mask()
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Dpaging_tmpl.h132 static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte) in FNAME()
137 return __is_bad_mt_xwr(rsvd_check, gpte); in FNAME()