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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Kernel-based Virtual Machine driver for Linux
4  *
5  * This module enables machines with Intel VT-x extensions to run virtual
6  * machines without emulation or binary translation.
7  *
8  * MMU support
9  *
10  * Copyright (C) 2006 Qumranet, Inc.
11  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12  *
13  * Authors:
14  *   Yaniv Kamay  <yaniv@qumranet.com>
15  *   Avi Kivity   <avi@qumranet.com>
16  */
17 
18 /*
19  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
20  * so the code in this file is compiled twice, once per pte size.
21  */
22 
23 #if PTTYPE == 64
24 	#define pt_element_t u64
25 	#define guest_walker guest_walker64
26 	#define FNAME(name) paging##64_##name
27 	#define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK
28 	#define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
29 	#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
30 	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
31 	#define PT_LEVEL_BITS PT64_LEVEL_BITS
32 	#define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
33 	#define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
34 	#define PT_HAVE_ACCESSED_DIRTY(mmu) true
35 	#ifdef CONFIG_X86_64
36 	#define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
37 	#define CMPXCHG "cmpxchgq"
38 	#else
39 	#define PT_MAX_FULL_LEVELS 2
40 	#endif
41 #elif PTTYPE == 32
42 	#define pt_element_t u32
43 	#define guest_walker guest_walker32
44 	#define FNAME(name) paging##32_##name
45 	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
46 	#define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
47 	#define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
48 	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
49 	#define PT_LEVEL_BITS PT32_LEVEL_BITS
50 	#define PT_MAX_FULL_LEVELS 2
51 	#define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
52 	#define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
53 	#define PT_HAVE_ACCESSED_DIRTY(mmu) true
54 	#define CMPXCHG "cmpxchgl"
55 #elif PTTYPE == PTTYPE_EPT
56 	#define pt_element_t u64
57 	#define guest_walker guest_walkerEPT
58 	#define FNAME(name) ept_##name
59 	#define PT_BASE_ADDR_MASK GUEST_PT64_BASE_ADDR_MASK
60 	#define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
61 	#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
62 	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
63 	#define PT_LEVEL_BITS PT64_LEVEL_BITS
64 	#define PT_GUEST_DIRTY_SHIFT 9
65 	#define PT_GUEST_ACCESSED_SHIFT 8
66 	#define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
67 	#ifdef CONFIG_X86_64
68 	#define CMPXCHG "cmpxchgq"
69 	#endif
70 	#define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
71 #else
72 	#error Invalid PTTYPE value
73 #endif
74 
75 #define PT_GUEST_DIRTY_MASK    (1 << PT_GUEST_DIRTY_SHIFT)
76 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
77 
78 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
79 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PG_LEVEL_4K)
80 
81 /*
82  * The guest_walker structure emulates the behavior of the hardware page
83  * table walker.
84  */
85 struct guest_walker {
86 	int level;
87 	unsigned max_level;
88 	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
89 	pt_element_t ptes[PT_MAX_FULL_LEVELS];
90 	pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
91 	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
92 	pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
93 	bool pte_writable[PT_MAX_FULL_LEVELS];
94 	unsigned int pt_access[PT_MAX_FULL_LEVELS];
95 	unsigned int pte_access;
96 	gfn_t gfn;
97 	struct x86_exception fault;
98 };
99 
gpte_to_gfn_lvl(pt_element_t gpte,int lvl)100 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
101 {
102 	return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
103 }
104 
FNAME(protect_clean_gpte)105 static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
106 					     unsigned gpte)
107 {
108 	unsigned mask;
109 
110 	/* dirty bit is not supported, so no need to track it */
111 	if (!PT_HAVE_ACCESSED_DIRTY(mmu))
112 		return;
113 
114 	BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
115 
116 	mask = (unsigned)~ACC_WRITE_MASK;
117 	/* Allow write access to dirty gptes */
118 	mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
119 		PT_WRITABLE_MASK;
120 	*access &= mask;
121 }
122 
FNAME(is_present_gpte)123 static inline int FNAME(is_present_gpte)(unsigned long pte)
124 {
125 #if PTTYPE != PTTYPE_EPT
126 	return pte & PT_PRESENT_MASK;
127 #else
128 	return pte & 7;
129 #endif
130 }
131 
FNAME(is_bad_mt_xwr)132 static bool FNAME(is_bad_mt_xwr)(struct rsvd_bits_validate *rsvd_check, u64 gpte)
133 {
134 #if PTTYPE != PTTYPE_EPT
135 	return false;
136 #else
137 	return __is_bad_mt_xwr(rsvd_check, gpte);
138 #endif
139 }
140 
FNAME(is_rsvd_bits_set)141 static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level)
142 {
143 	return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level) ||
144 	       FNAME(is_bad_mt_xwr)(&mmu->guest_rsvd_check, gpte);
145 }
146 
FNAME(cmpxchg_gpte)147 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
148 			       pt_element_t __user *ptep_user, unsigned index,
149 			       pt_element_t orig_pte, pt_element_t new_pte)
150 {
151 	int r = -EFAULT;
152 
153 	if (!user_access_begin(ptep_user, sizeof(pt_element_t)))
154 		return -EFAULT;
155 
156 #ifdef CMPXCHG
157 	asm volatile("1:" LOCK_PREFIX CMPXCHG " %[new], %[ptr]\n"
158 		     "mov $0, %[r]\n"
159 		     "setnz %b[r]\n"
160 		     "2:"
161 		     _ASM_EXTABLE_UA(1b, 2b)
162 		     : [ptr] "+m" (*ptep_user),
163 		       [old] "+a" (orig_pte),
164 		       [r] "+q" (r)
165 		     : [new] "r" (new_pte)
166 		     : "memory");
167 #else
168 	asm volatile("1:" LOCK_PREFIX "cmpxchg8b %[ptr]\n"
169 		     "movl $0, %[r]\n"
170 		     "jz 2f\n"
171 		     "incl %[r]\n"
172 		     "2:"
173 		     _ASM_EXTABLE_UA(1b, 2b)
174 		     : [ptr] "+m" (*ptep_user),
175 		       [old] "+A" (orig_pte),
176 		       [r] "+rm" (r)
177 		     : [new_lo] "b" ((u32)new_pte),
178 		       [new_hi] "c" ((u32)(new_pte >> 32))
179 		     : "memory");
180 #endif
181 
182 	user_access_end();
183 	return r;
184 }
185 
FNAME(prefetch_invalid_gpte)186 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
187 				  struct kvm_mmu_page *sp, u64 *spte,
188 				  u64 gpte)
189 {
190 	if (!FNAME(is_present_gpte)(gpte))
191 		goto no_present;
192 
193 	/* if accessed bit is not supported prefetch non accessed gpte */
194 	if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) &&
195 	    !(gpte & PT_GUEST_ACCESSED_MASK))
196 		goto no_present;
197 
198 	if (FNAME(is_rsvd_bits_set)(vcpu->arch.mmu, gpte, PG_LEVEL_4K))
199 		goto no_present;
200 
201 	return false;
202 
203 no_present:
204 	drop_spte(vcpu->kvm, spte);
205 	return true;
206 }
207 
208 /*
209  * For PTTYPE_EPT, a page table can be executable but not readable
210  * on supported processors. Therefore, set_spte does not automatically
211  * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
212  * to signify readability since it isn't used in the EPT case
213  */
FNAME(gpte_access)214 static inline unsigned FNAME(gpte_access)(u64 gpte)
215 {
216 	unsigned access;
217 #if PTTYPE == PTTYPE_EPT
218 	access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
219 		((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
220 		((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
221 #else
222 	BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
223 	BUILD_BUG_ON(ACC_EXEC_MASK != 1);
224 	access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
225 	/* Combine NX with P (which is set here) to get ACC_EXEC_MASK.  */
226 	access ^= (gpte >> PT64_NX_SHIFT);
227 #endif
228 
229 	return access;
230 }
231 
FNAME(update_accessed_dirty_bits)232 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
233 					     struct kvm_mmu *mmu,
234 					     struct guest_walker *walker,
235 					     gpa_t addr, int write_fault)
236 {
237 	unsigned level, index;
238 	pt_element_t pte, orig_pte;
239 	pt_element_t __user *ptep_user;
240 	gfn_t table_gfn;
241 	int ret;
242 
243 	/* dirty/accessed bits are not supported, so no need to update them */
244 	if (!PT_HAVE_ACCESSED_DIRTY(mmu))
245 		return 0;
246 
247 	for (level = walker->max_level; level >= walker->level; --level) {
248 		pte = orig_pte = walker->ptes[level - 1];
249 		table_gfn = walker->table_gfn[level - 1];
250 		ptep_user = walker->ptep_user[level - 1];
251 		index = offset_in_page(ptep_user) / sizeof(pt_element_t);
252 		if (!(pte & PT_GUEST_ACCESSED_MASK)) {
253 			trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
254 			pte |= PT_GUEST_ACCESSED_MASK;
255 		}
256 		if (level == walker->level && write_fault &&
257 				!(pte & PT_GUEST_DIRTY_MASK)) {
258 			trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
259 #if PTTYPE == PTTYPE_EPT
260 			if (kvm_x86_ops.nested_ops->write_log_dirty(vcpu, addr))
261 				return -EINVAL;
262 #endif
263 			pte |= PT_GUEST_DIRTY_MASK;
264 		}
265 		if (pte == orig_pte)
266 			continue;
267 
268 		/*
269 		 * If the slot is read-only, simply do not process the accessed
270 		 * and dirty bits.  This is the correct thing to do if the slot
271 		 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
272 		 * are only supported if the accessed and dirty bits are already
273 		 * set in the ROM (so that MMIO writes are never needed).
274 		 *
275 		 * Note that NPT does not allow this at all and faults, since
276 		 * it always wants nested page table entries for the guest
277 		 * page tables to be writable.  And EPT works but will simply
278 		 * overwrite the read-only memory to set the accessed and dirty
279 		 * bits.
280 		 */
281 		if (unlikely(!walker->pte_writable[level - 1]))
282 			continue;
283 
284 		ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
285 		if (ret)
286 			return ret;
287 
288 		kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
289 		walker->ptes[level - 1] = pte;
290 	}
291 	return 0;
292 }
293 
FNAME(gpte_pkeys)294 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
295 {
296 	unsigned pkeys = 0;
297 #if PTTYPE == 64
298 	pte_t pte = {.pte = gpte};
299 
300 	pkeys = pte_flags_pkey(pte_flags(pte));
301 #endif
302 	return pkeys;
303 }
304 
FNAME(is_last_gpte)305 static inline bool FNAME(is_last_gpte)(struct kvm_mmu *mmu,
306 				       unsigned int level, unsigned int gpte)
307 {
308 	/*
309 	 * For EPT and PAE paging (both variants), bit 7 is either reserved at
310 	 * all level or indicates a huge page (ignoring CR3/EPTP).  In either
311 	 * case, bit 7 being set terminates the walk.
312 	 */
313 #if PTTYPE == 32
314 	/*
315 	 * 32-bit paging requires special handling because bit 7 is ignored if
316 	 * CR4.PSE=0, not reserved.  Clear bit 7 in the gpte if the level is
317 	 * greater than the last level for which bit 7 is the PAGE_SIZE bit.
318 	 *
319 	 * The RHS has bit 7 set iff level < (2 + PSE).  If it is clear, bit 7
320 	 * is not reserved and does not indicate a large page at this level,
321 	 * so clear PT_PAGE_SIZE_MASK in gpte if that is the case.
322 	 */
323 	gpte &= level - (PT32_ROOT_LEVEL + mmu->mmu_role.ext.cr4_pse);
324 #endif
325 	/*
326 	 * PG_LEVEL_4K always terminates.  The RHS has bit 7 set
327 	 * iff level <= PG_LEVEL_4K, which for our purpose means
328 	 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
329 	 */
330 	gpte |= level - PG_LEVEL_4K - 1;
331 
332 	return gpte & PT_PAGE_SIZE_MASK;
333 }
334 /*
335  * Fetch a guest pte for a guest virtual address, or for an L2's GPA.
336  */
FNAME(walk_addr_generic)337 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
338 				    struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
339 				    gpa_t addr, u32 access)
340 {
341 	int ret;
342 	pt_element_t pte;
343 	pt_element_t __user *ptep_user;
344 	gfn_t table_gfn;
345 	u64 pt_access, pte_access;
346 	unsigned index, accessed_dirty, pte_pkey;
347 	unsigned nested_access;
348 	gpa_t pte_gpa;
349 	bool have_ad;
350 	int offset;
351 	u64 walk_nx_mask = 0;
352 	const int write_fault = access & PFERR_WRITE_MASK;
353 	const int user_fault  = access & PFERR_USER_MASK;
354 	const int fetch_fault = access & PFERR_FETCH_MASK;
355 	u16 errcode = 0;
356 	gpa_t real_gpa;
357 	gfn_t gfn;
358 
359 	trace_kvm_mmu_pagetable_walk(addr, access);
360 retry_walk:
361 	walker->level = mmu->root_level;
362 	pte           = mmu->get_guest_pgd(vcpu);
363 	have_ad       = PT_HAVE_ACCESSED_DIRTY(mmu);
364 
365 #if PTTYPE == 64
366 	walk_nx_mask = 1ULL << PT64_NX_SHIFT;
367 	if (walker->level == PT32E_ROOT_LEVEL) {
368 		pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
369 		trace_kvm_mmu_paging_element(pte, walker->level);
370 		if (!FNAME(is_present_gpte)(pte))
371 			goto error;
372 		--walker->level;
373 	}
374 #endif
375 	walker->max_level = walker->level;
376 	ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
377 
378 	/*
379 	 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
380 	 * by the MOV to CR instruction are treated as reads and do not cause the
381 	 * processor to set the dirty flag in any EPT paging-structure entry.
382 	 */
383 	nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
384 
385 	pte_access = ~0;
386 	++walker->level;
387 
388 	do {
389 		unsigned long host_addr;
390 
391 		pt_access = pte_access;
392 		--walker->level;
393 
394 		index = PT_INDEX(addr, walker->level);
395 		table_gfn = gpte_to_gfn(pte);
396 		offset    = index * sizeof(pt_element_t);
397 		pte_gpa   = gfn_to_gpa(table_gfn) + offset;
398 
399 		BUG_ON(walker->level < 1);
400 		walker->table_gfn[walker->level - 1] = table_gfn;
401 		walker->pte_gpa[walker->level - 1] = pte_gpa;
402 
403 		real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
404 					      nested_access,
405 					      &walker->fault);
406 
407 		/*
408 		 * FIXME: This can happen if emulation (for of an INS/OUTS
409 		 * instruction) triggers a nested page fault.  The exit
410 		 * qualification / exit info field will incorrectly have
411 		 * "guest page access" as the nested page fault's cause,
412 		 * instead of "guest page structure access".  To fix this,
413 		 * the x86_exception struct should be augmented with enough
414 		 * information to fix the exit_qualification or exit_info_1
415 		 * fields.
416 		 */
417 		if (unlikely(real_gpa == UNMAPPED_GVA))
418 			return 0;
419 
420 		host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, gpa_to_gfn(real_gpa),
421 					    &walker->pte_writable[walker->level - 1]);
422 		if (unlikely(kvm_is_error_hva(host_addr)))
423 			goto error;
424 
425 		ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
426 		if (unlikely(__get_user(pte, ptep_user)))
427 			goto error;
428 		walker->ptep_user[walker->level - 1] = ptep_user;
429 
430 		trace_kvm_mmu_paging_element(pte, walker->level);
431 
432 		/*
433 		 * Inverting the NX it lets us AND it like other
434 		 * permission bits.
435 		 */
436 		pte_access = pt_access & (pte ^ walk_nx_mask);
437 
438 		if (unlikely(!FNAME(is_present_gpte)(pte)))
439 			goto error;
440 
441 		if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte, walker->level))) {
442 			errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
443 			goto error;
444 		}
445 
446 		walker->ptes[walker->level - 1] = pte;
447 
448 		/* Convert to ACC_*_MASK flags for struct guest_walker.  */
449 		walker->pt_access[walker->level - 1] = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
450 	} while (!FNAME(is_last_gpte)(mmu, walker->level, pte));
451 
452 	pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
453 	accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
454 
455 	/* Convert to ACC_*_MASK flags for struct guest_walker.  */
456 	walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask);
457 	errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
458 	if (unlikely(errcode))
459 		goto error;
460 
461 	gfn = gpte_to_gfn_lvl(pte, walker->level);
462 	gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
463 
464 	if (PTTYPE == 32 && walker->level > PG_LEVEL_4K && is_cpuid_PSE36())
465 		gfn += pse36_gfn_delta(pte);
466 
467 	real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
468 	if (real_gpa == UNMAPPED_GVA)
469 		return 0;
470 
471 	walker->gfn = real_gpa >> PAGE_SHIFT;
472 
473 	if (!write_fault)
474 		FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
475 	else
476 		/*
477 		 * On a write fault, fold the dirty bit into accessed_dirty.
478 		 * For modes without A/D bits support accessed_dirty will be
479 		 * always clear.
480 		 */
481 		accessed_dirty &= pte >>
482 			(PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
483 
484 	if (unlikely(!accessed_dirty)) {
485 		ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker,
486 							addr, write_fault);
487 		if (unlikely(ret < 0))
488 			goto error;
489 		else if (ret)
490 			goto retry_walk;
491 	}
492 
493 	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
494 		 __func__, (u64)pte, walker->pte_access,
495 		 walker->pt_access[walker->level - 1]);
496 	return 1;
497 
498 error:
499 	errcode |= write_fault | user_fault;
500 	if (fetch_fault && (is_efer_nx(mmu) || is_cr4_smep(mmu)))
501 		errcode |= PFERR_FETCH_MASK;
502 
503 	walker->fault.vector = PF_VECTOR;
504 	walker->fault.error_code_valid = true;
505 	walker->fault.error_code = errcode;
506 
507 #if PTTYPE == PTTYPE_EPT
508 	/*
509 	 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
510 	 * misconfiguration requires to be injected. The detection is
511 	 * done by is_rsvd_bits_set() above.
512 	 *
513 	 * We set up the value of exit_qualification to inject:
514 	 * [2:0] - Derive from the access bits. The exit_qualification might be
515 	 *         out of date if it is serving an EPT misconfiguration.
516 	 * [5:3] - Calculated by the page walk of the guest EPT page tables
517 	 * [7:8] - Derived from [7:8] of real exit_qualification
518 	 *
519 	 * The other bits are set to 0.
520 	 */
521 	if (!(errcode & PFERR_RSVD_MASK)) {
522 		vcpu->arch.exit_qualification &= 0x180;
523 		if (write_fault)
524 			vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
525 		if (user_fault)
526 			vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ;
527 		if (fetch_fault)
528 			vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
529 		vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3;
530 	}
531 #endif
532 	walker->fault.address = addr;
533 	walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
534 	walker->fault.async_page_fault = false;
535 
536 	trace_kvm_mmu_walker_error(walker->fault.error_code);
537 	return 0;
538 }
539 
FNAME(walk_addr)540 static int FNAME(walk_addr)(struct guest_walker *walker,
541 			    struct kvm_vcpu *vcpu, gpa_t addr, u32 access)
542 {
543 	return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr,
544 					access);
545 }
546 
547 #if PTTYPE != PTTYPE_EPT
FNAME(walk_addr_nested)548 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
549 				   struct kvm_vcpu *vcpu, gva_t addr,
550 				   u32 access)
551 {
552 	return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
553 					addr, access);
554 }
555 #endif
556 
557 static bool
FNAME(prefetch_gpte)558 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
559 		     u64 *spte, pt_element_t gpte, bool no_dirty_log)
560 {
561 	unsigned pte_access;
562 	gfn_t gfn;
563 	kvm_pfn_t pfn;
564 
565 	if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
566 		return false;
567 
568 	pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
569 
570 	gfn = gpte_to_gfn(gpte);
571 	pte_access = sp->role.access & FNAME(gpte_access)(gpte);
572 	FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
573 	pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
574 			no_dirty_log && (pte_access & ACC_WRITE_MASK));
575 	if (is_error_pfn(pfn))
576 		return false;
577 
578 	/*
579 	 * we call mmu_set_spte() with host_writable = true because
580 	 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
581 	 */
582 	mmu_set_spte(vcpu, spte, pte_access, false, PG_LEVEL_4K, gfn, pfn,
583 		     true, true);
584 
585 	kvm_release_pfn_clean(pfn);
586 	return true;
587 }
588 
FNAME(update_pte)589 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
590 			      u64 *spte, const void *pte)
591 {
592 	pt_element_t gpte = *(const pt_element_t *)pte;
593 
594 	FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
595 }
596 
FNAME(gpte_changed)597 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
598 				struct guest_walker *gw, int level)
599 {
600 	pt_element_t curr_pte;
601 	gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
602 	u64 mask;
603 	int r, index;
604 
605 	if (level == PG_LEVEL_4K) {
606 		mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
607 		base_gpa = pte_gpa & ~mask;
608 		index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
609 
610 		r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
611 				gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
612 		curr_pte = gw->prefetch_ptes[index];
613 	} else
614 		r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
615 				  &curr_pte, sizeof(curr_pte));
616 
617 	return r || curr_pte != gw->ptes[level - 1];
618 }
619 
FNAME(pte_prefetch)620 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
621 				u64 *sptep)
622 {
623 	struct kvm_mmu_page *sp;
624 	pt_element_t *gptep = gw->prefetch_ptes;
625 	u64 *spte;
626 	int i;
627 
628 	sp = sptep_to_sp(sptep);
629 
630 	if (sp->role.level > PG_LEVEL_4K)
631 		return;
632 
633 	/*
634 	 * If addresses are being invalidated, skip prefetching to avoid
635 	 * accidentally prefetching those addresses.
636 	 */
637 	if (unlikely(vcpu->kvm->mmu_notifier_count))
638 		return;
639 
640 	if (sp->role.direct)
641 		return __direct_pte_prefetch(vcpu, sp, sptep);
642 
643 	i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
644 	spte = sp->spt + i;
645 
646 	for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
647 		if (spte == sptep)
648 			continue;
649 
650 		if (is_shadow_present_pte(*spte))
651 			continue;
652 
653 		if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
654 			break;
655 	}
656 }
657 
658 /*
659  * Fetch a shadow pte for a specific level in the paging hierarchy.
660  * If the guest tries to write a write-protected page, we need to
661  * emulate this operation, return 1 to indicate this case.
662  */
FNAME(fetch)663 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr,
664 			 struct guest_walker *gw, u32 error_code,
665 			 int max_level, kvm_pfn_t pfn, bool map_writable,
666 			 bool prefault)
667 {
668 	bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
669 	bool write_fault = error_code & PFERR_WRITE_MASK;
670 	bool exec = error_code & PFERR_FETCH_MASK;
671 	bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
672 	struct kvm_mmu_page *sp = NULL;
673 	struct kvm_shadow_walk_iterator it;
674 	unsigned int direct_access, access;
675 	int top_level, level, req_level, ret;
676 	gfn_t base_gfn = gw->gfn;
677 
678 	direct_access = gw->pte_access;
679 
680 	top_level = vcpu->arch.mmu->root_level;
681 	if (top_level == PT32E_ROOT_LEVEL)
682 		top_level = PT32_ROOT_LEVEL;
683 	/*
684 	 * Verify that the top-level gpte is still there.  Since the page
685 	 * is a root page, it is either write protected (and cannot be
686 	 * changed from now on) or it is invalid (in which case, we don't
687 	 * really care if it changes underneath us after this point).
688 	 */
689 	if (FNAME(gpte_changed)(vcpu, gw, top_level))
690 		goto out_gpte_changed;
691 
692 	if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
693 		goto out_gpte_changed;
694 
695 	for (shadow_walk_init(&it, vcpu, addr);
696 	     shadow_walk_okay(&it) && it.level > gw->level;
697 	     shadow_walk_next(&it)) {
698 		gfn_t table_gfn;
699 
700 		clear_sp_write_flooding_count(it.sptep);
701 		drop_large_spte(vcpu, it.sptep);
702 
703 		sp = NULL;
704 		if (!is_shadow_present_pte(*it.sptep)) {
705 			table_gfn = gw->table_gfn[it.level - 2];
706 			access = gw->pt_access[it.level - 2];
707 			sp = kvm_mmu_get_page(vcpu, table_gfn, addr,
708 					      it.level-1, false, access);
709 			/*
710 			 * We must synchronize the pagetable before linking it
711 			 * because the guest doesn't need to flush tlb when
712 			 * the gpte is changed from non-present to present.
713 			 * Otherwise, the guest may use the wrong mapping.
714 			 *
715 			 * For PG_LEVEL_4K, kvm_mmu_get_page() has already
716 			 * synchronized it transiently via kvm_sync_page().
717 			 *
718 			 * For higher level pagetable, we synchronize it via
719 			 * the slower mmu_sync_children().  If it needs to
720 			 * break, some progress has been made; return
721 			 * RET_PF_RETRY and retry on the next #PF.
722 			 * KVM_REQ_MMU_SYNC is not necessary but it
723 			 * expedites the process.
724 			 */
725 			if (sp->unsync_children &&
726 			    mmu_sync_children(vcpu, sp, false))
727 				return RET_PF_RETRY;
728 		}
729 
730 		/*
731 		 * Verify that the gpte in the page we've just write
732 		 * protected is still there.
733 		 */
734 		if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
735 			goto out_gpte_changed;
736 
737 		if (sp)
738 			link_shadow_page(vcpu, it.sptep, sp);
739 	}
740 
741 	level = kvm_mmu_hugepage_adjust(vcpu, gw->gfn, max_level, &pfn,
742 					huge_page_disallowed, &req_level);
743 
744 	trace_kvm_mmu_spte_requested(addr, gw->level, pfn);
745 
746 	for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
747 		clear_sp_write_flooding_count(it.sptep);
748 
749 		/*
750 		 * We cannot overwrite existing page tables with an NX
751 		 * large page, as the leaf could be executable.
752 		 */
753 		if (nx_huge_page_workaround_enabled)
754 			disallowed_hugepage_adjust(*it.sptep, gw->gfn, it.level,
755 						   &pfn, &level);
756 
757 		base_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
758 		if (it.level == level)
759 			break;
760 
761 		validate_direct_spte(vcpu, it.sptep, direct_access);
762 
763 		drop_large_spte(vcpu, it.sptep);
764 
765 		if (!is_shadow_present_pte(*it.sptep)) {
766 			sp = kvm_mmu_get_page(vcpu, base_gfn, addr,
767 					      it.level - 1, true, direct_access);
768 			link_shadow_page(vcpu, it.sptep, sp);
769 			if (huge_page_disallowed && req_level >= it.level)
770 				account_huge_nx_page(vcpu->kvm, sp);
771 		}
772 	}
773 
774 	ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
775 			   it.level, base_gfn, pfn, prefault, map_writable);
776 	if (ret == RET_PF_SPURIOUS)
777 		return ret;
778 
779 	FNAME(pte_prefetch)(vcpu, gw, it.sptep);
780 	++vcpu->stat.pf_fixed;
781 	return ret;
782 
783 out_gpte_changed:
784 	return RET_PF_RETRY;
785 }
786 
787  /*
788  * To see whether the mapped gfn can write its page table in the current
789  * mapping.
790  *
791  * It is the helper function of FNAME(page_fault). When guest uses large page
792  * size to map the writable gfn which is used as current page table, we should
793  * force kvm to use small page size to map it because new shadow page will be
794  * created when kvm establishes shadow page table that stop kvm using large
795  * page size. Do it early can avoid unnecessary #PF and emulation.
796  *
797  * @write_fault_to_shadow_pgtable will return true if the fault gfn is
798  * currently used as its page table.
799  *
800  * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
801  * since the PDPT is always shadowed, that means, we can not use large page
802  * size to map the gfn which is used as PDPT.
803  */
804 static bool
FNAME(is_self_change_mapping)805 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
806 			      struct guest_walker *walker, bool user_fault,
807 			      bool *write_fault_to_shadow_pgtable)
808 {
809 	int level;
810 	gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
811 	bool self_changed = false;
812 
813 	if (!(walker->pte_access & ACC_WRITE_MASK ||
814 	    (!is_cr0_wp(vcpu->arch.mmu) && !user_fault)))
815 		return false;
816 
817 	for (level = walker->level; level <= walker->max_level; level++) {
818 		gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
819 
820 		self_changed |= !(gfn & mask);
821 		*write_fault_to_shadow_pgtable |= !gfn;
822 	}
823 
824 	return self_changed;
825 }
826 
827 /*
828  * Page fault handler.  There are several causes for a page fault:
829  *   - there is no shadow pte for the guest pte
830  *   - write access through a shadow pte marked read only so that we can set
831  *     the dirty bit
832  *   - write access to a shadow pte marked read only so we can update the page
833  *     dirty bitmap, when userspace requests it
834  *   - mmio access; in this case we will never install a present shadow pte
835  *   - normal guest page fault due to the guest pte marked not present, not
836  *     writable, or not executable
837  *
838  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
839  *           a negative value on error.
840  */
FNAME(page_fault)841 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gpa_t addr, u32 error_code,
842 			     bool prefault)
843 {
844 	bool write_fault = error_code & PFERR_WRITE_MASK;
845 	bool user_fault = error_code & PFERR_USER_MASK;
846 	struct guest_walker walker;
847 	int r;
848 	kvm_pfn_t pfn;
849 	hva_t hva;
850 	unsigned long mmu_seq;
851 	bool map_writable, is_self_change_mapping;
852 	int max_level;
853 
854 	pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
855 
856 	/*
857 	 * If PFEC.RSVD is set, this is a shadow page fault.
858 	 * The bit needs to be cleared before walking guest page tables.
859 	 */
860 	error_code &= ~PFERR_RSVD_MASK;
861 
862 	/*
863 	 * Look up the guest pte for the faulting address.
864 	 */
865 	r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
866 
867 	/*
868 	 * The page is not mapped by the guest.  Let the guest handle it.
869 	 */
870 	if (!r) {
871 		pgprintk("%s: guest page fault\n", __func__);
872 		if (!prefault)
873 			kvm_inject_emulated_page_fault(vcpu, &walker.fault);
874 
875 		return RET_PF_RETRY;
876 	}
877 
878 	if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
879 		shadow_page_table_clear_flood(vcpu, addr);
880 		return RET_PF_EMULATE;
881 	}
882 
883 	r = mmu_topup_memory_caches(vcpu, true);
884 	if (r)
885 		return r;
886 
887 	vcpu->arch.write_fault_to_shadow_pgtable = false;
888 
889 	is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
890 	      &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
891 
892 	if (is_self_change_mapping)
893 		max_level = PG_LEVEL_4K;
894 	else
895 		max_level = walker.level;
896 
897 	mmu_seq = vcpu->kvm->mmu_notifier_seq;
898 	smp_rmb();
899 
900 	if (kvm_faultin_pfn(vcpu, prefault, walker.gfn, addr, &pfn, &hva,
901 			 write_fault, &map_writable, &r))
902 		return r;
903 
904 	if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r))
905 		return r;
906 
907 	/*
908 	 * Do not change pte_access if the pfn is a mmio page, otherwise
909 	 * we will cache the incorrect access into mmio spte.
910 	 */
911 	if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
912 	    !is_cr0_wp(vcpu->arch.mmu) && !user_fault && !is_noslot_pfn(pfn)) {
913 		walker.pte_access |= ACC_WRITE_MASK;
914 		walker.pte_access &= ~ACC_USER_MASK;
915 
916 		/*
917 		 * If we converted a user page to a kernel page,
918 		 * so that the kernel can write to it when cr0.wp=0,
919 		 * then we should prevent the kernel from executing it
920 		 * if SMEP is enabled.
921 		 */
922 		if (is_cr4_smep(vcpu->arch.mmu))
923 			walker.pte_access &= ~ACC_EXEC_MASK;
924 	}
925 
926 	r = RET_PF_RETRY;
927 	write_lock(&vcpu->kvm->mmu_lock);
928 	if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
929 		goto out_unlock;
930 
931 	kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
932 	r = make_mmu_pages_available(vcpu);
933 	if (r)
934 		goto out_unlock;
935 	r = FNAME(fetch)(vcpu, addr, &walker, error_code, max_level, pfn,
936 			 map_writable, prefault);
937 	kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
938 
939 out_unlock:
940 	write_unlock(&vcpu->kvm->mmu_lock);
941 	kvm_release_pfn_clean(pfn);
942 	return r;
943 }
944 
FNAME(get_level1_sp_gpa)945 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
946 {
947 	int offset = 0;
948 
949 	WARN_ON(sp->role.level != PG_LEVEL_4K);
950 
951 	if (PTTYPE == 32)
952 		offset = sp->role.quadrant << PT64_LEVEL_BITS;
953 
954 	return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
955 }
956 
FNAME(invlpg)957 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa)
958 {
959 	struct kvm_shadow_walk_iterator iterator;
960 	struct kvm_mmu_page *sp;
961 	u64 old_spte;
962 	int level;
963 	u64 *sptep;
964 
965 	vcpu_clear_mmio_info(vcpu, gva);
966 
967 	/*
968 	 * No need to check return value here, rmap_can_add() can
969 	 * help us to skip pte prefetch later.
970 	 */
971 	mmu_topup_memory_caches(vcpu, true);
972 
973 	if (!VALID_PAGE(root_hpa)) {
974 		WARN_ON(1);
975 		return;
976 	}
977 
978 	write_lock(&vcpu->kvm->mmu_lock);
979 	for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) {
980 		level = iterator.level;
981 		sptep = iterator.sptep;
982 
983 		sp = sptep_to_sp(sptep);
984 		old_spte = *sptep;
985 		if (is_last_spte(old_spte, level)) {
986 			pt_element_t gpte;
987 			gpa_t pte_gpa;
988 
989 			if (!sp->unsync)
990 				break;
991 
992 			pte_gpa = FNAME(get_level1_sp_gpa)(sp);
993 			pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
994 
995 			mmu_page_zap_pte(vcpu->kvm, sp, sptep, NULL);
996 			if (is_shadow_present_pte(old_spte))
997 				kvm_flush_remote_tlbs_with_address(vcpu->kvm,
998 					sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
999 
1000 			if (!rmap_can_add(vcpu))
1001 				break;
1002 
1003 			if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1004 						       sizeof(pt_element_t)))
1005 				break;
1006 
1007 			FNAME(update_pte)(vcpu, sp, sptep, &gpte);
1008 		}
1009 
1010 		if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
1011 			break;
1012 	}
1013 	write_unlock(&vcpu->kvm->mmu_lock);
1014 }
1015 
1016 /* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */
FNAME(gva_to_gpa)1017 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t addr, u32 access,
1018 			       struct x86_exception *exception)
1019 {
1020 	struct guest_walker walker;
1021 	gpa_t gpa = UNMAPPED_GVA;
1022 	int r;
1023 
1024 	r = FNAME(walk_addr)(&walker, vcpu, addr, access);
1025 
1026 	if (r) {
1027 		gpa = gfn_to_gpa(walker.gfn);
1028 		gpa |= addr & ~PAGE_MASK;
1029 	} else if (exception)
1030 		*exception = walker.fault;
1031 
1032 	return gpa;
1033 }
1034 
1035 #if PTTYPE != PTTYPE_EPT
1036 /* Note, gva_to_gpa_nested() is only used to translate L2 GVAs. */
FNAME(gva_to_gpa_nested)1037 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gpa_t vaddr,
1038 				      u32 access,
1039 				      struct x86_exception *exception)
1040 {
1041 	struct guest_walker walker;
1042 	gpa_t gpa = UNMAPPED_GVA;
1043 	int r;
1044 
1045 #ifndef CONFIG_X86_64
1046 	/* A 64-bit GVA should be impossible on 32-bit KVM. */
1047 	WARN_ON_ONCE(vaddr >> 32);
1048 #endif
1049 
1050 	r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
1051 
1052 	if (r) {
1053 		gpa = gfn_to_gpa(walker.gfn);
1054 		gpa |= vaddr & ~PAGE_MASK;
1055 	} else if (exception)
1056 		*exception = walker.fault;
1057 
1058 	return gpa;
1059 }
1060 #endif
1061 
1062 /*
1063  * Using the cached information from sp->gfns is safe because:
1064  * - The spte has a reference to the struct page, so the pfn for a given gfn
1065  *   can't change unless all sptes pointing to it are nuked first.
1066  */
FNAME(sync_page)1067 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1068 {
1069 	union kvm_mmu_page_role mmu_role = vcpu->arch.mmu->mmu_role.base;
1070 	int i, nr_present = 0;
1071 	bool host_writable;
1072 	gpa_t first_pte_gpa;
1073 	int set_spte_ret = 0;
1074 
1075 	/*
1076 	 * Ignore various flags when verifying that it's safe to sync a shadow
1077 	 * page using the current MMU context.
1078 	 *
1079 	 *  - level: not part of the overall MMU role and will never match as the MMU's
1080 	 *           level tracks the root level
1081 	 *  - access: updated based on the new guest PTE
1082 	 *  - quadrant: not part of the overall MMU role (similar to level)
1083 	 */
1084 	const union kvm_mmu_page_role sync_role_ign = {
1085 		.level = 0xf,
1086 		.access = 0x7,
1087 		.quadrant = 0x3,
1088 	};
1089 
1090 	/*
1091 	 * Direct pages can never be unsync, and KVM should never attempt to
1092 	 * sync a shadow page for a different MMU context, e.g. if the role
1093 	 * differs then the memslot lookup (SMM vs. non-SMM) will be bogus, the
1094 	 * reserved bits checks will be wrong, etc...
1095 	 */
1096 	if (WARN_ON_ONCE(sp->role.direct ||
1097 			 (sp->role.word ^ mmu_role.word) & ~sync_role_ign.word))
1098 		return 0;
1099 
1100 	first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
1101 
1102 	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
1103 		unsigned pte_access;
1104 		pt_element_t gpte;
1105 		gpa_t pte_gpa;
1106 		gfn_t gfn;
1107 
1108 		if (!sp->spt[i])
1109 			continue;
1110 
1111 		pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
1112 
1113 		if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1114 					       sizeof(pt_element_t)))
1115 			return 0;
1116 
1117 		if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
1118 			set_spte_ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
1119 			continue;
1120 		}
1121 
1122 		gfn = gpte_to_gfn(gpte);
1123 		pte_access = sp->role.access;
1124 		pte_access &= FNAME(gpte_access)(gpte);
1125 		FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
1126 
1127 		if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1128 		      &nr_present))
1129 			continue;
1130 
1131 		if (gfn != sp->gfns[i]) {
1132 			drop_spte(vcpu->kvm, &sp->spt[i]);
1133 			set_spte_ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
1134 			continue;
1135 		}
1136 
1137 		nr_present++;
1138 
1139 		host_writable = sp->spt[i] & shadow_host_writable_mask;
1140 
1141 		set_spte_ret |= set_spte(vcpu, &sp->spt[i],
1142 					 pte_access, PG_LEVEL_4K,
1143 					 gfn, spte_to_pfn(sp->spt[i]),
1144 					 true, false, host_writable);
1145 	}
1146 
1147 	if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH)
1148 		kvm_flush_remote_tlbs(vcpu->kvm);
1149 
1150 	return nr_present;
1151 }
1152 
1153 #undef pt_element_t
1154 #undef guest_walker
1155 #undef FNAME
1156 #undef PT_BASE_ADDR_MASK
1157 #undef PT_INDEX
1158 #undef PT_LVL_ADDR_MASK
1159 #undef PT_LVL_OFFSET_MASK
1160 #undef PT_LEVEL_BITS
1161 #undef PT_MAX_FULL_LEVELS
1162 #undef gpte_to_gfn
1163 #undef gpte_to_gfn_lvl
1164 #undef CMPXCHG
1165 #undef PT_GUEST_ACCESSED_MASK
1166 #undef PT_GUEST_DIRTY_MASK
1167 #undef PT_GUEST_DIRTY_SHIFT
1168 #undef PT_GUEST_ACCESSED_SHIFT
1169 #undef PT_HAVE_ACCESSED_DIRTY
1170