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Searched refs:write_sysreg_s (Results 1 – 12 of 12) sorted by relevance

/arch/arm64/include/asm/
Darm_dsu_pmu.h40 write_sysreg_s(val, CLUSTERPMCR_EL1); in __dsu_pmu_write_pmcr()
48 write_sysreg_s(val, CLUSTERPMOVSCLR_EL1); in __dsu_pmu_get_reset_overflow()
55 write_sysreg_s(counter, CLUSTERPMSELR_EL1); in __dsu_pmu_select_counter()
68 write_sysreg_s(val, CLUSTERPMXEVCNTR_EL1); in __dsu_pmu_write_counter()
75 write_sysreg_s(event, CLUSTERPMXEVTYPER_EL1); in __dsu_pmu_set_event()
86 write_sysreg_s(val, CLUSTERPMCCNTR_EL1); in __dsu_pmu_write_pmccntr()
92 write_sysreg_s(BIT(counter), CLUSTERPMCNTENCLR_EL1); in __dsu_pmu_disable_counter()
98 write_sysreg_s(BIT(counter), CLUSTERPMCNTENSET_EL1); in __dsu_pmu_enable_counter()
104 write_sysreg_s(BIT(counter), CLUSTERPMINTENSET_EL1); in __dsu_pmu_counter_interrupt_enable()
110 write_sysreg_s(BIT(counter), CLUSTERPMINTENCLR_EL1); in __dsu_pmu_counter_interrupt_disable()
Darch_gicv3.h20 #define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
31 write_sysreg_s(irq, SYS_ICC_DIR_EL1); in gic_write_dir()
65 write_sysreg_s(val, SYS_ICC_CTLR_EL1); in gic_write_ctlr()
76 write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1); in gic_write_grpen1()
82 write_sysreg_s(val, SYS_ICC_SGI1R_EL1); in gic_write_sgi1r()
92 write_sysreg_s(val, SYS_ICC_SRE_EL1); in gic_write_sre()
98 write_sysreg_s(val, SYS_ICC_BPR1_EL1); in gic_write_bpr1()
108 write_sysreg_s(val, SYS_ICC_PMR_EL1); in gic_write_pmr()
Dkvm_host.h662 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; in __vcpu_write_sys_reg_to_cpu()
663 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; in __vcpu_write_sys_reg_to_cpu()
664 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; in __vcpu_write_sys_reg_to_cpu()
665 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; in __vcpu_write_sys_reg_to_cpu()
666 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; in __vcpu_write_sys_reg_to_cpu()
667 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; in __vcpu_write_sys_reg_to_cpu()
668 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; in __vcpu_write_sys_reg_to_cpu()
669 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; in __vcpu_write_sys_reg_to_cpu()
670 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; in __vcpu_write_sys_reg_to_cpu()
671 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; in __vcpu_write_sys_reg_to_cpu()
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Dpointer_auth.h40 write_sysreg_s(__pki_v.lo, SYS_ ## k ## KEYLO_EL1); \
41 write_sysreg_s(__pki_v.hi, SYS_ ## k ## KEYHI_EL1); \
Dfpsimd.h139 write_sysreg_s(__new, (reg)); \
Dsysreg.h1313 #define write_sysreg_s(v, r) do { \ macro
1333 write_sysreg_s(__scs_new, sysreg); \
/arch/arm64/kvm/hyp/nvhe/
Ddebug-sr.c35 write_sysreg_s(0, SYS_PMSCR_EL1); in __debug_save_spe()
52 write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1); in __debug_restore_spe()
68 write_sysreg_s(0, SYS_TRFCR_EL1); in __debug_save_trace()
81 write_sysreg_s(trfcr_el1, SYS_TRFCR_EL1); in __debug_restore_trace()
/arch/arm64/kernel/
Dmte.c190 write_sysreg_s(0, SYS_TFSR_EL1); in mte_check_tfsr_el1()
244 write_sysreg_s( in mte_update_gcr_excl()
266 write_sysreg_s(0, SYS_TFSRE0_EL1); in mte_thread_init_user()
313 write_sysreg_s(KERNEL_GCR_EL1, SYS_GCR_EL1); in mte_cpu_setup()
325 write_sysreg_s(rgsr, SYS_RGSR_EL1); in mte_cpu_setup()
328 write_sysreg_s(0, SYS_TFSR_EL1); in mte_cpu_setup()
329 write_sysreg_s(0, SYS_TFSRE0_EL1); in mte_cpu_setup()
Dfpsimd.c712 write_sysreg_s(zcr | (vq - 1), SYS_ZCR_EL1); /* self-syncing */ in sve_probe_vqs()
844 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); in read_zcr_features()
Dcpufeature.c1781 write_sysreg_s(0, SYS_DISR_EL1); in cpu_clear_disr()
/arch/arm64/kvm/hyp/include/hyp/
Dsysreg-sr.h133 write_sysreg_s(ctxt_sys_reg(ctxt, TFSRE0_EL1), SYS_TFSRE0_EL1); in __sysreg_restore_el1_state()
182 write_sysreg_s(ctxt_sys_reg(ctxt, DISR_EL1), SYS_VDISR_EL2); in __sysreg_restore_el2_return_state()
Dswitch.h116 write_sysreg_s(vcpu->arch.vsesr_el2, SYS_VSESR_EL2); in ___activate_traps()