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Searched refs:BIT_3 (Results 1 – 24 of 24) sorted by relevance

/drivers/scsi/qla2xxx/
Dqla_fw.h456 #define BD_WRAP_BACK BIT_3
496 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
813 #define ECF_SEC_LOGIN BIT_3
972 #define TCF_ABORT_TASK_SET BIT_3
1003 #define AOF_ABTS_RTY_CNT BIT_3 /* Use driver specified retry count. */
1199 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
1202 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
1257 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
1262 #define GPDX_LED_GREEN_ON BIT_3
1395 #define MDBS_NON_PARTIC BIT_3
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Dqla_def.h106 #define BIT_3 0x8 macro
228 #define IDC_HEARTBEAT_FAILURE BIT_3
503 #define SRB_LOGIN_NVME_PRLI BIT_3
553 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
783 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
789 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
792 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
800 #define NVR_DATA_IN BIT_3
1195 #define FO1_CTIO_RETRY BIT_3
1374 #define MBX_3 BIT_3
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Dqla_nvme.h58 #define CF_DIF_SEG_DESCR_ENABLE BIT_3
Dqla_target.h180 #define NOTIFY_ACK_FLAGS_TERMINATE BIT_3
512 #define CTIO_CRC2_AF_DIF_DSD_ENA BIT_3
846 TRC_XFR_RDY = BIT_3,
Dqla_init.c1172 mb[1] = BIT_2 | BIT_3; in qla24xx_async_gnl()
4475 (BIT_4 | BIT_3)) >> 3; in qla2x00_update_fw_options()
4477 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4495 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4523 ha->fw_options[2] |= BIT_3; in qla2x00_update_fw_options()
4548 ha->fw_options[2] |= BIT_3; in qla24xx_update_fw_options()
5261 nv->firmware_options[0] = BIT_3 | BIT_1; in qla2x00_nvram_config()
5304 nv->firmware_options[0] &= ~BIT_3; in qla2x00_nvram_config()
5382 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); in qla2x00_nvram_config()
5457 icb->firmware_options[0] &= ~BIT_3; in qla2x00_nvram_config()
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Dqla_inline.h389 RESOURCE_HA = BIT_3,
Dqla_gbl.h1000 #define QLA2XX_CMD_TIMEOUT BIT_3
Dqla_mbx.c669 #define NVME_ENABLE_FLAG BIT_3
4256 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; in qla24xx_modify_vp_config()
6364 } else if (subcode & (BIT_3 | BIT_4)) { in qla83xx_access_control()
6651 if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0) in __qla24xx_parse_gpdb()
6967 if (options & BIT_3) { in ql26xx_led_config()
Dqla_attr.c1392 options |= BIT_3|BIT_2|BIT_1; in qla2x00_beacon_config_store()
1409 options |= BIT_3; in qla2x00_beacon_config_store()
Dqla_isr.c4020 if (rd_reg_dword(&reg->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()
/drivers/scsi/
Dqla1280.h20 #define BIT_3 0x8 macro
123 #define ISP_CFG0_1040A BIT_3 /* ISP1040A */
149 #define NV_DATA_IN BIT_3
157 #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
174 #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
570 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
Dqla1280.c1123 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1703 #define CMD_ARGS (BIT_7 | BIT_6 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1707 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1908 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1922 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2215 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
2838 pkt->control_flags |= cpu_to_le16(BIT_3); in qla1280_64bit_start_scsi()
3093 pkt->control_flags |= cpu_to_le16(BIT_3); in qla1280_32bit_start_scsi()
3701 if (pkt->entry_status & BIT_3) in qla1280_error_entry()
3721 if (pkt->entry_status & (BIT_3 + BIT_2)) { in qla1280_error_entry()
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/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_ctx.c1348 arg1 &= ~(BIT_2 | BIT_3); in qlcnic_config_switch_port()
1354 arg2 |= (BIT_2 | BIT_3); in qlcnic_config_switch_port()
1364 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()
1368 arg2 &= ~BIT_3; in qlcnic_config_switch_port()
1376 arg1 |= (BIT_3 | BIT_5); in qlcnic_config_switch_port()
Dqlcnic_hdr.h198 #define BIT_3 0x8 macro
495 #define TA_CTL_BUSY BIT_3
Dqlcnic.h922 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
1317 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
Dqlcnic_dcb.c553 if (mbx_out & BIT_3) in qlcnic_83xx_dcb_get_hw_capability()
Dqlcnic_minidump.c26 #define QLCNIC_DUMP_ORCRB BIT_3
Dqlcnic_sriov_pf.c703 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8; in qlcnic_sriov_set_vf_acl()
Dqlcnic_83xx_init.c1024 #define QLC_83XX_SET_VXLAN_UDP_DPORT BIT_3
Dqlcnic_sriov_common.c386 if (status & BIT_3) in qlcnic_sriov_get_vf_vport_info()
Dqlcnic_io.c365 #define QLCNIC_ENCAP_INNER_L4_UDP BIT_3
Dqlcnic_83xx_hw.c2023 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
/drivers/scsi/qla4xxx/
Dql4_def.h84 #define BIT_3 0x8 macro
231 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
Dql4_os.c3556 conn->tcp_timer_scale |= BIT_3; in qla4xxx_copy_from_fwddb_param()
3663 SET_BITVAL(sess->entry_state, options, BIT_3); in qla4xxx_copy_to_fwddb_param()
3677 SET_BITVAL(sess->discovery_auth_optional, options, BIT_3); in qla4xxx_copy_to_fwddb_param()
3686 SET_BITVAL(conn->tcp_timer_scale & BIT_2, options, BIT_3); in qla4xxx_copy_to_fwddb_param()
3793 conn->tcp_timer_scale |= BIT_3; in qla4xxx_copy_to_sess_conn_params()