Searched refs:DC__VOLTAGE_STATES (Results 1 – 12 of 12) sorted by relevance
371 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];372 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];420 double DCFCLKPerState[DC__VOLTAGE_STATES];421 double DCFCLKState[DC__VOLTAGE_STATES][2];422 double FabricClockPerState[DC__VOLTAGE_STATES];423 double SOCCLKPerState[DC__VOLTAGE_STATES];424 double PHYCLKPerState[DC__VOLTAGE_STATES];425 double DTBCLKPerState[DC__VOLTAGE_STATES];426 double MaxDppclk[DC__VOLTAGE_STATES];427 double MaxDSCCLK[DC__VOLTAGE_STATES];[all …]
73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
32 #define DC__VOLTAGE_STATES 9 macro
1217 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box()1218 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box()1219 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box()1220 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box()1222 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn303_update_bw_bounding_box()1296 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_update_bw_bounding_box()1311 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_update_bw_bounding_box()1316 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn303_update_bw_bounding_box()
1287 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box()1288 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box()1289 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box()1290 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box()1292 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn302_update_bw_bounding_box()1369 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()1383 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_update_bw_bounding_box()1388 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn302_update_bw_bounding_box()
2386 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()2387 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()2388 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()2389 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()2391 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box()2470 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()2484 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()2489 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
1579 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in dcn301_update_bw_bounding_box()
1595 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in update_bw_bounding_box()
1866 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in dcn31_update_bw_bounding_box()
3513 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES]; in dcn20_update_bounding_box()
6727 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } }; in UseMinimumDCFCLK()
7096 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];