1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn31_resource.h"
35
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
38
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn30/dcn30_hubbub.h"
41 #include "dcn31/dcn31_hubbub.h"
42 #include "dcn30/dcn30_mpc.h"
43 #include "dcn31/dcn31_hubp.h"
44 #include "irq/dcn31/irq_service_dcn31.h"
45 #include "dcn30/dcn30_dpp.h"
46 #include "dcn31/dcn31_optc.h"
47 #include "dcn20/dcn20_hwseq.h"
48 #include "dcn30/dcn30_hwseq.h"
49 #include "dce110/dce110_hw_sequencer.h"
50 #include "dcn30/dcn30_opp.h"
51 #include "dcn20/dcn20_dsc.h"
52 #include "dcn30/dcn30_vpg.h"
53 #include "dcn30/dcn30_afmt.h"
54 #include "dcn30/dcn30_dio_stream_encoder.h"
55 #include "dcn31/dcn31_dio_link_encoder.h"
56 #include "dce/dce_clock_source.h"
57 #include "dce/dce_audio.h"
58 #include "dce/dce_hwseq.h"
59 #include "clk_mgr.h"
60 #include "virtual/virtual_stream_encoder.h"
61 #include "dce110/dce110_resource.h"
62 #include "dml/display_mode_vba.h"
63 #include "dcn31/dcn31_dccg.h"
64 #include "dcn10/dcn10_resource.h"
65 #include "dcn31_panel_cntl.h"
66
67 #include "dcn30/dcn30_dwb.h"
68 #include "dcn30/dcn30_mmhubbub.h"
69
70 // TODO: change include headers /amd/include/asic_reg after upstream
71 #include "yellow_carp_offset.h"
72 #include "dcn/dcn_3_1_2_offset.h"
73 #include "dcn/dcn_3_1_2_sh_mask.h"
74 #include "nbio/nbio_7_2_0_offset.h"
75 #include "dpcs/dpcs_4_2_0_offset.h"
76 #include "dpcs/dpcs_4_2_0_sh_mask.h"
77 #include "mmhub/mmhub_2_3_0_offset.h"
78 #include "mmhub/mmhub_2_3_0_sh_mask.h"
79
80
81 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
82 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
83 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
84 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
85
86 #include "reg_helper.h"
87 #include "dce/dmub_abm.h"
88 #include "dce/dmub_psr.h"
89 #include "dce/dce_aux.h"
90 #include "dce/dce_i2c.h"
91
92 #include "dml/dcn30/display_mode_vba_30.h"
93 #include "vm_helper.h"
94 #include "dcn20/dcn20_vmid.h"
95
96 #include "link_enc_cfg.h"
97
98 #define DC_LOGGER_INIT(logger)
99 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
100 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
101
102 #define DCN3_1_DEFAULT_DET_SIZE 384
103
104 struct _vcs_dpi_ip_params_st dcn3_1_ip = {
105 .gpuvm_enable = 1,
106 .gpuvm_max_page_table_levels = 1,
107 .hostvm_enable = 1,
108 .hostvm_max_page_table_levels = 2,
109 .rob_buffer_size_kbytes = 64,
110 .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
111 .config_return_buffer_size_in_kbytes = 1792,
112 .compressed_buffer_segment_size_in_kbytes = 64,
113 .meta_fifo_size_in_kentries = 32,
114 .zero_size_buffer_entries = 512,
115 .compbuf_reserved_space_64b = 256,
116 .compbuf_reserved_space_zs = 64,
117 .dpp_output_buffer_pixels = 2560,
118 .opp_output_buffer_lines = 1,
119 .pixel_chunk_size_kbytes = 8,
120 .meta_chunk_size_kbytes = 2,
121 .min_meta_chunk_size_bytes = 256,
122 .writeback_chunk_size_kbytes = 8,
123 .ptoi_supported = false,
124 .num_dsc = 3,
125 .maximum_dsc_bits_per_component = 10,
126 .dsc422_native_support = false,
127 .is_line_buffer_bpp_fixed = true,
128 .line_buffer_fixed_bpp = 48,
129 .line_buffer_size_bits = 789504,
130 .max_line_buffer_lines = 12,
131 .writeback_interface_buffer_size_kbytes = 90,
132 .max_num_dpp = 4,
133 .max_num_otg = 4,
134 .max_num_hdmi_frl_outputs = 1,
135 .max_num_wb = 1,
136 .max_dchub_pscl_bw_pix_per_clk = 4,
137 .max_pscl_lb_bw_pix_per_clk = 2,
138 .max_lb_vscl_bw_pix_per_clk = 4,
139 .max_vscl_hscl_bw_pix_per_clk = 4,
140 .max_hscl_ratio = 6,
141 .max_vscl_ratio = 6,
142 .max_hscl_taps = 8,
143 .max_vscl_taps = 8,
144 .dpte_buffer_size_in_pte_reqs_luma = 64,
145 .dpte_buffer_size_in_pte_reqs_chroma = 34,
146 .dispclk_ramp_margin_percent = 1,
147 .max_inter_dcn_tile_repeaters = 8,
148 .cursor_buffer_size = 16,
149 .cursor_chunk_size = 2,
150 .writeback_line_buffer_buffer_size = 0,
151 .writeback_min_hscl_ratio = 1,
152 .writeback_min_vscl_ratio = 1,
153 .writeback_max_hscl_ratio = 1,
154 .writeback_max_vscl_ratio = 1,
155 .writeback_max_hscl_taps = 1,
156 .writeback_max_vscl_taps = 1,
157 .dppclk_delay_subtotal = 46,
158 .dppclk_delay_scl = 50,
159 .dppclk_delay_scl_lb_only = 16,
160 .dppclk_delay_cnvc_formatter = 27,
161 .dppclk_delay_cnvc_cursor = 6,
162 .dispclk_delay_subtotal = 119,
163 .dynamic_metadata_vm_enabled = false,
164 .odm_combine_4to1_supported = false,
165 .dcc_supported = true,
166 };
167
168 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
169 /*TODO: correct dispclk/dppclk voltage level determination*/
170 .clock_limits = {
171 {
172 .state = 0,
173 .dispclk_mhz = 1200.0,
174 .dppclk_mhz = 1200.0,
175 .phyclk_mhz = 600.0,
176 .phyclk_d18_mhz = 667.0,
177 .dscclk_mhz = 186.0,
178 .dtbclk_mhz = 625.0,
179 },
180 {
181 .state = 1,
182 .dispclk_mhz = 1200.0,
183 .dppclk_mhz = 1200.0,
184 .phyclk_mhz = 810.0,
185 .phyclk_d18_mhz = 667.0,
186 .dscclk_mhz = 209.0,
187 .dtbclk_mhz = 625.0,
188 },
189 {
190 .state = 2,
191 .dispclk_mhz = 1200.0,
192 .dppclk_mhz = 1200.0,
193 .phyclk_mhz = 810.0,
194 .phyclk_d18_mhz = 667.0,
195 .dscclk_mhz = 209.0,
196 .dtbclk_mhz = 625.0,
197 },
198 {
199 .state = 3,
200 .dispclk_mhz = 1200.0,
201 .dppclk_mhz = 1200.0,
202 .phyclk_mhz = 810.0,
203 .phyclk_d18_mhz = 667.0,
204 .dscclk_mhz = 371.0,
205 .dtbclk_mhz = 625.0,
206 },
207 {
208 .state = 4,
209 .dispclk_mhz = 1200.0,
210 .dppclk_mhz = 1200.0,
211 .phyclk_mhz = 810.0,
212 .phyclk_d18_mhz = 667.0,
213 .dscclk_mhz = 417.0,
214 .dtbclk_mhz = 625.0,
215 },
216 },
217 .num_states = 5,
218 .sr_exit_time_us = 9.0,
219 .sr_enter_plus_exit_time_us = 11.0,
220 .sr_exit_z8_time_us = 442.0,
221 .sr_enter_plus_exit_z8_time_us = 560.0,
222 .writeback_latency_us = 12.0,
223 .dram_channel_width_bytes = 4,
224 .round_trip_ping_latency_dcfclk_cycles = 106,
225 .urgent_latency_pixel_data_only_us = 4.0,
226 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
227 .urgent_latency_vm_data_only_us = 4.0,
228 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
229 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
230 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
231 .pct_ideal_sdp_bw_after_urgent = 80.0,
232 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
233 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
234 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
235 .max_avg_sdp_bw_use_normal_percent = 60.0,
236 .max_avg_dram_bw_use_normal_percent = 60.0,
237 .fabric_datapath_to_dcn_data_return_bytes = 32,
238 .return_bus_width_bytes = 64,
239 .downspread_percent = 0.38,
240 .dcn_downspread_percent = 0.5,
241 .gpuvm_min_page_size_bytes = 4096,
242 .hostvm_min_page_size_bytes = 4096,
243 .do_urgent_latency_adjustment = false,
244 .urgent_latency_adjustment_fabric_clock_component_us = 0,
245 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
246 };
247
248 enum dcn31_clk_src_array_id {
249 DCN31_CLK_SRC_PLL0,
250 DCN31_CLK_SRC_PLL1,
251 DCN31_CLK_SRC_PLL2,
252 DCN31_CLK_SRC_PLL3,
253 DCN31_CLK_SRC_PLL4,
254 DCN30_CLK_SRC_TOTAL
255 };
256
257 /* begin *********************
258 * macros to expend register list macro defined in HW object header file
259 */
260
261 /* DCN */
262 /* TODO awful hack. fixup dcn20_dwb.h */
263 #undef BASE_INNER
264 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
265
266 #define BASE(seg) BASE_INNER(seg)
267
268 #define SR(reg_name)\
269 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
270 reg ## reg_name
271
272 #define SRI(reg_name, block, id)\
273 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
274 reg ## block ## id ## _ ## reg_name
275
276 #define SRI2(reg_name, block, id)\
277 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
278 reg ## reg_name
279
280 #define SRIR(var_name, reg_name, block, id)\
281 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
282 reg ## block ## id ## _ ## reg_name
283
284 #define SRII(reg_name, block, id)\
285 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
286 reg ## block ## id ## _ ## reg_name
287
288 #define SRII_MPC_RMU(reg_name, block, id)\
289 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
290 reg ## block ## id ## _ ## reg_name
291
292 #define SRII_DWB(reg_name, temp_name, block, id)\
293 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
294 reg ## block ## id ## _ ## temp_name
295
296 #define DCCG_SRII(reg_name, block, id)\
297 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
298 reg ## block ## id ## _ ## reg_name
299
300 #define VUPDATE_SRII(reg_name, block, id)\
301 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
302 reg ## reg_name ## _ ## block ## id
303
304 /* NBIO */
305 #define NBIO_BASE_INNER(seg) \
306 NBIO_BASE__INST0_SEG ## seg
307
308 #define NBIO_BASE(seg) \
309 NBIO_BASE_INNER(seg)
310
311 #define NBIO_SR(reg_name)\
312 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
313 regBIF_BX1_ ## reg_name
314
315 /* MMHUB */
316 #define MMHUB_BASE_INNER(seg) \
317 MMHUB_BASE__INST0_SEG ## seg
318
319 #define MMHUB_BASE(seg) \
320 MMHUB_BASE_INNER(seg)
321
322 #define MMHUB_SR(reg_name)\
323 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
324 mm ## reg_name
325
326 /* CLOCK */
327 #define CLK_BASE_INNER(seg) \
328 CLK_BASE__INST0_SEG ## seg
329
330 #define CLK_BASE(seg) \
331 CLK_BASE_INNER(seg)
332
333 #define CLK_SRI(reg_name, block, inst)\
334 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
335 reg ## block ## _ ## inst ## _ ## reg_name
336
337
338 static const struct bios_registers bios_regs = {
339 NBIO_SR(BIOS_SCRATCH_3),
340 NBIO_SR(BIOS_SCRATCH_6)
341 };
342
343 #define clk_src_regs(index, pllid)\
344 [index] = {\
345 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
346 }
347
348 static const struct dce110_clk_src_regs clk_src_regs[] = {
349 clk_src_regs(0, A),
350 clk_src_regs(1, B),
351 clk_src_regs(2, C),
352 clk_src_regs(3, D),
353 clk_src_regs(4, E)
354 };
355 /*pll_id being rempped in dmub, in driver it is logical instance*/
356 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
357 clk_src_regs(0, A),
358 clk_src_regs(1, B),
359 clk_src_regs(2, F),
360 clk_src_regs(3, G),
361 clk_src_regs(4, E)
362 };
363
364 static const struct dce110_clk_src_shift cs_shift = {
365 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
366 };
367
368 static const struct dce110_clk_src_mask cs_mask = {
369 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
370 };
371
372 #define abm_regs(id)\
373 [id] = {\
374 ABM_DCN301_REG_LIST(id)\
375 }
376
377 static const struct dce_abm_registers abm_regs[] = {
378 abm_regs(0),
379 abm_regs(1),
380 abm_regs(2),
381 abm_regs(3),
382 };
383
384 static const struct dce_abm_shift abm_shift = {
385 ABM_MASK_SH_LIST_DCN30(__SHIFT)
386 };
387
388 static const struct dce_abm_mask abm_mask = {
389 ABM_MASK_SH_LIST_DCN30(_MASK)
390 };
391
392 #define audio_regs(id)\
393 [id] = {\
394 AUD_COMMON_REG_LIST(id)\
395 }
396
397 static const struct dce_audio_registers audio_regs[] = {
398 audio_regs(0),
399 audio_regs(1),
400 audio_regs(2),
401 audio_regs(3),
402 audio_regs(4),
403 audio_regs(5),
404 audio_regs(6)
405 };
406
407 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
408 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
409 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
410 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
411
412 static const struct dce_audio_shift audio_shift = {
413 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
414 };
415
416 static const struct dce_audio_mask audio_mask = {
417 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
418 };
419
420 #define vpg_regs(id)\
421 [id] = {\
422 VPG_DCN3_REG_LIST(id)\
423 }
424
425 static const struct dcn30_vpg_registers vpg_regs[] = {
426 vpg_regs(0),
427 vpg_regs(1),
428 vpg_regs(2),
429 vpg_regs(3),
430 vpg_regs(4),
431 vpg_regs(5),
432 vpg_regs(6),
433 vpg_regs(7),
434 vpg_regs(8),
435 vpg_regs(9),
436 };
437
438 static const struct dcn30_vpg_shift vpg_shift = {
439 DCN3_VPG_MASK_SH_LIST(__SHIFT)
440 };
441
442 static const struct dcn30_vpg_mask vpg_mask = {
443 DCN3_VPG_MASK_SH_LIST(_MASK)
444 };
445
446 #define afmt_regs(id)\
447 [id] = {\
448 AFMT_DCN3_REG_LIST(id)\
449 }
450
451 static const struct dcn30_afmt_registers afmt_regs[] = {
452 afmt_regs(0),
453 afmt_regs(1),
454 afmt_regs(2),
455 afmt_regs(3),
456 afmt_regs(4),
457 afmt_regs(5)
458 };
459
460 static const struct dcn30_afmt_shift afmt_shift = {
461 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
462 };
463
464 static const struct dcn30_afmt_mask afmt_mask = {
465 DCN3_AFMT_MASK_SH_LIST(_MASK)
466 };
467
468 #define stream_enc_regs(id)\
469 [id] = {\
470 SE_DCN3_REG_LIST(id)\
471 }
472
473 /* Some encoders won't be initialized here - but they're logical, not physical. */
474 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
475 stream_enc_regs(0),
476 stream_enc_regs(1),
477 stream_enc_regs(2),
478 stream_enc_regs(3),
479 stream_enc_regs(4)
480 };
481
482 static const struct dcn10_stream_encoder_shift se_shift = {
483 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
484 };
485
486 static const struct dcn10_stream_encoder_mask se_mask = {
487 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
488 };
489
490
491 #define aux_regs(id)\
492 [id] = {\
493 DCN2_AUX_REG_LIST(id)\
494 }
495
496 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
497 aux_regs(0),
498 aux_regs(1),
499 aux_regs(2),
500 aux_regs(3),
501 aux_regs(4)
502 };
503
504 #define hpd_regs(id)\
505 [id] = {\
506 HPD_REG_LIST(id)\
507 }
508
509 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
510 hpd_regs(0),
511 hpd_regs(1),
512 hpd_regs(2),
513 hpd_regs(3),
514 hpd_regs(4)
515 };
516
517 #define link_regs(id, phyid)\
518 [id] = {\
519 LE_DCN31_REG_LIST(id), \
520 UNIPHY_DCN2_REG_LIST(phyid), \
521 DPCS_DCN31_REG_LIST(id), \
522 }
523
524 static const struct dce110_aux_registers_shift aux_shift = {
525 DCN_AUX_MASK_SH_LIST(__SHIFT)
526 };
527
528 static const struct dce110_aux_registers_mask aux_mask = {
529 DCN_AUX_MASK_SH_LIST(_MASK)
530 };
531
532 static const struct dcn10_link_enc_registers link_enc_regs[] = {
533 link_regs(0, A),
534 link_regs(1, B),
535 link_regs(2, C),
536 link_regs(3, D),
537 link_regs(4, E)
538 };
539
540 static const struct dcn10_link_enc_shift le_shift = {
541 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
542 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
543 };
544
545 static const struct dcn10_link_enc_mask le_mask = {
546 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
547 DPCS_DCN31_MASK_SH_LIST(_MASK)
548 };
549
550 #define dpp_regs(id)\
551 [id] = {\
552 DPP_REG_LIST_DCN30(id),\
553 }
554
555 static const struct dcn3_dpp_registers dpp_regs[] = {
556 dpp_regs(0),
557 dpp_regs(1),
558 dpp_regs(2),
559 dpp_regs(3)
560 };
561
562 static const struct dcn3_dpp_shift tf_shift = {
563 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
564 };
565
566 static const struct dcn3_dpp_mask tf_mask = {
567 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
568 };
569
570 #define opp_regs(id)\
571 [id] = {\
572 OPP_REG_LIST_DCN30(id),\
573 }
574
575 static const struct dcn20_opp_registers opp_regs[] = {
576 opp_regs(0),
577 opp_regs(1),
578 opp_regs(2),
579 opp_regs(3)
580 };
581
582 static const struct dcn20_opp_shift opp_shift = {
583 OPP_MASK_SH_LIST_DCN20(__SHIFT)
584 };
585
586 static const struct dcn20_opp_mask opp_mask = {
587 OPP_MASK_SH_LIST_DCN20(_MASK)
588 };
589
590 #define aux_engine_regs(id)\
591 [id] = {\
592 AUX_COMMON_REG_LIST0(id), \
593 .AUXN_IMPCAL = 0, \
594 .AUXP_IMPCAL = 0, \
595 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
596 }
597
598 static const struct dce110_aux_registers aux_engine_regs[] = {
599 aux_engine_regs(0),
600 aux_engine_regs(1),
601 aux_engine_regs(2),
602 aux_engine_regs(3),
603 aux_engine_regs(4)
604 };
605
606 #define dwbc_regs_dcn3(id)\
607 [id] = {\
608 DWBC_COMMON_REG_LIST_DCN30(id),\
609 }
610
611 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
612 dwbc_regs_dcn3(0),
613 };
614
615 static const struct dcn30_dwbc_shift dwbc30_shift = {
616 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
617 };
618
619 static const struct dcn30_dwbc_mask dwbc30_mask = {
620 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
621 };
622
623 #define mcif_wb_regs_dcn3(id)\
624 [id] = {\
625 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
626 }
627
628 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
629 mcif_wb_regs_dcn3(0)
630 };
631
632 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
633 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
634 };
635
636 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
637 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
638 };
639
640 #define dsc_regsDCN20(id)\
641 [id] = {\
642 DSC_REG_LIST_DCN20(id)\
643 }
644
645 static const struct dcn20_dsc_registers dsc_regs[] = {
646 dsc_regsDCN20(0),
647 dsc_regsDCN20(1),
648 dsc_regsDCN20(2)
649 };
650
651 static const struct dcn20_dsc_shift dsc_shift = {
652 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
653 };
654
655 static const struct dcn20_dsc_mask dsc_mask = {
656 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
657 };
658
659 static const struct dcn30_mpc_registers mpc_regs = {
660 MPC_REG_LIST_DCN3_0(0),
661 MPC_REG_LIST_DCN3_0(1),
662 MPC_REG_LIST_DCN3_0(2),
663 MPC_REG_LIST_DCN3_0(3),
664 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
665 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
666 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
667 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
668 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
669 MPC_RMU_REG_LIST_DCN3AG(0),
670 MPC_RMU_REG_LIST_DCN3AG(1),
671 //MPC_RMU_REG_LIST_DCN3AG(2),
672 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
673 };
674
675 static const struct dcn30_mpc_shift mpc_shift = {
676 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
677 };
678
679 static const struct dcn30_mpc_mask mpc_mask = {
680 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
681 };
682
683 #define optc_regs(id)\
684 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
685
686 static const struct dcn_optc_registers optc_regs[] = {
687 optc_regs(0),
688 optc_regs(1),
689 optc_regs(2),
690 optc_regs(3)
691 };
692
693 static const struct dcn_optc_shift optc_shift = {
694 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
695 };
696
697 static const struct dcn_optc_mask optc_mask = {
698 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
699 };
700
701 #define hubp_regs(id)\
702 [id] = {\
703 HUBP_REG_LIST_DCN30(id)\
704 }
705
706 static const struct dcn_hubp2_registers hubp_regs[] = {
707 hubp_regs(0),
708 hubp_regs(1),
709 hubp_regs(2),
710 hubp_regs(3)
711 };
712
713
714 static const struct dcn_hubp2_shift hubp_shift = {
715 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
716 };
717
718 static const struct dcn_hubp2_mask hubp_mask = {
719 HUBP_MASK_SH_LIST_DCN31(_MASK)
720 };
721 static const struct dcn_hubbub_registers hubbub_reg = {
722 HUBBUB_REG_LIST_DCN31(0)
723 };
724
725 static const struct dcn_hubbub_shift hubbub_shift = {
726 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
727 };
728
729 static const struct dcn_hubbub_mask hubbub_mask = {
730 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
731 };
732
733 static const struct dccg_registers dccg_regs = {
734 DCCG_REG_LIST_DCN31()
735 };
736
737 static const struct dccg_shift dccg_shift = {
738 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
739 };
740
741 static const struct dccg_mask dccg_mask = {
742 DCCG_MASK_SH_LIST_DCN31(_MASK)
743 };
744
745
746 #define SRII2(reg_name_pre, reg_name_post, id)\
747 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
748 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
749 reg ## reg_name_pre ## id ## _ ## reg_name_post
750
751
752 #define HWSEQ_DCN31_REG_LIST()\
753 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
754 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
755 SR(DIO_MEM_PWR_CTRL), \
756 SR(ODM_MEM_PWR_CTRL3), \
757 SR(DMU_MEM_PWR_CNTL), \
758 SR(MMHUBBUB_MEM_PWR_CNTL), \
759 SR(DCCG_GATE_DISABLE_CNTL), \
760 SR(DCCG_GATE_DISABLE_CNTL2), \
761 SR(DCFCLK_CNTL),\
762 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
763 SRII(PIXEL_RATE_CNTL, OTG, 0), \
764 SRII(PIXEL_RATE_CNTL, OTG, 1),\
765 SRII(PIXEL_RATE_CNTL, OTG, 2),\
766 SRII(PIXEL_RATE_CNTL, OTG, 3),\
767 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
768 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
769 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
770 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
771 SR(MICROSECOND_TIME_BASE_DIV), \
772 SR(MILLISECOND_TIME_BASE_DIV), \
773 SR(DISPCLK_FREQ_CHANGE_CNTL), \
774 SR(RBBMIF_TIMEOUT_DIS), \
775 SR(RBBMIF_TIMEOUT_DIS_2), \
776 SR(DCHUBBUB_CRC_CTRL), \
777 SR(DPP_TOP0_DPP_CRC_CTRL), \
778 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
779 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
780 SR(MPC_CRC_CTRL), \
781 SR(MPC_CRC_RESULT_GB), \
782 SR(MPC_CRC_RESULT_C), \
783 SR(MPC_CRC_RESULT_AR), \
784 SR(DOMAIN0_PG_CONFIG), \
785 SR(DOMAIN1_PG_CONFIG), \
786 SR(DOMAIN2_PG_CONFIG), \
787 SR(DOMAIN3_PG_CONFIG), \
788 SR(DOMAIN16_PG_CONFIG), \
789 SR(DOMAIN17_PG_CONFIG), \
790 SR(DOMAIN18_PG_CONFIG), \
791 SR(DOMAIN0_PG_STATUS), \
792 SR(DOMAIN1_PG_STATUS), \
793 SR(DOMAIN2_PG_STATUS), \
794 SR(DOMAIN3_PG_STATUS), \
795 SR(DOMAIN16_PG_STATUS), \
796 SR(DOMAIN17_PG_STATUS), \
797 SR(DOMAIN18_PG_STATUS), \
798 SR(D1VGA_CONTROL), \
799 SR(D2VGA_CONTROL), \
800 SR(D3VGA_CONTROL), \
801 SR(D4VGA_CONTROL), \
802 SR(D5VGA_CONTROL), \
803 SR(D6VGA_CONTROL), \
804 SR(DC_IP_REQUEST_CNTL), \
805 SR(AZALIA_AUDIO_DTO), \
806 SR(AZALIA_CONTROLLER_CLOCK_GATING)
807
808 static const struct dce_hwseq_registers hwseq_reg = {
809 HWSEQ_DCN31_REG_LIST()
810 };
811
812 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
813 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
814 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
815 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
816 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
817 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
818 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
819 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
820 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
821 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
822 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
823 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
824 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
825 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
826 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
827 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
828 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
829 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
830 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
831 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
832 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
833 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
834 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
835 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
836 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
837 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
838 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
839 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
840 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
841 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
842 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
843 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
844
845 static const struct dce_hwseq_shift hwseq_shift = {
846 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
847 };
848
849 static const struct dce_hwseq_mask hwseq_mask = {
850 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
851 };
852 #define vmid_regs(id)\
853 [id] = {\
854 DCN20_VMID_REG_LIST(id)\
855 }
856
857 static const struct dcn_vmid_registers vmid_regs[] = {
858 vmid_regs(0),
859 vmid_regs(1),
860 vmid_regs(2),
861 vmid_regs(3),
862 vmid_regs(4),
863 vmid_regs(5),
864 vmid_regs(6),
865 vmid_regs(7),
866 vmid_regs(8),
867 vmid_regs(9),
868 vmid_regs(10),
869 vmid_regs(11),
870 vmid_regs(12),
871 vmid_regs(13),
872 vmid_regs(14),
873 vmid_regs(15)
874 };
875
876 static const struct dcn20_vmid_shift vmid_shifts = {
877 DCN20_VMID_MASK_SH_LIST(__SHIFT)
878 };
879
880 static const struct dcn20_vmid_mask vmid_masks = {
881 DCN20_VMID_MASK_SH_LIST(_MASK)
882 };
883
884 static const struct resource_caps res_cap_dcn31 = {
885 .num_timing_generator = 4,
886 .num_opp = 4,
887 .num_video_plane = 4,
888 .num_audio = 5,
889 .num_stream_encoder = 5,
890 .num_dig_link_enc = 5,
891 .num_pll = 5,
892 .num_dwb = 1,
893 .num_ddc = 5,
894 .num_vmid = 16,
895 .num_mpc_3dlut = 2,
896 .num_dsc = 3,
897 };
898
899 static const struct dc_plane_cap plane_cap = {
900 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
901 .blends_with_above = true,
902 .blends_with_below = true,
903 .per_pixel_alpha = true,
904
905 .pixel_format_support = {
906 .argb8888 = true,
907 .nv12 = true,
908 .fp16 = true,
909 .p010 = false,
910 .ayuv = false,
911 },
912
913 .max_upscale_factor = {
914 .argb8888 = 16000,
915 .nv12 = 16000,
916 .fp16 = 16000
917 },
918
919 // 6:1 downscaling ratio: 1000/6 = 166.666
920 .max_downscale_factor = {
921 .argb8888 = 167,
922 .nv12 = 167,
923 .fp16 = 167
924 },
925 64,
926 64
927 };
928
929 static const struct dc_debug_options debug_defaults_drv = {
930 .disable_dmcu = true,
931 .force_abm_enable = false,
932 .timing_trace = false,
933 .clock_trace = true,
934 .disable_pplib_clock_request = false,
935 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
936 .force_single_disp_pipe_split = false,
937 .disable_dcc = DCC_ENABLE,
938 .vsr_support = true,
939 .performance_trace = false,
940 .max_downscale_src_width = 4096,/*upto true 4K*/
941 .disable_pplib_wm_range = false,
942 .scl_reset_length10 = true,
943 .sanity_checks = true,
944 .underflow_assert_delay_us = 0xFFFFFFFF,
945 .dwb_fi_phase = -1, // -1 = disable,
946 .dmub_command_table = true,
947 .pstate_enabled = true,
948 .use_max_lb = true,
949 .enable_mem_low_power = {
950 .bits = {
951 .vga = false,
952 .i2c = false,
953 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
954 .dscl = false,
955 .cm = false,
956 .mpc = false,
957 .optc = false,
958 }
959 },
960 .disable_z10 = true,
961 .optimize_edp_link_rate = true,
962 .enable_sw_cntl_psr = true,
963 };
964
965 static const struct dc_debug_options debug_defaults_diags = {
966 .disable_dmcu = true,
967 .force_abm_enable = false,
968 .timing_trace = true,
969 .clock_trace = true,
970 .disable_dpp_power_gate = true,
971 .disable_hubp_power_gate = true,
972 .disable_clock_gate = true,
973 .disable_pplib_clock_request = true,
974 .disable_pplib_wm_range = true,
975 .disable_stutter = false,
976 .scl_reset_length10 = true,
977 .dwb_fi_phase = -1, // -1 = disable
978 .dmub_command_table = true,
979 .enable_tri_buf = true,
980 .use_max_lb = true
981 };
982
dcn31_dpp_destroy(struct dpp ** dpp)983 static void dcn31_dpp_destroy(struct dpp **dpp)
984 {
985 kfree(TO_DCN20_DPP(*dpp));
986 *dpp = NULL;
987 }
988
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)989 static struct dpp *dcn31_dpp_create(
990 struct dc_context *ctx,
991 uint32_t inst)
992 {
993 struct dcn3_dpp *dpp =
994 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
995
996 if (!dpp)
997 return NULL;
998
999 if (dpp3_construct(dpp, ctx, inst,
1000 &dpp_regs[inst], &tf_shift, &tf_mask))
1001 return &dpp->base;
1002
1003 BREAK_TO_DEBUGGER();
1004 kfree(dpp);
1005 return NULL;
1006 }
1007
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)1008 static struct output_pixel_processor *dcn31_opp_create(
1009 struct dc_context *ctx, uint32_t inst)
1010 {
1011 struct dcn20_opp *opp =
1012 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1013
1014 if (!opp) {
1015 BREAK_TO_DEBUGGER();
1016 return NULL;
1017 }
1018
1019 dcn20_opp_construct(opp, ctx, inst,
1020 &opp_regs[inst], &opp_shift, &opp_mask);
1021 return &opp->base;
1022 }
1023
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)1024 static struct dce_aux *dcn31_aux_engine_create(
1025 struct dc_context *ctx,
1026 uint32_t inst)
1027 {
1028 struct aux_engine_dce110 *aux_engine =
1029 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1030
1031 if (!aux_engine)
1032 return NULL;
1033
1034 dce110_aux_engine_construct(aux_engine, ctx, inst,
1035 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1036 &aux_engine_regs[inst],
1037 &aux_mask,
1038 &aux_shift,
1039 ctx->dc->caps.extended_aux_timeout_support);
1040
1041 return &aux_engine->base;
1042 }
1043 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1044
1045 static const struct dce_i2c_registers i2c_hw_regs[] = {
1046 i2c_inst_regs(1),
1047 i2c_inst_regs(2),
1048 i2c_inst_regs(3),
1049 i2c_inst_regs(4),
1050 i2c_inst_regs(5),
1051 };
1052
1053 static const struct dce_i2c_shift i2c_shifts = {
1054 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1055 };
1056
1057 static const struct dce_i2c_mask i2c_masks = {
1058 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1059 };
1060
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)1061 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1062 struct dc_context *ctx,
1063 uint32_t inst)
1064 {
1065 struct dce_i2c_hw *dce_i2c_hw =
1066 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1067
1068 if (!dce_i2c_hw)
1069 return NULL;
1070
1071 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1072 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1073
1074 return dce_i2c_hw;
1075 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1076 static struct mpc *dcn31_mpc_create(
1077 struct dc_context *ctx,
1078 int num_mpcc,
1079 int num_rmu)
1080 {
1081 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1082 GFP_KERNEL);
1083
1084 if (!mpc30)
1085 return NULL;
1086
1087 dcn30_mpc_construct(mpc30, ctx,
1088 &mpc_regs,
1089 &mpc_shift,
1090 &mpc_mask,
1091 num_mpcc,
1092 num_rmu);
1093
1094 return &mpc30->base;
1095 }
1096
dcn31_hubbub_create(struct dc_context * ctx)1097 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1098 {
1099 int i;
1100
1101 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1102 GFP_KERNEL);
1103
1104 if (!hubbub3)
1105 return NULL;
1106
1107 hubbub31_construct(hubbub3, ctx,
1108 &hubbub_reg,
1109 &hubbub_shift,
1110 &hubbub_mask,
1111 dcn3_1_ip.det_buffer_size_kbytes,
1112 dcn3_1_ip.pixel_chunk_size_kbytes,
1113 dcn3_1_ip.config_return_buffer_size_in_kbytes);
1114
1115
1116 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1117 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1118
1119 vmid->ctx = ctx;
1120
1121 vmid->regs = &vmid_regs[i];
1122 vmid->shifts = &vmid_shifts;
1123 vmid->masks = &vmid_masks;
1124 }
1125
1126 return &hubbub3->base;
1127 }
1128
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1129 static struct timing_generator *dcn31_timing_generator_create(
1130 struct dc_context *ctx,
1131 uint32_t instance)
1132 {
1133 struct optc *tgn10 =
1134 kzalloc(sizeof(struct optc), GFP_KERNEL);
1135
1136 if (!tgn10)
1137 return NULL;
1138
1139 tgn10->base.inst = instance;
1140 tgn10->base.ctx = ctx;
1141
1142 tgn10->tg_regs = &optc_regs[instance];
1143 tgn10->tg_shift = &optc_shift;
1144 tgn10->tg_mask = &optc_mask;
1145
1146 dcn31_timing_generator_init(tgn10);
1147
1148 return &tgn10->base;
1149 }
1150
1151 static const struct encoder_feature_support link_enc_feature = {
1152 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1153 .max_hdmi_pixel_clock = 600000,
1154 .hdmi_ycbcr420_supported = true,
1155 .dp_ycbcr420_supported = true,
1156 .fec_supported = true,
1157 .flags.bits.IS_HBR2_CAPABLE = true,
1158 .flags.bits.IS_HBR3_CAPABLE = true,
1159 .flags.bits.IS_TPS3_CAPABLE = true,
1160 .flags.bits.IS_TPS4_CAPABLE = true
1161 };
1162
dcn31_link_encoder_create(const struct encoder_init_data * enc_init_data)1163 static struct link_encoder *dcn31_link_encoder_create(
1164 const struct encoder_init_data *enc_init_data)
1165 {
1166 struct dcn20_link_encoder *enc20 =
1167 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1168
1169 if (!enc20)
1170 return NULL;
1171
1172 dcn31_link_encoder_construct(enc20,
1173 enc_init_data,
1174 &link_enc_feature,
1175 &link_enc_regs[enc_init_data->transmitter],
1176 &link_enc_aux_regs[enc_init_data->channel - 1],
1177 &link_enc_hpd_regs[enc_init_data->hpd_source],
1178 &le_shift,
1179 &le_mask);
1180
1181 return &enc20->enc10.base;
1182 }
1183
1184 /* Create a minimal link encoder object not associated with a particular
1185 * physical connector.
1186 * resource_funcs.link_enc_create_minimal
1187 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1188 static struct link_encoder *dcn31_link_enc_create_minimal(
1189 struct dc_context *ctx, enum engine_id eng_id)
1190 {
1191 struct dcn20_link_encoder *enc20;
1192
1193 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1194 return NULL;
1195
1196 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1197 if (!enc20)
1198 return NULL;
1199
1200 dcn31_link_encoder_construct_minimal(
1201 enc20,
1202 ctx,
1203 &link_enc_feature,
1204 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1205 eng_id);
1206
1207 return &enc20->enc10.base;
1208 }
1209
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1210 struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1211 {
1212 struct dcn31_panel_cntl *panel_cntl =
1213 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1214
1215 if (!panel_cntl)
1216 return NULL;
1217
1218 dcn31_panel_cntl_construct(panel_cntl, init_data);
1219
1220 return &panel_cntl->base;
1221 }
1222
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1223 static void read_dce_straps(
1224 struct dc_context *ctx,
1225 struct resource_straps *straps)
1226 {
1227 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1228 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1229
1230 }
1231
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1232 static struct audio *dcn31_create_audio(
1233 struct dc_context *ctx, unsigned int inst)
1234 {
1235 return dce_audio_create(ctx, inst,
1236 &audio_regs[inst], &audio_shift, &audio_mask);
1237 }
1238
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1239 static struct vpg *dcn31_vpg_create(
1240 struct dc_context *ctx,
1241 uint32_t inst)
1242 {
1243 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1244
1245 if (!vpg3)
1246 return NULL;
1247
1248 vpg3_construct(vpg3, ctx, inst,
1249 &vpg_regs[inst],
1250 &vpg_shift,
1251 &vpg_mask);
1252
1253 return &vpg3->base;
1254 }
1255
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1256 static struct afmt *dcn31_afmt_create(
1257 struct dc_context *ctx,
1258 uint32_t inst)
1259 {
1260 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1261
1262 if (!afmt3)
1263 return NULL;
1264
1265 afmt3_construct(afmt3, ctx, inst,
1266 &afmt_regs[inst],
1267 &afmt_shift,
1268 &afmt_mask);
1269
1270 return &afmt3->base;
1271 }
1272
dcn31_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1273 static struct stream_encoder *dcn31_stream_encoder_create(
1274 enum engine_id eng_id,
1275 struct dc_context *ctx)
1276 {
1277 struct dcn10_stream_encoder *enc1;
1278 struct vpg *vpg;
1279 struct afmt *afmt;
1280 int vpg_inst;
1281 int afmt_inst;
1282
1283 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1284 if (eng_id <= ENGINE_ID_DIGF) {
1285 vpg_inst = eng_id;
1286 afmt_inst = eng_id;
1287 } else
1288 return NULL;
1289
1290 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1291 vpg = dcn31_vpg_create(ctx, vpg_inst);
1292 afmt = dcn31_afmt_create(ctx, afmt_inst);
1293
1294 if (!enc1 || !vpg || !afmt) {
1295 kfree(enc1);
1296 kfree(vpg);
1297 kfree(afmt);
1298 return NULL;
1299 }
1300
1301 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1302 eng_id, vpg, afmt,
1303 &stream_enc_regs[eng_id],
1304 &se_shift, &se_mask);
1305
1306 return &enc1->base;
1307 }
1308
dcn31_hwseq_create(struct dc_context * ctx)1309 static struct dce_hwseq *dcn31_hwseq_create(
1310 struct dc_context *ctx)
1311 {
1312 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1313
1314 if (hws) {
1315 hws->ctx = ctx;
1316 hws->regs = &hwseq_reg;
1317 hws->shifts = &hwseq_shift;
1318 hws->masks = &hwseq_mask;
1319 }
1320 return hws;
1321 }
1322 static const struct resource_create_funcs res_create_funcs = {
1323 .read_dce_straps = read_dce_straps,
1324 .create_audio = dcn31_create_audio,
1325 .create_stream_encoder = dcn31_stream_encoder_create,
1326 .create_hwseq = dcn31_hwseq_create,
1327 };
1328
1329 static const struct resource_create_funcs res_create_maximus_funcs = {
1330 .read_dce_straps = NULL,
1331 .create_audio = NULL,
1332 .create_stream_encoder = NULL,
1333 .create_hwseq = dcn31_hwseq_create,
1334 };
1335
dcn31_resource_destruct(struct dcn31_resource_pool * pool)1336 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1337 {
1338 unsigned int i;
1339
1340 for (i = 0; i < pool->base.stream_enc_count; i++) {
1341 if (pool->base.stream_enc[i] != NULL) {
1342 if (pool->base.stream_enc[i]->vpg != NULL) {
1343 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1344 pool->base.stream_enc[i]->vpg = NULL;
1345 }
1346 if (pool->base.stream_enc[i]->afmt != NULL) {
1347 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1348 pool->base.stream_enc[i]->afmt = NULL;
1349 }
1350 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1351 pool->base.stream_enc[i] = NULL;
1352 }
1353 }
1354
1355 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1356 if (pool->base.dscs[i] != NULL)
1357 dcn20_dsc_destroy(&pool->base.dscs[i]);
1358 }
1359
1360 if (pool->base.mpc != NULL) {
1361 kfree(TO_DCN20_MPC(pool->base.mpc));
1362 pool->base.mpc = NULL;
1363 }
1364 if (pool->base.hubbub != NULL) {
1365 kfree(pool->base.hubbub);
1366 pool->base.hubbub = NULL;
1367 }
1368 for (i = 0; i < pool->base.pipe_count; i++) {
1369 if (pool->base.dpps[i] != NULL)
1370 dcn31_dpp_destroy(&pool->base.dpps[i]);
1371
1372 if (pool->base.ipps[i] != NULL)
1373 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1374
1375 if (pool->base.hubps[i] != NULL) {
1376 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1377 pool->base.hubps[i] = NULL;
1378 }
1379
1380 if (pool->base.irqs != NULL) {
1381 dal_irq_service_destroy(&pool->base.irqs);
1382 }
1383 }
1384
1385 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1386 if (pool->base.engines[i] != NULL)
1387 dce110_engine_destroy(&pool->base.engines[i]);
1388 if (pool->base.hw_i2cs[i] != NULL) {
1389 kfree(pool->base.hw_i2cs[i]);
1390 pool->base.hw_i2cs[i] = NULL;
1391 }
1392 if (pool->base.sw_i2cs[i] != NULL) {
1393 kfree(pool->base.sw_i2cs[i]);
1394 pool->base.sw_i2cs[i] = NULL;
1395 }
1396 }
1397
1398 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1399 if (pool->base.opps[i] != NULL)
1400 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1401 }
1402
1403 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1404 if (pool->base.timing_generators[i] != NULL) {
1405 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1406 pool->base.timing_generators[i] = NULL;
1407 }
1408 }
1409
1410 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1411 if (pool->base.dwbc[i] != NULL) {
1412 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1413 pool->base.dwbc[i] = NULL;
1414 }
1415 if (pool->base.mcif_wb[i] != NULL) {
1416 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1417 pool->base.mcif_wb[i] = NULL;
1418 }
1419 }
1420
1421 for (i = 0; i < pool->base.audio_count; i++) {
1422 if (pool->base.audios[i])
1423 dce_aud_destroy(&pool->base.audios[i]);
1424 }
1425
1426 for (i = 0; i < pool->base.clk_src_count; i++) {
1427 if (pool->base.clock_sources[i] != NULL) {
1428 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1429 pool->base.clock_sources[i] = NULL;
1430 }
1431 }
1432
1433 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1434 if (pool->base.mpc_lut[i] != NULL) {
1435 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1436 pool->base.mpc_lut[i] = NULL;
1437 }
1438 if (pool->base.mpc_shaper[i] != NULL) {
1439 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1440 pool->base.mpc_shaper[i] = NULL;
1441 }
1442 }
1443
1444 if (pool->base.dp_clock_source != NULL) {
1445 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1446 pool->base.dp_clock_source = NULL;
1447 }
1448
1449 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1450 if (pool->base.multiple_abms[i] != NULL)
1451 dce_abm_destroy(&pool->base.multiple_abms[i]);
1452 }
1453
1454 if (pool->base.psr != NULL)
1455 dmub_psr_destroy(&pool->base.psr);
1456
1457 if (pool->base.dccg != NULL)
1458 dcn_dccg_destroy(&pool->base.dccg);
1459 }
1460
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1461 static struct hubp *dcn31_hubp_create(
1462 struct dc_context *ctx,
1463 uint32_t inst)
1464 {
1465 struct dcn20_hubp *hubp2 =
1466 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1467
1468 if (!hubp2)
1469 return NULL;
1470
1471 if (hubp31_construct(hubp2, ctx, inst,
1472 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1473 return &hubp2->base;
1474
1475 BREAK_TO_DEBUGGER();
1476 kfree(hubp2);
1477 return NULL;
1478 }
1479
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1480 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1481 {
1482 int i;
1483 uint32_t pipe_count = pool->res_cap->num_dwb;
1484
1485 for (i = 0; i < pipe_count; i++) {
1486 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1487 GFP_KERNEL);
1488
1489 if (!dwbc30) {
1490 dm_error("DC: failed to create dwbc30!\n");
1491 return false;
1492 }
1493
1494 dcn30_dwbc_construct(dwbc30, ctx,
1495 &dwbc30_regs[i],
1496 &dwbc30_shift,
1497 &dwbc30_mask,
1498 i);
1499
1500 pool->dwbc[i] = &dwbc30->base;
1501 }
1502 return true;
1503 }
1504
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1505 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1506 {
1507 int i;
1508 uint32_t pipe_count = pool->res_cap->num_dwb;
1509
1510 for (i = 0; i < pipe_count; i++) {
1511 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1512 GFP_KERNEL);
1513
1514 if (!mcif_wb30) {
1515 dm_error("DC: failed to create mcif_wb30!\n");
1516 return false;
1517 }
1518
1519 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1520 &mcif_wb30_regs[i],
1521 &mcif_wb30_shift,
1522 &mcif_wb30_mask,
1523 i);
1524
1525 pool->mcif_wb[i] = &mcif_wb30->base;
1526 }
1527 return true;
1528 }
1529
dcn31_dsc_create(struct dc_context * ctx,uint32_t inst)1530 static struct display_stream_compressor *dcn31_dsc_create(
1531 struct dc_context *ctx, uint32_t inst)
1532 {
1533 struct dcn20_dsc *dsc =
1534 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1535
1536 if (!dsc) {
1537 BREAK_TO_DEBUGGER();
1538 return NULL;
1539 }
1540
1541 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1542 return &dsc->base;
1543 }
1544
dcn31_destroy_resource_pool(struct resource_pool ** pool)1545 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1546 {
1547 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1548
1549 dcn31_resource_destruct(dcn31_pool);
1550 kfree(dcn31_pool);
1551 *pool = NULL;
1552 }
1553
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1554 static struct clock_source *dcn31_clock_source_create(
1555 struct dc_context *ctx,
1556 struct dc_bios *bios,
1557 enum clock_source_id id,
1558 const struct dce110_clk_src_regs *regs,
1559 bool dp_clk_src)
1560 {
1561 struct dce110_clk_src *clk_src =
1562 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1563
1564 if (!clk_src)
1565 return NULL;
1566
1567 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1568 regs, &cs_shift, &cs_mask)) {
1569 clk_src->base.dp_clk_src = dp_clk_src;
1570 return &clk_src->base;
1571 }
1572
1573 BREAK_TO_DEBUGGER();
1574 return NULL;
1575 }
1576
is_dual_plane(enum surface_pixel_format format)1577 static bool is_dual_plane(enum surface_pixel_format format)
1578 {
1579 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1580 }
1581
dcn31_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1582 static int dcn31_populate_dml_pipes_from_context(
1583 struct dc *dc, struct dc_state *context,
1584 display_e2e_pipe_params_st *pipes,
1585 bool fast_validate)
1586 {
1587 int i, pipe_cnt;
1588 struct resource_context *res_ctx = &context->res_ctx;
1589 struct pipe_ctx *pipe;
1590
1591 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1592
1593 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1594 struct dc_crtc_timing *timing;
1595
1596 if (!res_ctx->pipe_ctx[i].stream)
1597 continue;
1598 pipe = &res_ctx->pipe_ctx[i];
1599 timing = &pipe->stream->timing;
1600
1601 /*
1602 * Immediate flip can be set dynamically after enabling the plane.
1603 * We need to require support for immediate flip or underflow can be
1604 * intermittently experienced depending on peak b/w requirements.
1605 */
1606 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1607
1608 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1609 pipes[pipe_cnt].pipe.src.gpuvm = true;
1610 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
1611 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
1612 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1613 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1614 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1615
1616 if (pipes[pipe_cnt].dout.dsc_enable) {
1617 switch (timing->display_color_depth) {
1618 case COLOR_DEPTH_888:
1619 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1620 break;
1621 case COLOR_DEPTH_101010:
1622 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1623 break;
1624 case COLOR_DEPTH_121212:
1625 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1626 break;
1627 default:
1628 ASSERT(0);
1629 break;
1630 }
1631 }
1632
1633 pipe_cnt++;
1634 }
1635 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1636 dc->config.enable_4to1MPC = false;
1637 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1638 if (is_dual_plane(pipe->plane_state->format)
1639 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1640 dc->config.enable_4to1MPC = true;
1641 } else if (!is_dual_plane(pipe->plane_state->format)) {
1642 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1643 pipes[0].pipe.src.unbounded_req_mode = true;
1644 }
1645 }
1646
1647 return pipe_cnt;
1648 }
1649
dcn31_update_soc_for_wm_a(struct dc * dc,struct dc_state * context)1650 static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
1651 {
1652 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
1653 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
1654 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
1655 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
1656 }
1657 }
1658
dcn31_calculate_wm_and_dlg_fp(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1659 static void dcn31_calculate_wm_and_dlg_fp(
1660 struct dc *dc, struct dc_state *context,
1661 display_e2e_pipe_params_st *pipes,
1662 int pipe_cnt,
1663 int vlevel)
1664 {
1665 int i, pipe_idx;
1666 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1667
1668 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
1669 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
1670
1671 /* We don't recalculate clocks for 0 pipe configs, which can block
1672 * S0i3 as high clocks will block low power states
1673 * Override any clocks that can block S0i3 to min here
1674 */
1675 if (pipe_cnt == 0) {
1676 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0
1677 return;
1678 }
1679
1680 pipes[0].clks_cfg.voltage = vlevel;
1681 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1682 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1683
1684 #if 0 // TODO
1685 /* Set B:
1686 * TODO
1687 */
1688 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
1689 if (vlevel == 0) {
1690 pipes[0].clks_cfg.voltage = 1;
1691 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
1692 }
1693 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
1694 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
1695 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
1696 }
1697 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1698 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1699 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1700 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1701 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1702 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1703 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1704 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1705 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1706 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1707
1708 pipes[0].clks_cfg.voltage = vlevel;
1709 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1710
1711 /* Set C:
1712 * TODO
1713 */
1714 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
1715 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
1716 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
1717 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
1718 }
1719 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1720 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1721 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1722 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1723 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1724 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1725 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1726 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1727 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1728 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1729
1730 /* Set D:
1731 * TODO
1732 */
1733 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
1734 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
1735 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
1736 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
1737 }
1738 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1739 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1740 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1741 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1742 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1743 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1744 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1745 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1746 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1747 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1748 #endif
1749
1750 /* Set A:
1751 * All clocks min required
1752 *
1753 * Set A calculated last so that following calculations are based on Set A
1754 */
1755 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1756 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1757 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1758 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1759 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1760 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1761 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1762 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1763 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1764 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1765 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1766 /* TODO: remove: */
1767 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1768 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1769 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1770 /* end remove*/
1771
1772 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1773 if (!context->res_ctx.pipe_ctx[i].stream)
1774 continue;
1775
1776 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1777 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1778
1779 if (dc->config.forced_clocks) {
1780 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1781 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1782 }
1783 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1784 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1785 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1786 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1787
1788 pipe_idx++;
1789 }
1790
1791 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1792 }
1793
dcn31_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1794 static void dcn31_calculate_wm_and_dlg(
1795 struct dc *dc, struct dc_state *context,
1796 display_e2e_pipe_params_st *pipes,
1797 int pipe_cnt,
1798 int vlevel)
1799 {
1800 DC_FP_START();
1801 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1802 DC_FP_END();
1803 }
1804
dcn31_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1805 bool dcn31_validate_bandwidth(struct dc *dc,
1806 struct dc_state *context,
1807 bool fast_validate)
1808 {
1809 bool out = false;
1810
1811 BW_VAL_TRACE_SETUP();
1812
1813 int vlevel = 0;
1814 int pipe_cnt = 0;
1815 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1816 DC_LOGGER_INIT(dc->ctx->logger);
1817
1818 BW_VAL_TRACE_COUNT();
1819
1820 DC_FP_START();
1821 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1822 DC_FP_END();
1823
1824 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
1825 if (pipe_cnt == 0)
1826 fast_validate = false;
1827
1828 if (!out)
1829 goto validate_fail;
1830
1831 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1832
1833 if (fast_validate) {
1834 BW_VAL_TRACE_SKIP(fast);
1835 goto validate_out;
1836 }
1837
1838 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1839
1840 BW_VAL_TRACE_END_WATERMARKS();
1841
1842 goto validate_out;
1843
1844 validate_fail:
1845 DC_LOG_WARNING("Mode Validation Warning: %s failed alidation.\n",
1846 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1847
1848 BW_VAL_TRACE_SKIP(fail);
1849 out = false;
1850
1851 validate_out:
1852 kfree(pipes);
1853
1854 BW_VAL_TRACE_FINISH();
1855
1856 return out;
1857 }
1858
1859 static struct dc_cap_funcs cap_funcs = {
1860 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1861 };
1862
dcn31_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1863 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1864 {
1865 struct clk_limit_table *clk_table = &bw_params->clk_table;
1866 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1867 unsigned int i, closest_clk_lvl;
1868 int j;
1869
1870 // Default clock levels are used for diags, which may lead to overclocking.
1871 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
1872 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
1873
1874 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
1875 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
1876 dcn3_1_soc.num_chans = bw_params->num_channels;
1877
1878 ASSERT(clk_table->num_entries);
1879
1880 /* Prepass to find max clocks independent of voltage level. */
1881 for (i = 0; i < clk_table->num_entries; ++i) {
1882 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
1883 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
1884 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
1885 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
1886 }
1887
1888 for (i = 0; i < clk_table->num_entries; i++) {
1889 /* loop backwards*/
1890 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
1891 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1892 closest_clk_lvl = j;
1893 break;
1894 }
1895 }
1896
1897 clock_limits[i].state = i;
1898
1899 /* Clocks dependent on voltage level. */
1900 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1901 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1902 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1903 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
1904
1905 /* Clocks independent of voltage level. */
1906 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
1907 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1908
1909 clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
1910 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1911
1912 clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1913 clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1914 clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1915 clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1916 clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1917 }
1918 for (i = 0; i < clk_table->num_entries; i++)
1919 dcn3_1_soc.clock_limits[i] = clock_limits[i];
1920 if (clk_table->num_entries) {
1921 dcn3_1_soc.num_states = clk_table->num_entries;
1922 }
1923 }
1924
1925 dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1926 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1927
1928 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1929 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
1930 else
1931 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
1932 }
1933
1934 static struct resource_funcs dcn31_res_pool_funcs = {
1935 .destroy = dcn31_destroy_resource_pool,
1936 .link_enc_create = dcn31_link_encoder_create,
1937 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1938 .link_encs_assign = link_enc_cfg_link_encs_assign,
1939 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1940 .panel_cntl_create = dcn31_panel_cntl_create,
1941 .validate_bandwidth = dcn31_validate_bandwidth,
1942 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1943 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1944 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
1945 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1946 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1947 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1948 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1949 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1950 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1951 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1952 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1953 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1954 .update_bw_bounding_box = dcn31_update_bw_bounding_box,
1955 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1956 };
1957
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1958 static struct clock_source *dcn30_clock_source_create(
1959 struct dc_context *ctx,
1960 struct dc_bios *bios,
1961 enum clock_source_id id,
1962 const struct dce110_clk_src_regs *regs,
1963 bool dp_clk_src)
1964 {
1965 struct dce110_clk_src *clk_src =
1966 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1967
1968 if (!clk_src)
1969 return NULL;
1970
1971 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1972 regs, &cs_shift, &cs_mask)) {
1973 clk_src->base.dp_clk_src = dp_clk_src;
1974 return &clk_src->base;
1975 }
1976
1977 BREAK_TO_DEBUGGER();
1978 return NULL;
1979 }
1980
dcn31_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn31_resource_pool * pool)1981 static bool dcn31_resource_construct(
1982 uint8_t num_virtual_links,
1983 struct dc *dc,
1984 struct dcn31_resource_pool *pool)
1985 {
1986 int i;
1987 struct dc_context *ctx = dc->ctx;
1988 struct irq_service_init_data init_data;
1989
1990 DC_FP_START();
1991
1992 ctx->dc_bios->regs = &bios_regs;
1993
1994 pool->base.res_cap = &res_cap_dcn31;
1995
1996 pool->base.funcs = &dcn31_res_pool_funcs;
1997
1998 /*************************************************
1999 * Resource + asic cap harcoding *
2000 *************************************************/
2001 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2002 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2003 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2004 dc->caps.max_downscale_ratio = 600;
2005 dc->caps.i2c_speed_in_khz = 100;
2006 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
2007 dc->caps.max_cursor_size = 256;
2008 dc->caps.min_horizontal_blanking_period = 80;
2009 dc->caps.dmdata_alloc_size = 2048;
2010
2011 dc->caps.max_slave_planes = 1;
2012 dc->caps.max_slave_yuv_planes = 1;
2013 dc->caps.max_slave_rgb_planes = 1;
2014 dc->caps.post_blend_color_processing = true;
2015 dc->caps.force_dp_tps4_for_cp2520 = true;
2016 dc->caps.extended_aux_timeout_support = true;
2017 dc->caps.dmcub_support = true;
2018 dc->caps.is_apu = true;
2019
2020 /* Color pipeline capabilities */
2021 dc->caps.color.dpp.dcn_arch = 1;
2022 dc->caps.color.dpp.input_lut_shared = 0;
2023 dc->caps.color.dpp.icsc = 1;
2024 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2025 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2026 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2027 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2028 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2029 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2030 dc->caps.color.dpp.post_csc = 1;
2031 dc->caps.color.dpp.gamma_corr = 1;
2032 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2033
2034 dc->caps.color.dpp.hw_3d_lut = 1;
2035 dc->caps.color.dpp.ogam_ram = 1;
2036 // no OGAM ROM on DCN301
2037 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2038 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2039 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2040 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2041 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2042 dc->caps.color.dpp.ocsc = 0;
2043
2044 dc->caps.color.mpc.gamut_remap = 1;
2045 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
2046 dc->caps.color.mpc.ogam_ram = 1;
2047 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2048 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2049 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2050 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2051 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2052 dc->caps.color.mpc.ocsc = 1;
2053
2054 /* read VBIOS LTTPR caps */
2055 {
2056 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2057 enum bp_result bp_query_result;
2058 uint8_t is_vbios_lttpr_enable = 0;
2059
2060 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2061 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2062 }
2063
2064 /* interop bit is implicit */
2065 {
2066 dc->caps.vbios_lttpr_aware = true;
2067 }
2068 }
2069
2070 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2071 dc->debug = debug_defaults_drv;
2072 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2073 dc->debug = debug_defaults_diags;
2074 } else
2075 dc->debug = debug_defaults_diags;
2076 // Init the vm_helper
2077 if (dc->vm_helper)
2078 vm_helper_init(dc->vm_helper, 16);
2079
2080 /*************************************************
2081 * Create resources *
2082 *************************************************/
2083
2084 /* Clock Sources for Pixel Clock*/
2085 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2086 dcn30_clock_source_create(ctx, ctx->dc_bios,
2087 CLOCK_SOURCE_COMBO_PHY_PLL0,
2088 &clk_src_regs[0], false);
2089 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2090 dcn30_clock_source_create(ctx, ctx->dc_bios,
2091 CLOCK_SOURCE_COMBO_PHY_PLL1,
2092 &clk_src_regs[1], false);
2093 /*move phypllx_pixclk_resync to dmub next*/
2094 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
2095 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2096 dcn30_clock_source_create(ctx, ctx->dc_bios,
2097 CLOCK_SOURCE_COMBO_PHY_PLL2,
2098 &clk_src_regs_b0[2], false);
2099 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2100 dcn30_clock_source_create(ctx, ctx->dc_bios,
2101 CLOCK_SOURCE_COMBO_PHY_PLL3,
2102 &clk_src_regs_b0[3], false);
2103 } else {
2104 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2105 dcn30_clock_source_create(ctx, ctx->dc_bios,
2106 CLOCK_SOURCE_COMBO_PHY_PLL2,
2107 &clk_src_regs[2], false);
2108 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2109 dcn30_clock_source_create(ctx, ctx->dc_bios,
2110 CLOCK_SOURCE_COMBO_PHY_PLL3,
2111 &clk_src_regs[3], false);
2112 }
2113
2114 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2115 dcn30_clock_source_create(ctx, ctx->dc_bios,
2116 CLOCK_SOURCE_COMBO_PHY_PLL4,
2117 &clk_src_regs[4], false);
2118
2119 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2120
2121 /* todo: not reuse phy_pll registers */
2122 pool->base.dp_clock_source =
2123 dcn31_clock_source_create(ctx, ctx->dc_bios,
2124 CLOCK_SOURCE_ID_DP_DTO,
2125 &clk_src_regs[0], true);
2126
2127 for (i = 0; i < pool->base.clk_src_count; i++) {
2128 if (pool->base.clock_sources[i] == NULL) {
2129 dm_error("DC: failed to create clock sources!\n");
2130 BREAK_TO_DEBUGGER();
2131 goto create_fail;
2132 }
2133 }
2134
2135 /* TODO: DCCG */
2136 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2137 if (pool->base.dccg == NULL) {
2138 dm_error("DC: failed to create dccg!\n");
2139 BREAK_TO_DEBUGGER();
2140 goto create_fail;
2141 }
2142
2143 /* TODO: IRQ */
2144 init_data.ctx = dc->ctx;
2145 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2146 if (!pool->base.irqs)
2147 goto create_fail;
2148
2149 /* HUBBUB */
2150 pool->base.hubbub = dcn31_hubbub_create(ctx);
2151 if (pool->base.hubbub == NULL) {
2152 BREAK_TO_DEBUGGER();
2153 dm_error("DC: failed to create hubbub!\n");
2154 goto create_fail;
2155 }
2156
2157 /* HUBPs, DPPs, OPPs and TGs */
2158 for (i = 0; i < pool->base.pipe_count; i++) {
2159 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2160 if (pool->base.hubps[i] == NULL) {
2161 BREAK_TO_DEBUGGER();
2162 dm_error(
2163 "DC: failed to create hubps!\n");
2164 goto create_fail;
2165 }
2166
2167 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2168 if (pool->base.dpps[i] == NULL) {
2169 BREAK_TO_DEBUGGER();
2170 dm_error(
2171 "DC: failed to create dpps!\n");
2172 goto create_fail;
2173 }
2174 }
2175
2176 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2177 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2178 if (pool->base.opps[i] == NULL) {
2179 BREAK_TO_DEBUGGER();
2180 dm_error(
2181 "DC: failed to create output pixel processor!\n");
2182 goto create_fail;
2183 }
2184 }
2185
2186 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2187 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2188 ctx, i);
2189 if (pool->base.timing_generators[i] == NULL) {
2190 BREAK_TO_DEBUGGER();
2191 dm_error("DC: failed to create tg!\n");
2192 goto create_fail;
2193 }
2194 }
2195 pool->base.timing_generator_count = i;
2196
2197 /* PSR */
2198 pool->base.psr = dmub_psr_create(ctx);
2199 if (pool->base.psr == NULL) {
2200 dm_error("DC: failed to create psr obj!\n");
2201 BREAK_TO_DEBUGGER();
2202 goto create_fail;
2203 }
2204
2205 /* ABM */
2206 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2207 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2208 &abm_regs[i],
2209 &abm_shift,
2210 &abm_mask);
2211 if (pool->base.multiple_abms[i] == NULL) {
2212 dm_error("DC: failed to create abm for pipe %d!\n", i);
2213 BREAK_TO_DEBUGGER();
2214 goto create_fail;
2215 }
2216 }
2217
2218 /* MPC and DSC */
2219 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2220 if (pool->base.mpc == NULL) {
2221 BREAK_TO_DEBUGGER();
2222 dm_error("DC: failed to create mpc!\n");
2223 goto create_fail;
2224 }
2225
2226 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2227 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2228 if (pool->base.dscs[i] == NULL) {
2229 BREAK_TO_DEBUGGER();
2230 dm_error("DC: failed to create display stream compressor %d!\n", i);
2231 goto create_fail;
2232 }
2233 }
2234
2235 /* DWB and MMHUBBUB */
2236 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2237 BREAK_TO_DEBUGGER();
2238 dm_error("DC: failed to create dwbc!\n");
2239 goto create_fail;
2240 }
2241
2242 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2243 BREAK_TO_DEBUGGER();
2244 dm_error("DC: failed to create mcif_wb!\n");
2245 goto create_fail;
2246 }
2247
2248 /* AUX and I2C */
2249 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2250 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2251 if (pool->base.engines[i] == NULL) {
2252 BREAK_TO_DEBUGGER();
2253 dm_error(
2254 "DC:failed to create aux engine!!\n");
2255 goto create_fail;
2256 }
2257 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2258 if (pool->base.hw_i2cs[i] == NULL) {
2259 BREAK_TO_DEBUGGER();
2260 dm_error(
2261 "DC:failed to create hw i2c!!\n");
2262 goto create_fail;
2263 }
2264 pool->base.sw_i2cs[i] = NULL;
2265 }
2266
2267 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2268 if (!resource_construct(num_virtual_links, dc, &pool->base,
2269 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2270 &res_create_funcs : &res_create_maximus_funcs)))
2271 goto create_fail;
2272
2273 /* HW Sequencer and Plane caps */
2274 dcn31_hw_sequencer_construct(dc);
2275
2276 dc->caps.max_planes = pool->base.pipe_count;
2277
2278 for (i = 0; i < dc->caps.max_planes; ++i)
2279 dc->caps.planes[i] = plane_cap;
2280
2281 dc->cap_funcs = cap_funcs;
2282
2283 DC_FP_END();
2284
2285 return true;
2286
2287 create_fail:
2288
2289 DC_FP_END();
2290 dcn31_resource_destruct(pool);
2291
2292 return false;
2293 }
2294
dcn31_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2295 struct resource_pool *dcn31_create_resource_pool(
2296 const struct dc_init_data *init_data,
2297 struct dc *dc)
2298 {
2299 struct dcn31_resource_pool *pool =
2300 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2301
2302 if (!pool)
2303 return NULL;
2304
2305 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2306 return &pool->base;
2307
2308 BREAK_TO_DEBUGGER();
2309 kfree(pool);
2310 return NULL;
2311 }
2312