Searched refs:DMU_MEM_PWR_CNTL (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_dmcu.h | 94 SR(DMU_MEM_PWR_CNTL)
174 DMCU_SF(DMU_MEM_PWR_CNTL, \
211 uint32_t DMU_MEM_PWR_CNTL; member
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| D | dce_dmcu.c | 347 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_get_dmcu_version()
497 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_dmcu_load_iram()
538 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_get_dmcu_psr_state()
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| D | dce_link_encoder.h | 155 uint32_t DMU_MEM_PWR_CNTL; member
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| D | dce_hwseq.h | 637 uint32_t DMU_MEM_PWR_CNTL; member
880 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 112 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); in dcn31_init_hw()
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| D | dcn31_resource.c | 757 SR(DMU_MEM_PWR_CNTL), \
840 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 481 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); in dcn30_init_hw()
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