Searched refs:GC_HWIP (Results 1 – 22 of 22) sorted by relevance
103 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)110 …uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \111 …uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \112 …uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SP…131 …5_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP)135 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)147 …uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \148 …uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \149 …uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_G…150 …uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_G…[all …]
35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in cyan_skillfish_reg_base_init()
35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in yellow_carp_reg_base_init()
35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vangogh_reg_base_init()
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in navi12_reg_base_init()
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in navi10_reg_base_init()
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in navi14_reg_base_init()
35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in beige_goby_reg_base_init()
35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in sienna_cichlid_reg_base_init()
35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
72 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_2_get_reg_offset()77 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_2_get_reg_offset()81 base = adev->reg_offset[GC_HWIP][0][2]; in sdma_v5_2_get_reg_offset()
112 [GC_HWIP] = GC_HWID,
505 tmp = (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()518 (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
176 base = adev->reg_offset[GC_HWIP][0][1]; in sdma_v5_0_get_reg_offset()180 base = adev->reg_offset[GC_HWIP][0][0]; in sdma_v5_0_get_reg_offset()
1489 case GC_HWIP: in gfx_v10_get_rlcg_flag()1532 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4; in gfx_v10_rlcg_rw()1534 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4; in gfx_v10_rlcg_rw()1536 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4; in gfx_v10_rlcg_rw()1538 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4; in gfx_v10_rlcg_rw()1542 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX] in gfx_v10_rlcg_rw()1546 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4; in gfx_v10_rlcg_rw()1549 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; in gfx_v10_rlcg_rw()1550 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; in gfx_v10_rlcg_rw()8211 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + in gfx_v10_0_apply_medium_grain_clock_gating_workaround()[all …]
752 …scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()753 …scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()754 …scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()755 …scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_RE… in gfx_v9_0_rlcg_w()756 …spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_IN… in gfx_v9_0_rlcg_w()758 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; in gfx_v9_0_rlcg_w()759 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; in gfx_v9_0_rlcg_w()
236 GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_vm_hub()
729 GC_HWIP = 1, enumerator