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Searched refs:MAX_PIPES (Results 1 – 25 of 33) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h210 struct mem_input *mis[MAX_PIPES];
211 struct hubp *hubps[MAX_PIPES];
212 struct input_pixel_processor *ipps[MAX_PIPES];
213 struct transform *transforms[MAX_PIPES];
214 struct dpp *dpps[MAX_PIPES];
215 struct output_pixel_processor *opps[MAX_PIPES];
216 struct timing_generator *timing_generators[MAX_PIPES];
217 struct stream_encoder *stream_enc[MAX_PIPES * 2];
221 struct dce_aux *engines[MAX_PIPES];
222 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dccg.h132 type OTG_ADD_PIXEL[MAX_PIPES];\
133 type OTG_DROP_PIXEL[MAX_PIPES];
166 type DTBCLK_DTO_ENABLE[MAX_PIPES];\
167 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
168 type PIPE_DTO_SRC_SEL[MAX_PIPES];\
169 type DTBCLK_DTO_DIV[MAX_PIPES];\
191 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
198 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
199 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
/drivers/gpu/drm/amd/display/dc/core/
Ddc_stream.c263 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_attributes()
363 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_position()
562 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_vblank_counter()
590 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_send_dp_sdp()
621 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_scanoutpos()
648 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_dmdata_status_done()
654 if (i == MAX_PIPES) in dc_stream_dmdata_status_done()
676 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dynamic_metadata()
682 if (i == MAX_PIPES) in dc_stream_set_dynamic_metadata()
Ddc.c314 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_adjust_vmin_vmax()
350 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_last_used_drr_vtotal()
380 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crtc_position()
418 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_dmcu_crc_window()
425 if (i == MAX_PIPES) in dc_stream_forward_dmcu_crc_window()
452 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_stop_dmcu_crc_win_update()
459 if (i == MAX_PIPES) in dc_stream_stop_dmcu_crc_win_update()
497 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_configure_crc()
503 if (i == MAX_PIPES) in dc_stream_configure_crc()
562 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crc()
[all …]
Ddc_debug.c312 int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0}; in context_timing_trace()
Ddc_link_hwss.c96 for (i = 0; i < MAX_PIPES; i++) { in dp_enable_link_phy()
333 for (i = 0; i < MAX_PIPES; i++) { in dp_retrain_link_dp_test()
Ddc_link.c2571 for (i = 0; i < MAX_PIPES; i++) { in get_abm_from_stream_res()
2618 for (i = 0; i < MAX_PIPES; i++) { in get_pipe_from_link()
2806 for (i = 0; i < MAX_PIPES; i++) { in dc_link_setup_psr()
3561 for (i = 0; i < MAX_PIPES; i++) { in dc_link_set_preferred_link_settings()
3572 if (i == MAX_PIPES) in dc_link_set_preferred_link_settings()
Ddc_resource.c573 for (i = 0; i < MAX_PIPES; i++) { in resource_find_used_clk_src_for_sharing()
1170 for (i = 0; i < MAX_PIPES; i++) { in resource_build_scaling_params_for_context()
1246 for (i = 0; i < MAX_PIPES; i++) { in resource_get_head_pipe_for_stream()
2577 for (i = 0; i < MAX_PIPES; i++) { in dc_resource_state_copy_construct()
Ddc_link_dp.c2991 for (i = 0; i < MAX_PIPES; i++) { in dp_test_send_link_test_pattern()
3234 for (i = 0; i < MAX_PIPES; i++) { in dc_link_dp_handle_link_loss()
3243 for (i = 0; i < MAX_PIPES; i++) { in dc_link_dp_handle_link_loss()
3251 for (i = 0; i < MAX_PIPES; i++) { in dc_link_dp_handle_link_loss()
4373 for (i = 0; i < MAX_PIPES; i++) { in dc_link_dp_set_test_pattern()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddccg.h61 int pipe_dppclk_khz[MAX_PIPES];
63 int dtbclk_khz[MAX_PIPES];
Dopp.h200 int dpp[MAX_PIPES];
201 int mpcc[MAX_PIPES];
209 bool mpcc_disconnect_pending[MAX_PIPES];
Dhw_shared.h38 #define MAX_PIPES 6 macro
Dclk_mgr_internal.h284 unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.h213 uint32_t PHASE[MAX_PIPES];
214 uint32_t MODULO[MAX_PIPES];
215 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
Ddmub_psr.c34 #define MAX_PIPES 6 macro
244 for (i = 0; i < MAX_PIPES; i++) { in dmub_psr_copy_settings()
Ddce_clk_mgr.c189 for (i = 0; i < MAX_PIPES; i++) { in get_max_pixel_clock_for_all_paths()
508 for (k = 0; k < MAX_PIPES; k++) in dce110_fill_display_configs()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_mst_types.c667 bool bpp_increased[MAX_PIPES]; in increase_dsc_bpp()
668 int initial_slack[MAX_PIPES]; in increase_dsc_bpp()
763 bool tried[MAX_PIPES]; in try_disable_dsc()
764 int kbps_increase[MAX_PIPES]; in try_disable_dsc()
830 struct dsc_mst_fairness_params params[MAX_PIPES]; in compute_mst_dsc_configs_for_link()
933 bool computed_streams[MAX_PIPES]; in compute_mst_dsc_configs_for_state()
Damdgpu_dm_debugfs.c1316 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_read()
1422 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_write()
1507 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_read()
1611 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_write()
1696 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_read()
1800 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_write()
1881 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_read()
1982 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_write()
2061 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_width_read()
2122 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_height_read()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c134 for (k = 0; k < MAX_PIPES; k++) in dce110_fill_display_configs()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c170 for (i = 0; i < MAX_PIPES; i++) { in dce_get_max_pixel_clock_for_all_paths()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c1192 int split[MAX_PIPES] = { 0 }; in dcn21_fast_validate_bw()
1256 for (i = 0; i < MAX_PIPES; i++) in dcn21_fast_validate_bw()
1341 int pipe_split_from[MAX_PIPES]; in dcn21_validate_bandwidth_fp()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c498 for (i = 0; i < MAX_PIPES * 2; i++) { in dcn2_notify_link_rate_change()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c1100 for (i = 0; i < MAX_PIPES; i++) { in dce110_enable_audio_stream()
1784 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { in dce110_set_displaymarks()
1825 for (i = 0; i < MAX_PIPES; i++) { in dce110_set_safe_displaymarks()
2019 for (i = 0; i < MAX_PIPES; i++) { in dce110_reset_hw_ctx_wrap()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c1093 TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES); in dcn10_verify_allow_pstate_change_high()
2020 struct dc_crtc_timing hw_crtc_timing[MAX_PIPES] = {0}; in dcn10_align_pixel_clocks()
2021 uint64_t phase[MAX_PIPES]; in dcn10_align_pixel_clocks()
2022 uint64_t modulo[MAX_PIPES]; in dcn10_align_pixel_clocks()
3141 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { in dcn10_wait_for_mpcc_disconnect()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c492 for (i = 0; i < MAX_PIPES * 2; i++) { in dcn30_notify_link_rate_change()

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