1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28
29 #include "dce100/dce_clk_mgr.h"
30 #include "dcn20_clk_mgr.h"
31 #include "reg_helper.h"
32 #include "core_types.h"
33 #include "dm_helpers.h"
34
35 #include "navi10_ip_offset.h"
36 #include "dcn/dcn_2_0_0_offset.h"
37 #include "dcn/dcn_2_0_0_sh_mask.h"
38 #include "clk/clk_11_0_0_offset.h"
39 #include "clk/clk_11_0_0_sh_mask.h"
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
44
45 #define REG(reg) \
46 (clk_mgr->regs->reg)
47
48 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
49
50 #define BASE(seg) BASE_INNER(seg)
51
52 #define SR(reg_name)\
53 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
54 mm ## reg_name
55
56 #define CLK_BASE_INNER(seg) \
57 CLK_BASE__INST0_SEG ## seg
58
59
60 static const struct clk_mgr_registers clk_mgr_regs = {
61 CLK_REG_LIST_NV10()
62 };
63
64 static const struct clk_mgr_shift clk_mgr_shift = {
65 CLK_MASK_SH_LIST_NV10(__SHIFT)
66 };
67
68 static const struct clk_mgr_mask clk_mgr_mask = {
69 CLK_MASK_SH_LIST_NV10(_MASK)
70 };
71
dentist_get_did_from_divider(int divider)72 uint32_t dentist_get_did_from_divider(int divider)
73 {
74 uint32_t divider_id;
75
76 /* we want to floor here to get higher clock than required rather than lower */
77 if (divider < DENTIST_DIVIDER_RANGE_2_START) {
78 if (divider < DENTIST_DIVIDER_RANGE_1_START)
79 divider_id = DENTIST_BASE_DID_1;
80 else
81 divider_id = DENTIST_BASE_DID_1
82 + (divider - DENTIST_DIVIDER_RANGE_1_START)
83 / DENTIST_DIVIDER_RANGE_1_STEP;
84 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) {
85 divider_id = DENTIST_BASE_DID_2
86 + (divider - DENTIST_DIVIDER_RANGE_2_START)
87 / DENTIST_DIVIDER_RANGE_2_STEP;
88 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) {
89 divider_id = DENTIST_BASE_DID_3
90 + (divider - DENTIST_DIVIDER_RANGE_3_START)
91 / DENTIST_DIVIDER_RANGE_3_STEP;
92 } else {
93 divider_id = DENTIST_BASE_DID_4
94 + (divider - DENTIST_DIVIDER_RANGE_4_START)
95 / DENTIST_DIVIDER_RANGE_4_STEP;
96 if (divider_id > DENTIST_MAX_DID)
97 divider_id = DENTIST_MAX_DID;
98 }
99
100 return divider_id;
101 }
102
dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)103 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
104 struct dc_state *context, bool safe_to_lower)
105 {
106 int i;
107
108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
110 int dpp_inst, dppclk_khz, prev_dppclk_khz;
111
112 /* Loop index will match dpp->inst if resource exists,
113 * and we want to avoid dependency on dpp object
114 */
115 dpp_inst = i;
116 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
117
118 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
119
120 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
121 clk_mgr->dccg->funcs->update_dpp_dto(
122 clk_mgr->dccg, dpp_inst, dppclk_khz);
123 }
124 }
125
dcn20_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context)126 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context)
127 {
128 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
129 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
130 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
131 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
132
133 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
134 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
135 uint32_t current_dispclk_wdivider;
136 uint32_t i;
137
138 REG_GET(DENTIST_DISPCLK_CNTL,
139 DENTIST_DISPCLK_WDIVIDER, ¤t_dispclk_wdivider);
140
141 /* When changing divider to or from 127, some extra programming is required to prevent corruption */
142 if (current_dispclk_wdivider == 127 && dispclk_wdivider != 127) {
143 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
144 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
145 uint32_t fifo_level;
146 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
147 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
148 int32_t N;
149 int32_t j;
150
151 if (!pipe_ctx->stream)
152 continue;
153 /* Virtual encoders don't have this function */
154 if (!stream_enc->funcs->get_fifo_cal_average_level)
155 continue;
156 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
157 stream_enc);
158 N = fifo_level / 4;
159 dccg->funcs->set_fifo_errdet_ovr_en(
160 dccg,
161 true);
162 for (j = 0; j < N - 4; j++)
163 dccg->funcs->otg_drop_pixel(
164 dccg,
165 pipe_ctx->stream_res.tg->inst);
166 dccg->funcs->set_fifo_errdet_ovr_en(
167 dccg,
168 false);
169 }
170 } else if (dispclk_wdivider == 127 && current_dispclk_wdivider != 127) {
171 REG_UPDATE(DENTIST_DISPCLK_CNTL,
172 DENTIST_DISPCLK_WDIVIDER, 126);
173 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 100);
174 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
175 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
176 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
177 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
178 uint32_t fifo_level;
179 int32_t N;
180 int32_t j;
181
182 if (!pipe_ctx->stream)
183 continue;
184 /* Virtual encoders don't have this function */
185 if (!stream_enc->funcs->get_fifo_cal_average_level)
186 continue;
187 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
188 stream_enc);
189 N = fifo_level / 4;
190 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
191 for (j = 0; j < 12 - N; j++)
192 dccg->funcs->otg_add_pixel(dccg,
193 pipe_ctx->stream_res.tg->inst);
194 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
195 }
196 }
197
198 REG_UPDATE(DENTIST_DISPCLK_CNTL,
199 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
200 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 1000);
201 REG_UPDATE(DENTIST_DISPCLK_CNTL,
202 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
203 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
204 }
205
206
dcn2_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)207 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
208 struct dc_state *context,
209 bool safe_to_lower)
210 {
211 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
212 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
213 struct dc *dc = clk_mgr_base->ctx->dc;
214 struct pp_smu_funcs_nv *pp_smu = NULL;
215 int display_count;
216 bool update_dppclk = false;
217 bool update_dispclk = false;
218 bool enter_display_off = false;
219 bool dpp_clock_lowered = false;
220 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
221 bool force_reset = false;
222 bool p_state_change_support;
223 int total_plane_count;
224
225 if (dc->work_arounds.skip_clock_update)
226 return;
227
228 if (clk_mgr_base->clks.dispclk_khz == 0 ||
229 dc->debug.force_clock_mode & 0x1) {
230 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
231 force_reset = true;
232
233 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
234
235 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level.
236 }
237 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
238 if (dc->res_pool->pp_smu)
239 pp_smu = &dc->res_pool->pp_smu->nv_funcs;
240
241 if (display_count == 0)
242 enter_display_off = true;
243
244 if (enter_display_off == safe_to_lower) {
245 if (pp_smu && pp_smu->set_display_count)
246 pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
247 }
248
249 if (dc->debug.force_min_dcfclk_mhz > 0)
250 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
251 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
252
253 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
254 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
255 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq)
256 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
257 }
258
259 if (should_set_clock(safe_to_lower,
260 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
261 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
262 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
263 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
264 }
265
266 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) {
267 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
268 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq)
269 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.socclk_khz));
270 }
271
272 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
273 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
274 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
275 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
276 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
277 if (pp_smu && pp_smu->set_pstate_handshake_support)
278 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
279 }
280
281 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
282 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
283 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
284 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
285 }
286
287 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
288 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
289 dpp_clock_lowered = true;
290 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
291
292 update_dppclk = true;
293 }
294
295 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
296 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
297
298 update_dispclk = true;
299 }
300
301 if (update_dppclk || update_dispclk) {
302 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dppclk_khz;
303
304 if (update_dispclk)
305 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dispclk_khz > new_clocks->dppclk_khz ? new_clocks->dispclk_khz : new_clocks->dppclk_khz;
306
307 clk_mgr_base->clks.disp_dpp_voltage_level_khz = new_clocks->disp_dpp_voltage_level_khz;
308 if (pp_smu && pp_smu->set_voltage_by_freq)
309 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.disp_dpp_voltage_level_khz));
310 }
311
312 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
313 if (dpp_clock_lowered) {
314 // if clock is being lowered, increase DTO before lowering refclk
315 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
316 dcn20_update_clocks_update_dentist(clk_mgr, context);
317 } else {
318 // if clock is being raised, increase refclk before lowering DTO
319 if (update_dppclk || update_dispclk)
320 dcn20_update_clocks_update_dentist(clk_mgr, context);
321 // always update dtos unless clock is lowered and not safe to lower
322 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
323 }
324 }
325
326 if (update_dispclk &&
327 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
328 /*update dmcu for wait_loop count*/
329 dmcu->funcs->set_psr_wait_loop(dmcu,
330 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
331 }
332 }
333
dcn2_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)334 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
335 struct dc_state *context,
336 bool safe_to_lower)
337 {
338 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
339
340 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
341 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
342 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
343
344 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
345 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
346 }
347
348 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
349 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
350 }
351
352 if (should_set_clock(safe_to_lower,
353 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
354 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
355 }
356
357 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
358 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
359 }
360
361 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
362 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
363 }
364
365 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
366 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
367 }
368
369 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
370 clk_mgr->clks.fclk_khz = fclk_adj;
371 }
372
373 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
374 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
375 }
376
377 /* Both fclk and ref_dppclk run on the same scemi clock.
378 * So take the higher value since the DPP DTO is typically programmed
379 * such that max dppclk is 1:1 with ref_dppclk.
380 */
381 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
382 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
383 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
384 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
385
386 // Both fclk and ref_dppclk run on the same scemi clock.
387 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
388
389 /* TODO: set dtbclk in correct place */
390 clk_mgr->clks.dtbclk_en = false;
391 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
392 }
393
dcn2_init_clocks(struct clk_mgr * clk_mgr)394 void dcn2_init_clocks(struct clk_mgr *clk_mgr)
395 {
396 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
397 // Assumption is that boot state always supports pstate
398 clk_mgr->clks.p_state_change_support = true;
399 clk_mgr->clks.prev_p_state_change_support = true;
400 }
401
dcn2_enable_pme_wa(struct clk_mgr * clk_mgr_base)402 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
403 {
404 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
405 struct pp_smu_funcs_nv *pp_smu = NULL;
406
407 if (clk_mgr->pp_smu) {
408 pp_smu = &clk_mgr->pp_smu->nv_funcs;
409
410 if (pp_smu->set_pme_wa_enable)
411 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
412 }
413 }
414
415
dcn2_read_clocks_from_hw_dentist(struct clk_mgr * clk_mgr_base)416 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
417 {
418 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
419 uint32_t dispclk_wdivider;
420 uint32_t dppclk_wdivider;
421 int disp_divider;
422 int dpp_divider;
423
424 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
425 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider);
426
427 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
428 dpp_divider = dentist_get_divider_from_did(dppclk_wdivider);
429
430 if (disp_divider && dpp_divider) {
431 /* Calculate the current DFS clock, in kHz.*/
432 clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
433 * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
434
435 clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
436 * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
437 }
438
439 }
440
dcn2_get_clock(struct clk_mgr * clk_mgr,struct dc_state * context,enum dc_clock_type clock_type,struct dc_clock_config * clock_cfg)441 void dcn2_get_clock(struct clk_mgr *clk_mgr,
442 struct dc_state *context,
443 enum dc_clock_type clock_type,
444 struct dc_clock_config *clock_cfg)
445 {
446
447 if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
448 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
449 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
450 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
451 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
452 }
453 if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
454 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
455 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
456 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
457 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
458 }
459 }
460
dcn2_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)461 static bool dcn2_are_clock_states_equal(struct dc_clocks *a,
462 struct dc_clocks *b)
463 {
464 if (a->dispclk_khz != b->dispclk_khz)
465 return false;
466 else if (a->dppclk_khz != b->dppclk_khz)
467 return false;
468 else if (a->disp_dpp_voltage_level_khz != b->disp_dpp_voltage_level_khz)
469 return false;
470 else if (a->dcfclk_khz != b->dcfclk_khz)
471 return false;
472 else if (a->socclk_khz != b->socclk_khz)
473 return false;
474 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
475 return false;
476 else if (a->dramclk_khz != b->dramclk_khz)
477 return false;
478 else if (a->p_state_change_support != b->p_state_change_support)
479 return false;
480
481 return true;
482 }
483
484 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
dcn2_notify_link_rate_change(struct clk_mgr * clk_mgr_base,struct dc_link * link)485 static void dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
486 {
487 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
488 unsigned int i, max_phyclk_req = 0;
489 struct pp_smu_funcs_nv *pp_smu = NULL;
490
491 if (!clk_mgr->pp_smu || !clk_mgr->pp_smu->nv_funcs.set_voltage_by_freq)
492 return;
493
494 pp_smu = &clk_mgr->pp_smu->nv_funcs;
495
496 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
497
498 for (i = 0; i < MAX_PIPES * 2; i++) {
499 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
500 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
501 }
502
503 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
504 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
505 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
506 }
507 }
508
509 static struct clk_mgr_funcs dcn2_funcs = {
510 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
511 .update_clocks = dcn2_update_clocks,
512 .init_clocks = dcn2_init_clocks,
513 .enable_pme_wa = dcn2_enable_pme_wa,
514 .get_clock = dcn2_get_clock,
515 .are_clock_states_equal = dcn2_are_clock_states_equal,
516 .notify_link_rate_change = dcn2_notify_link_rate_change,
517 };
518
519
dcn20_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)520 void dcn20_clk_mgr_construct(
521 struct dc_context *ctx,
522 struct clk_mgr_internal *clk_mgr,
523 struct pp_smu_funcs *pp_smu,
524 struct dccg *dccg)
525 {
526 clk_mgr->base.ctx = ctx;
527 clk_mgr->pp_smu = pp_smu;
528 clk_mgr->base.funcs = &dcn2_funcs;
529 clk_mgr->regs = &clk_mgr_regs;
530 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
531 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
532
533 clk_mgr->dccg = dccg;
534 clk_mgr->dfs_bypass_disp_clk = 0;
535
536 clk_mgr->dprefclk_ss_percentage = 0;
537 clk_mgr->dprefclk_ss_divider = 1000;
538 clk_mgr->ss_on_dprefclk = false;
539
540 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
541
542 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
543 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga;
544 clk_mgr->base.dentist_vco_freq_khz = 3850000;
545
546 } else {
547 /* DFS Slice 2 should be used for DPREFCLK */
548 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL);
549 /* Convert DPREFCLK DFS Slice DID to actual divider*/
550 int target_div = dentist_get_divider_from_did(dprefclk_did);
551
552 /* get FbMult value */
553 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ);
554 struct fixed31_32 pll_req;
555
556 /* set up a fixed-point number
557 * this works because the int part is on the right edge of the register
558 * and the frac part is on the left edge
559 */
560
561 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
562 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
563
564 /* multiply by REFCLK period */
565 pll_req = dc_fixpt_mul_int(pll_req, 100000);
566
567 /* integer part is now VCO frequency in kHz */
568 clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req);
569
570 /* in case we don't get a value from the register, use default */
571 if (clk_mgr->base.dentist_vco_freq_khz == 0)
572 clk_mgr->base.dentist_vco_freq_khz = 3850000;
573
574 /* Calculate the DPREFCLK in kHz.*/
575 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
576 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
577 }
578 //Integrated_info table does not exist on dGPU projects so should not be referenced
579 //anywhere in code for dGPUs.
580 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14.
581 clk_mgr->dfs_bypass_enabled = false;
582
583 dce_clock_read_ss_info(clk_mgr);
584 }
585
586