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Searched refs:WREG32_NO_KIQ (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_ai.c142 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), in xgpu_ai_mailbox_trans_msg()
144 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), in xgpu_ai_mailbox_trans_msg()
146 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), in xgpu_ai_mailbox_trans_msg()
148 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), in xgpu_ai_mailbox_trans_msg()
240 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_ack_irq()
291 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_rcv_irq()
Dmxgpu_nv.c139 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, req); in xgpu_nv_mailbox_trans_msg()
140 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW1, data1); in xgpu_nv_mailbox_trans_msg()
141 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW2, data2); in xgpu_nv_mailbox_trans_msg()
142 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW3, data3); in xgpu_nv_mailbox_trans_msg()
269 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_nv_set_mailbox_ack_irq()
326 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_nv_set_mailbox_rcv_irq()
Dmxgpu_vi.c325 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_send_ack()
348 WREG32_NO_KIQ(mmMAILBOX_CONTROL, reg); in xgpu_vi_mailbox_set_valid()
359 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg); in xgpu_vi_mailbox_trans_msg()
506 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_ack_irq()
536 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp); in xgpu_vi_set_mailbox_rcv_irq()
Dhdp_v4_0.c44 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); in hdp_v4_0_flush_hdp()
Dvi.c304 WREG32_NO_KIQ(mmPCIE_INDEX, reg); in vi_pcie_rreg()
316 WREG32_NO_KIQ(mmPCIE_INDEX, reg); in vi_pcie_wreg()
318 WREG32_NO_KIQ(mmPCIE_DATA, v); in vi_pcie_wreg()
329 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); in vi_smc_rreg()
340 WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); in vi_smc_wreg()
341 WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v)); in vi_smc_wreg()
Dhdp_v5_0.c35 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); in hdp_v5_0_flush_hdp()
Dgmc_v9_0.c805 WREG32_NO_KIQ(hub->vm_inv_eng0_req + in gmc_v9_0_flush_gpu_tlb()
836 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + in gmc_v9_0_flush_gpu_tlb()
Dvega10_ih.c372 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega10_ih_get_wptr()
Dnavi10_ih.c449 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in navi10_ih_get_wptr()
Dvega20_ih.c423 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega20_ih_get_wptr()
Damdgpu.h1164 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) macro
Damdgpu_device.c325 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000); in amdgpu_device_mm_access()
327 WREG32_NO_KIQ(mmMM_INDEX_HI, tmp); in amdgpu_device_mm_access()
331 WREG32_NO_KIQ(mmMM_DATA, *data++); in amdgpu_device_mm_access()
Dgfx_v8_0.c5636 WREG32_NO_KIQ(mmRLC_SPM_VMID, data); in gfx_v8_0_update_spm_vmid()
Dgfx_v9_0.c806 WREG32_NO_KIQ(offset, v); in gfx_v9_0_sriov_wreg()
Dgfx_v10_0.c1603 WREG32_NO_KIQ(offset, value); in gfx_v10_sriov_wreg()