1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/pci.h>
26
27 #include <drm/drm_cache.h>
28
29 #include "amdgpu.h"
30 #include "gmc_v9_0.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_gem.h"
33
34 #include "gc/gc_9_0_sh_mask.h"
35 #include "dce/dce_12_0_offset.h"
36 #include "dce/dce_12_0_sh_mask.h"
37 #include "vega10_enum.h"
38 #include "mmhub/mmhub_1_0_offset.h"
39 #include "athub/athub_1_0_sh_mask.h"
40 #include "athub/athub_1_0_offset.h"
41 #include "oss/osssys_4_0_offset.h"
42
43 #include "soc15.h"
44 #include "soc15d.h"
45 #include "soc15_common.h"
46 #include "umc/umc_6_0_sh_mask.h"
47
48 #include "gfxhub_v1_0.h"
49 #include "mmhub_v1_0.h"
50 #include "athub_v1_0.h"
51 #include "gfxhub_v1_1.h"
52 #include "mmhub_v9_4.h"
53 #include "mmhub_v1_7.h"
54 #include "umc_v6_1.h"
55 #include "umc_v6_0.h"
56 #include "umc_v6_7.h"
57 #include "hdp_v4_0.h"
58 #include "mca_v3_0.h"
59
60 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
61
62 #include "amdgpu_ras.h"
63 #include "amdgpu_xgmi.h"
64
65 /* add these here since we already include dce12 headers and these are for DCN */
66 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
67 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
69 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
70 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
72 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
73 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
74
75 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea
76 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2
77
78
79 static const char *gfxhub_client_ids[] = {
80 "CB",
81 "DB",
82 "IA",
83 "WD",
84 "CPF",
85 "CPC",
86 "CPG",
87 "RLC",
88 "TCP",
89 "SQC (inst)",
90 "SQC (data)",
91 "SQG",
92 "PA",
93 };
94
95 static const char *mmhub_client_ids_raven[][2] = {
96 [0][0] = "MP1",
97 [1][0] = "MP0",
98 [2][0] = "VCN",
99 [3][0] = "VCNU",
100 [4][0] = "HDP",
101 [5][0] = "DCE",
102 [13][0] = "UTCL2",
103 [19][0] = "TLS",
104 [26][0] = "OSS",
105 [27][0] = "SDMA0",
106 [0][1] = "MP1",
107 [1][1] = "MP0",
108 [2][1] = "VCN",
109 [3][1] = "VCNU",
110 [4][1] = "HDP",
111 [5][1] = "XDP",
112 [6][1] = "DBGU0",
113 [7][1] = "DCE",
114 [8][1] = "DCEDWB0",
115 [9][1] = "DCEDWB1",
116 [26][1] = "OSS",
117 [27][1] = "SDMA0",
118 };
119
120 static const char *mmhub_client_ids_renoir[][2] = {
121 [0][0] = "MP1",
122 [1][0] = "MP0",
123 [2][0] = "HDP",
124 [4][0] = "DCEDMC",
125 [5][0] = "DCEVGA",
126 [13][0] = "UTCL2",
127 [19][0] = "TLS",
128 [26][0] = "OSS",
129 [27][0] = "SDMA0",
130 [28][0] = "VCN",
131 [29][0] = "VCNU",
132 [30][0] = "JPEG",
133 [0][1] = "MP1",
134 [1][1] = "MP0",
135 [2][1] = "HDP",
136 [3][1] = "XDP",
137 [6][1] = "DBGU0",
138 [7][1] = "DCEDMC",
139 [8][1] = "DCEVGA",
140 [9][1] = "DCEDWB",
141 [26][1] = "OSS",
142 [27][1] = "SDMA0",
143 [28][1] = "VCN",
144 [29][1] = "VCNU",
145 [30][1] = "JPEG",
146 };
147
148 static const char *mmhub_client_ids_vega10[][2] = {
149 [0][0] = "MP0",
150 [1][0] = "UVD",
151 [2][0] = "UVDU",
152 [3][0] = "HDP",
153 [13][0] = "UTCL2",
154 [14][0] = "OSS",
155 [15][0] = "SDMA1",
156 [32+0][0] = "VCE0",
157 [32+1][0] = "VCE0U",
158 [32+2][0] = "XDMA",
159 [32+3][0] = "DCE",
160 [32+4][0] = "MP1",
161 [32+14][0] = "SDMA0",
162 [0][1] = "MP0",
163 [1][1] = "UVD",
164 [2][1] = "UVDU",
165 [3][1] = "DBGU0",
166 [4][1] = "HDP",
167 [5][1] = "XDP",
168 [14][1] = "OSS",
169 [15][1] = "SDMA0",
170 [32+0][1] = "VCE0",
171 [32+1][1] = "VCE0U",
172 [32+2][1] = "XDMA",
173 [32+3][1] = "DCE",
174 [32+4][1] = "DCEDWB",
175 [32+5][1] = "MP1",
176 [32+6][1] = "DBGU1",
177 [32+14][1] = "SDMA1",
178 };
179
180 static const char *mmhub_client_ids_vega12[][2] = {
181 [0][0] = "MP0",
182 [1][0] = "VCE0",
183 [2][0] = "VCE0U",
184 [3][0] = "HDP",
185 [13][0] = "UTCL2",
186 [14][0] = "OSS",
187 [15][0] = "SDMA1",
188 [32+0][0] = "DCE",
189 [32+1][0] = "XDMA",
190 [32+2][0] = "UVD",
191 [32+3][0] = "UVDU",
192 [32+4][0] = "MP1",
193 [32+15][0] = "SDMA0",
194 [0][1] = "MP0",
195 [1][1] = "VCE0",
196 [2][1] = "VCE0U",
197 [3][1] = "DBGU0",
198 [4][1] = "HDP",
199 [5][1] = "XDP",
200 [14][1] = "OSS",
201 [15][1] = "SDMA0",
202 [32+0][1] = "DCE",
203 [32+1][1] = "DCEDWB",
204 [32+2][1] = "XDMA",
205 [32+3][1] = "UVD",
206 [32+4][1] = "UVDU",
207 [32+5][1] = "MP1",
208 [32+6][1] = "DBGU1",
209 [32+15][1] = "SDMA1",
210 };
211
212 static const char *mmhub_client_ids_vega20[][2] = {
213 [0][0] = "XDMA",
214 [1][0] = "DCE",
215 [2][0] = "VCE0",
216 [3][0] = "VCE0U",
217 [4][0] = "UVD",
218 [5][0] = "UVD1U",
219 [13][0] = "OSS",
220 [14][0] = "HDP",
221 [15][0] = "SDMA0",
222 [32+0][0] = "UVD",
223 [32+1][0] = "UVDU",
224 [32+2][0] = "MP1",
225 [32+3][0] = "MP0",
226 [32+12][0] = "UTCL2",
227 [32+14][0] = "SDMA1",
228 [0][1] = "XDMA",
229 [1][1] = "DCE",
230 [2][1] = "DCEDWB",
231 [3][1] = "VCE0",
232 [4][1] = "VCE0U",
233 [5][1] = "UVD1",
234 [6][1] = "UVD1U",
235 [7][1] = "DBGU0",
236 [8][1] = "XDP",
237 [13][1] = "OSS",
238 [14][1] = "HDP",
239 [15][1] = "SDMA0",
240 [32+0][1] = "UVD",
241 [32+1][1] = "UVDU",
242 [32+2][1] = "DBGU1",
243 [32+3][1] = "MP1",
244 [32+4][1] = "MP0",
245 [32+14][1] = "SDMA1",
246 };
247
248 static const char *mmhub_client_ids_arcturus[][2] = {
249 [0][0] = "DBGU1",
250 [1][0] = "XDP",
251 [2][0] = "MP1",
252 [14][0] = "HDP",
253 [171][0] = "JPEG",
254 [172][0] = "VCN",
255 [173][0] = "VCNU",
256 [203][0] = "JPEG1",
257 [204][0] = "VCN1",
258 [205][0] = "VCN1U",
259 [256][0] = "SDMA0",
260 [257][0] = "SDMA1",
261 [258][0] = "SDMA2",
262 [259][0] = "SDMA3",
263 [260][0] = "SDMA4",
264 [261][0] = "SDMA5",
265 [262][0] = "SDMA6",
266 [263][0] = "SDMA7",
267 [384][0] = "OSS",
268 [0][1] = "DBGU1",
269 [1][1] = "XDP",
270 [2][1] = "MP1",
271 [14][1] = "HDP",
272 [171][1] = "JPEG",
273 [172][1] = "VCN",
274 [173][1] = "VCNU",
275 [203][1] = "JPEG1",
276 [204][1] = "VCN1",
277 [205][1] = "VCN1U",
278 [256][1] = "SDMA0",
279 [257][1] = "SDMA1",
280 [258][1] = "SDMA2",
281 [259][1] = "SDMA3",
282 [260][1] = "SDMA4",
283 [261][1] = "SDMA5",
284 [262][1] = "SDMA6",
285 [263][1] = "SDMA7",
286 [384][1] = "OSS",
287 };
288
289 static const char *mmhub_client_ids_aldebaran[][2] = {
290 [2][0] = "MP1",
291 [3][0] = "MP0",
292 [32+1][0] = "DBGU_IO0",
293 [32+2][0] = "DBGU_IO2",
294 [32+4][0] = "MPIO",
295 [96+11][0] = "JPEG0",
296 [96+12][0] = "VCN0",
297 [96+13][0] = "VCNU0",
298 [128+11][0] = "JPEG1",
299 [128+12][0] = "VCN1",
300 [128+13][0] = "VCNU1",
301 [160+1][0] = "XDP",
302 [160+14][0] = "HDP",
303 [256+0][0] = "SDMA0",
304 [256+1][0] = "SDMA1",
305 [256+2][0] = "SDMA2",
306 [256+3][0] = "SDMA3",
307 [256+4][0] = "SDMA4",
308 [384+0][0] = "OSS",
309 [2][1] = "MP1",
310 [3][1] = "MP0",
311 [32+1][1] = "DBGU_IO0",
312 [32+2][1] = "DBGU_IO2",
313 [32+4][1] = "MPIO",
314 [96+11][1] = "JPEG0",
315 [96+12][1] = "VCN0",
316 [96+13][1] = "VCNU0",
317 [128+11][1] = "JPEG1",
318 [128+12][1] = "VCN1",
319 [128+13][1] = "VCNU1",
320 [160+1][1] = "XDP",
321 [160+14][1] = "HDP",
322 [256+0][1] = "SDMA0",
323 [256+1][1] = "SDMA1",
324 [256+2][1] = "SDMA2",
325 [256+3][1] = "SDMA3",
326 [256+4][1] = "SDMA4",
327 [384+0][1] = "OSS",
328 };
329
330 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
331 {
332 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
333 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
334 };
335
336 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
337 {
338 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
339 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
340 };
341
342 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
343 (0x000143c0 + 0x00000000),
344 (0x000143c0 + 0x00000800),
345 (0x000143c0 + 0x00001000),
346 (0x000143c0 + 0x00001800),
347 (0x000543c0 + 0x00000000),
348 (0x000543c0 + 0x00000800),
349 (0x000543c0 + 0x00001000),
350 (0x000543c0 + 0x00001800),
351 (0x000943c0 + 0x00000000),
352 (0x000943c0 + 0x00000800),
353 (0x000943c0 + 0x00001000),
354 (0x000943c0 + 0x00001800),
355 (0x000d43c0 + 0x00000000),
356 (0x000d43c0 + 0x00000800),
357 (0x000d43c0 + 0x00001000),
358 (0x000d43c0 + 0x00001800),
359 (0x001143c0 + 0x00000000),
360 (0x001143c0 + 0x00000800),
361 (0x001143c0 + 0x00001000),
362 (0x001143c0 + 0x00001800),
363 (0x001543c0 + 0x00000000),
364 (0x001543c0 + 0x00000800),
365 (0x001543c0 + 0x00001000),
366 (0x001543c0 + 0x00001800),
367 (0x001943c0 + 0x00000000),
368 (0x001943c0 + 0x00000800),
369 (0x001943c0 + 0x00001000),
370 (0x001943c0 + 0x00001800),
371 (0x001d43c0 + 0x00000000),
372 (0x001d43c0 + 0x00000800),
373 (0x001d43c0 + 0x00001000),
374 (0x001d43c0 + 0x00001800),
375 };
376
377 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
378 (0x000143e0 + 0x00000000),
379 (0x000143e0 + 0x00000800),
380 (0x000143e0 + 0x00001000),
381 (0x000143e0 + 0x00001800),
382 (0x000543e0 + 0x00000000),
383 (0x000543e0 + 0x00000800),
384 (0x000543e0 + 0x00001000),
385 (0x000543e0 + 0x00001800),
386 (0x000943e0 + 0x00000000),
387 (0x000943e0 + 0x00000800),
388 (0x000943e0 + 0x00001000),
389 (0x000943e0 + 0x00001800),
390 (0x000d43e0 + 0x00000000),
391 (0x000d43e0 + 0x00000800),
392 (0x000d43e0 + 0x00001000),
393 (0x000d43e0 + 0x00001800),
394 (0x001143e0 + 0x00000000),
395 (0x001143e0 + 0x00000800),
396 (0x001143e0 + 0x00001000),
397 (0x001143e0 + 0x00001800),
398 (0x001543e0 + 0x00000000),
399 (0x001543e0 + 0x00000800),
400 (0x001543e0 + 0x00001000),
401 (0x001543e0 + 0x00001800),
402 (0x001943e0 + 0x00000000),
403 (0x001943e0 + 0x00000800),
404 (0x001943e0 + 0x00001000),
405 (0x001943e0 + 0x00001800),
406 (0x001d43e0 + 0x00000000),
407 (0x001d43e0 + 0x00000800),
408 (0x001d43e0 + 0x00001000),
409 (0x001d43e0 + 0x00001800),
410 };
411
gmc_v9_0_ecc_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)412 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
413 struct amdgpu_irq_src *src,
414 unsigned type,
415 enum amdgpu_interrupt_state state)
416 {
417 u32 bits, i, tmp, reg;
418
419 /* Devices newer then VEGA10/12 shall have these programming
420 sequences performed by PSP BL */
421 if (adev->asic_type >= CHIP_VEGA20)
422 return 0;
423
424 bits = 0x7f;
425
426 switch (state) {
427 case AMDGPU_IRQ_STATE_DISABLE:
428 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
429 reg = ecc_umc_mcumc_ctrl_addrs[i];
430 tmp = RREG32(reg);
431 tmp &= ~bits;
432 WREG32(reg, tmp);
433 }
434 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
435 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
436 tmp = RREG32(reg);
437 tmp &= ~bits;
438 WREG32(reg, tmp);
439 }
440 break;
441 case AMDGPU_IRQ_STATE_ENABLE:
442 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
443 reg = ecc_umc_mcumc_ctrl_addrs[i];
444 tmp = RREG32(reg);
445 tmp |= bits;
446 WREG32(reg, tmp);
447 }
448 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
449 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
450 tmp = RREG32(reg);
451 tmp |= bits;
452 WREG32(reg, tmp);
453 }
454 break;
455 default:
456 break;
457 }
458
459 return 0;
460 }
461
gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)462 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
463 struct amdgpu_irq_src *src,
464 unsigned type,
465 enum amdgpu_interrupt_state state)
466 {
467 struct amdgpu_vmhub *hub;
468 u32 tmp, reg, bits, i, j;
469
470 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
471 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
472 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
473 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
474 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
475 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
476 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
477
478 switch (state) {
479 case AMDGPU_IRQ_STATE_DISABLE:
480 for (j = 0; j < adev->num_vmhubs; j++) {
481 hub = &adev->vmhub[j];
482 for (i = 0; i < 16; i++) {
483 reg = hub->vm_context0_cntl + i;
484 tmp = RREG32(reg);
485 tmp &= ~bits;
486 WREG32(reg, tmp);
487 }
488 }
489 break;
490 case AMDGPU_IRQ_STATE_ENABLE:
491 for (j = 0; j < adev->num_vmhubs; j++) {
492 hub = &adev->vmhub[j];
493 for (i = 0; i < 16; i++) {
494 reg = hub->vm_context0_cntl + i;
495 tmp = RREG32(reg);
496 tmp |= bits;
497 WREG32(reg, tmp);
498 }
499 }
500 break;
501 default:
502 break;
503 }
504
505 return 0;
506 }
507
gmc_v9_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)508 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
509 struct amdgpu_irq_src *source,
510 struct amdgpu_iv_entry *entry)
511 {
512 bool retry_fault = !!(entry->src_data[1] & 0x80);
513 bool write_fault = !!(entry->src_data[1] & 0x20);
514 uint32_t status = 0, cid = 0, rw = 0;
515 struct amdgpu_task_info task_info;
516 struct amdgpu_vmhub *hub;
517 const char *mmhub_cid;
518 const char *hub_name;
519 u64 addr;
520
521 addr = (u64)entry->src_data[0] << 12;
522 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
523
524 if (retry_fault) {
525 /* Returning 1 here also prevents sending the IV to the KFD */
526
527 /* Process it onyl if it's the first fault for this address */
528 if (entry->ih != &adev->irq.ih_soft &&
529 amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
530 entry->timestamp))
531 return 1;
532
533 /* Delegate it to a different ring if the hardware hasn't
534 * already done it.
535 */
536 if (entry->ih == &adev->irq.ih) {
537 amdgpu_irq_delegate(adev, entry, 8);
538 return 1;
539 }
540
541 /* Try to handle the recoverable page faults by filling page
542 * tables
543 */
544 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault))
545 return 1;
546 }
547
548 if (!printk_ratelimit())
549 return 0;
550
551 if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
552 hub_name = "mmhub0";
553 hub = &adev->vmhub[AMDGPU_MMHUB_0];
554 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
555 hub_name = "mmhub1";
556 hub = &adev->vmhub[AMDGPU_MMHUB_1];
557 } else {
558 hub_name = "gfxhub0";
559 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
560 }
561
562 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
563 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
564
565 dev_err(adev->dev,
566 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
567 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
568 hub_name, retry_fault ? "retry" : "no-retry",
569 entry->src_id, entry->ring_id, entry->vmid,
570 entry->pasid, task_info.process_name, task_info.tgid,
571 task_info.task_name, task_info.pid);
572 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
573 addr, entry->client_id,
574 soc15_ih_clientid_name[entry->client_id]);
575
576 if (amdgpu_sriov_vf(adev))
577 return 0;
578
579 /*
580 * Issue a dummy read to wait for the status register to
581 * be updated to avoid reading an incorrect value due to
582 * the new fast GRBM interface.
583 */
584 if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
585 (adev->asic_type < CHIP_ALDEBARAN))
586 RREG32(hub->vm_l2_pro_fault_status);
587
588 status = RREG32(hub->vm_l2_pro_fault_status);
589 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
590 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
591 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
592
593
594 dev_err(adev->dev,
595 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
596 status);
597 if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) {
598 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
599 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
600 gfxhub_client_ids[cid],
601 cid);
602 } else {
603 switch (adev->asic_type) {
604 case CHIP_VEGA10:
605 mmhub_cid = mmhub_client_ids_vega10[cid][rw];
606 break;
607 case CHIP_VEGA12:
608 mmhub_cid = mmhub_client_ids_vega12[cid][rw];
609 break;
610 case CHIP_VEGA20:
611 mmhub_cid = mmhub_client_ids_vega20[cid][rw];
612 break;
613 case CHIP_ARCTURUS:
614 mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
615 break;
616 case CHIP_RAVEN:
617 mmhub_cid = mmhub_client_ids_raven[cid][rw];
618 break;
619 case CHIP_RENOIR:
620 mmhub_cid = mmhub_client_ids_renoir[cid][rw];
621 break;
622 case CHIP_ALDEBARAN:
623 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
624 break;
625 default:
626 mmhub_cid = NULL;
627 break;
628 }
629 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
630 mmhub_cid ? mmhub_cid : "unknown", cid);
631 }
632 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
633 REG_GET_FIELD(status,
634 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
635 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
636 REG_GET_FIELD(status,
637 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
638 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
639 REG_GET_FIELD(status,
640 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
641 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
642 REG_GET_FIELD(status,
643 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
644 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
645 return 0;
646 }
647
648 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
649 .set = gmc_v9_0_vm_fault_interrupt_state,
650 .process = gmc_v9_0_process_interrupt,
651 };
652
653
654 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
655 .set = gmc_v9_0_ecc_interrupt_state,
656 .process = amdgpu_umc_process_ecc_irq,
657 };
658
gmc_v9_0_set_irq_funcs(struct amdgpu_device * adev)659 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
660 {
661 adev->gmc.vm_fault.num_types = 1;
662 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
663
664 if (!amdgpu_sriov_vf(adev) &&
665 !adev->gmc.xgmi.connected_to_cpu) {
666 adev->gmc.ecc_irq.num_types = 1;
667 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
668 }
669 }
670
gmc_v9_0_get_invalidate_req(unsigned int vmid,uint32_t flush_type)671 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
672 uint32_t flush_type)
673 {
674 u32 req = 0;
675
676 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
677 PER_VMID_INVALIDATE_REQ, 1 << vmid);
678 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
679 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
680 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
681 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
682 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
683 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
684 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
685 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
686
687 return req;
688 }
689
690 /**
691 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
692 *
693 * @adev: amdgpu_device pointer
694 * @vmhub: vmhub type
695 *
696 */
gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device * adev,uint32_t vmhub)697 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
698 uint32_t vmhub)
699 {
700 if (adev->asic_type == CHIP_ALDEBARAN)
701 return false;
702
703 return ((vmhub == AMDGPU_MMHUB_0 ||
704 vmhub == AMDGPU_MMHUB_1) &&
705 (!amdgpu_sriov_vf(adev)) &&
706 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
707 (adev->apu_flags & AMD_APU_IS_PICASSO))));
708 }
709
gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device * adev,uint8_t vmid,uint16_t * p_pasid)710 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
711 uint8_t vmid, uint16_t *p_pasid)
712 {
713 uint32_t value;
714
715 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
716 + vmid);
717 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
718
719 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
720 }
721
722 /*
723 * GART
724 * VMID 0 is the physical GPU addresses as used by the kernel.
725 * VMIDs 1-15 are used for userspace clients and are handled
726 * by the amdgpu vm/hsa code.
727 */
728
729 /**
730 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
731 *
732 * @adev: amdgpu_device pointer
733 * @vmid: vm instance to flush
734 * @vmhub: which hub to flush
735 * @flush_type: the flush type
736 *
737 * Flush the TLB for the requested page table using certain type.
738 */
gmc_v9_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)739 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
740 uint32_t vmhub, uint32_t flush_type)
741 {
742 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
743 const unsigned eng = 17;
744 u32 j, inv_req, inv_req2, tmp;
745 struct amdgpu_vmhub *hub;
746
747 BUG_ON(vmhub >= adev->num_vmhubs);
748
749 hub = &adev->vmhub[vmhub];
750 if (adev->gmc.xgmi.num_physical_nodes &&
751 adev->asic_type == CHIP_VEGA20) {
752 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
753 * heavy-weight TLB flush (type 2), which flushes
754 * both. Due to a race condition with concurrent
755 * memory accesses using the same TLB cache line, we
756 * still need a second TLB flush after this.
757 */
758 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
759 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
760 } else {
761 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
762 inv_req2 = 0;
763 }
764
765 /* This is necessary for a HW workaround under SRIOV as well
766 * as GFXOFF under bare metal
767 */
768 if (adev->gfx.kiq.ring.sched.ready &&
769 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
770 down_read_trylock(&adev->reset_sem)) {
771 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
772 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
773
774 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
775 1 << vmid);
776 up_read(&adev->reset_sem);
777 return;
778 }
779
780 spin_lock(&adev->gmc.invalidate_lock);
781
782 /*
783 * It may lose gpuvm invalidate acknowldege state across power-gating
784 * off cycle, add semaphore acquire before invalidation and semaphore
785 * release after invalidation to avoid entering power gated state
786 * to WA the Issue
787 */
788
789 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
790 if (use_semaphore) {
791 for (j = 0; j < adev->usec_timeout; j++) {
792 /* a read return value of 1 means semaphore acuqire */
793 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
794 hub->eng_distance * eng);
795 if (tmp & 0x1)
796 break;
797 udelay(1);
798 }
799
800 if (j >= adev->usec_timeout)
801 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
802 }
803
804 do {
805 WREG32_NO_KIQ(hub->vm_inv_eng0_req +
806 hub->eng_distance * eng, inv_req);
807
808 /*
809 * Issue a dummy read to wait for the ACK register to
810 * be cleared to avoid a false ACK due to the new fast
811 * GRBM interface.
812 */
813 if ((vmhub == AMDGPU_GFXHUB_0) &&
814 (adev->asic_type < CHIP_ALDEBARAN))
815 RREG32_NO_KIQ(hub->vm_inv_eng0_req +
816 hub->eng_distance * eng);
817
818 for (j = 0; j < adev->usec_timeout; j++) {
819 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
820 hub->eng_distance * eng);
821 if (tmp & (1 << vmid))
822 break;
823 udelay(1);
824 }
825
826 inv_req = inv_req2;
827 inv_req2 = 0;
828 } while (inv_req);
829
830 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
831 if (use_semaphore)
832 /*
833 * add semaphore release after invalidation,
834 * write with 0 means semaphore release
835 */
836 WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
837 hub->eng_distance * eng, 0);
838
839 spin_unlock(&adev->gmc.invalidate_lock);
840
841 if (j < adev->usec_timeout)
842 return;
843
844 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
845 }
846
847 /**
848 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
849 *
850 * @adev: amdgpu_device pointer
851 * @pasid: pasid to be flush
852 * @flush_type: the flush type
853 * @all_hub: flush all hubs
854 *
855 * Flush the TLB for the requested pasid.
856 */
gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device * adev,uint16_t pasid,uint32_t flush_type,bool all_hub)857 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
858 uint16_t pasid, uint32_t flush_type,
859 bool all_hub)
860 {
861 int vmid, i;
862 signed long r;
863 uint32_t seq;
864 uint16_t queried_pasid;
865 bool ret;
866 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout;
867 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
868 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
869
870 if (amdgpu_in_reset(adev))
871 return -EIO;
872
873 if (ring->sched.ready && down_read_trylock(&adev->reset_sem)) {
874 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
875 * heavy-weight TLB flush (type 2), which flushes
876 * both. Due to a race condition with concurrent
877 * memory accesses using the same TLB cache line, we
878 * still need a second TLB flush after this.
879 */
880 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
881 adev->asic_type == CHIP_VEGA20);
882 /* 2 dwords flush + 8 dwords fence */
883 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
884
885 if (vega20_xgmi_wa)
886 ndw += kiq->pmf->invalidate_tlbs_size;
887
888 spin_lock(&adev->gfx.kiq.ring_lock);
889 /* 2 dwords flush + 8 dwords fence */
890 amdgpu_ring_alloc(ring, ndw);
891 if (vega20_xgmi_wa)
892 kiq->pmf->kiq_invalidate_tlbs(ring,
893 pasid, 2, all_hub);
894 kiq->pmf->kiq_invalidate_tlbs(ring,
895 pasid, flush_type, all_hub);
896 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
897 if (r) {
898 amdgpu_ring_undo(ring);
899 spin_unlock(&adev->gfx.kiq.ring_lock);
900 up_read(&adev->reset_sem);
901 return -ETIME;
902 }
903
904 amdgpu_ring_commit(ring);
905 spin_unlock(&adev->gfx.kiq.ring_lock);
906 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout);
907 if (r < 1) {
908 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
909 up_read(&adev->reset_sem);
910 return -ETIME;
911 }
912 up_read(&adev->reset_sem);
913 return 0;
914 }
915
916 for (vmid = 1; vmid < 16; vmid++) {
917
918 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
919 &queried_pasid);
920 if (ret && queried_pasid == pasid) {
921 if (all_hub) {
922 for (i = 0; i < adev->num_vmhubs; i++)
923 gmc_v9_0_flush_gpu_tlb(adev, vmid,
924 i, flush_type);
925 } else {
926 gmc_v9_0_flush_gpu_tlb(adev, vmid,
927 AMDGPU_GFXHUB_0, flush_type);
928 }
929 break;
930 }
931 }
932
933 return 0;
934
935 }
936
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)937 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
938 unsigned vmid, uint64_t pd_addr)
939 {
940 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
941 struct amdgpu_device *adev = ring->adev;
942 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
943 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
944 unsigned eng = ring->vm_inv_eng;
945
946 /*
947 * It may lose gpuvm invalidate acknowldege state across power-gating
948 * off cycle, add semaphore acquire before invalidation and semaphore
949 * release after invalidation to avoid entering power gated state
950 * to WA the Issue
951 */
952
953 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
954 if (use_semaphore)
955 /* a read return value of 1 means semaphore acuqire */
956 amdgpu_ring_emit_reg_wait(ring,
957 hub->vm_inv_eng0_sem +
958 hub->eng_distance * eng, 0x1, 0x1);
959
960 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
961 (hub->ctx_addr_distance * vmid),
962 lower_32_bits(pd_addr));
963
964 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
965 (hub->ctx_addr_distance * vmid),
966 upper_32_bits(pd_addr));
967
968 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
969 hub->eng_distance * eng,
970 hub->vm_inv_eng0_ack +
971 hub->eng_distance * eng,
972 req, 1 << vmid);
973
974 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
975 if (use_semaphore)
976 /*
977 * add semaphore release after invalidation,
978 * write with 0 means semaphore release
979 */
980 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
981 hub->eng_distance * eng, 0);
982
983 return pd_addr;
984 }
985
gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring * ring,unsigned vmid,unsigned pasid)986 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
987 unsigned pasid)
988 {
989 struct amdgpu_device *adev = ring->adev;
990 uint32_t reg;
991
992 /* Do nothing because there's no lut register for mmhub1. */
993 if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
994 return;
995
996 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
997 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
998 else
999 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
1000
1001 amdgpu_ring_emit_wreg(ring, reg, pasid);
1002 }
1003
1004 /*
1005 * PTE format on VEGA 10:
1006 * 63:59 reserved
1007 * 58:57 mtype
1008 * 56 F
1009 * 55 L
1010 * 54 P
1011 * 53 SW
1012 * 52 T
1013 * 50:48 reserved
1014 * 47:12 4k physical page base address
1015 * 11:7 fragment
1016 * 6 write
1017 * 5 read
1018 * 4 exe
1019 * 3 Z
1020 * 2 snooped
1021 * 1 system
1022 * 0 valid
1023 *
1024 * PDE format on VEGA 10:
1025 * 63:59 block fragment size
1026 * 58:55 reserved
1027 * 54 P
1028 * 53:48 reserved
1029 * 47:6 physical base address of PD or PTE
1030 * 5:3 reserved
1031 * 2 C
1032 * 1 system
1033 * 0 valid
1034 */
1035
gmc_v9_0_map_mtype(struct amdgpu_device * adev,uint32_t flags)1036 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1037
1038 {
1039 switch (flags) {
1040 case AMDGPU_VM_MTYPE_DEFAULT:
1041 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1042 case AMDGPU_VM_MTYPE_NC:
1043 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1044 case AMDGPU_VM_MTYPE_WC:
1045 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
1046 case AMDGPU_VM_MTYPE_RW:
1047 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
1048 case AMDGPU_VM_MTYPE_CC:
1049 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1050 case AMDGPU_VM_MTYPE_UC:
1051 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
1052 default:
1053 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1054 }
1055 }
1056
gmc_v9_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)1057 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1058 uint64_t *addr, uint64_t *flags)
1059 {
1060 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1061 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1062 BUG_ON(*addr & 0xFFFF00000000003FULL);
1063
1064 if (!adev->gmc.translate_further)
1065 return;
1066
1067 if (level == AMDGPU_VM_PDB1) {
1068 /* Set the block fragment size */
1069 if (!(*flags & AMDGPU_PDE_PTE))
1070 *flags |= AMDGPU_PDE_BFS(0x9);
1071
1072 } else if (level == AMDGPU_VM_PDB0) {
1073 if (*flags & AMDGPU_PDE_PTE)
1074 *flags &= ~AMDGPU_PDE_PTE;
1075 else
1076 *flags |= AMDGPU_PTE_TF;
1077 }
1078 }
1079
gmc_v9_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)1080 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1081 struct amdgpu_bo_va_mapping *mapping,
1082 uint64_t *flags)
1083 {
1084 *flags &= ~AMDGPU_PTE_EXECUTABLE;
1085 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1086
1087 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1088 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1089
1090 if (mapping->flags & AMDGPU_PTE_PRT) {
1091 *flags |= AMDGPU_PTE_PRT;
1092 *flags &= ~AMDGPU_PTE_VALID;
1093 }
1094
1095 if ((adev->asic_type == CHIP_ARCTURUS ||
1096 adev->asic_type == CHIP_ALDEBARAN) &&
1097 !(*flags & AMDGPU_PTE_SYSTEM) &&
1098 mapping->bo_va->is_xgmi)
1099 *flags |= AMDGPU_PTE_SNOOPED;
1100
1101 if (adev->asic_type == CHIP_ALDEBARAN)
1102 *flags |= mapping->flags & AMDGPU_PTE_SNOOPED;
1103 }
1104
gmc_v9_0_get_vbios_fb_size(struct amdgpu_device * adev)1105 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1106 {
1107 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1108 unsigned size;
1109
1110 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1111
1112 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1113 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1114 } else {
1115 u32 viewport;
1116
1117 switch (adev->asic_type) {
1118 case CHIP_RAVEN:
1119 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1120 size = (REG_GET_FIELD(viewport,
1121 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1122 REG_GET_FIELD(viewport,
1123 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1124 4);
1125 break;
1126 case CHIP_RENOIR:
1127 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1128 size = (REG_GET_FIELD(viewport,
1129 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1130 REG_GET_FIELD(viewport,
1131 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1132 4);
1133 break;
1134 case CHIP_VEGA10:
1135 case CHIP_VEGA12:
1136 case CHIP_VEGA20:
1137 default:
1138 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1139 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1140 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1141 4);
1142 break;
1143 }
1144 }
1145
1146 return size;
1147 }
1148
1149 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1150 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1151 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1152 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1153 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1154 .map_mtype = gmc_v9_0_map_mtype,
1155 .get_vm_pde = gmc_v9_0_get_vm_pde,
1156 .get_vm_pte = gmc_v9_0_get_vm_pte,
1157 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1158 };
1159
gmc_v9_0_set_gmc_funcs(struct amdgpu_device * adev)1160 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1161 {
1162 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1163 }
1164
gmc_v9_0_set_umc_funcs(struct amdgpu_device * adev)1165 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1166 {
1167 switch (adev->asic_type) {
1168 case CHIP_VEGA10:
1169 adev->umc.funcs = &umc_v6_0_funcs;
1170 break;
1171 case CHIP_VEGA20:
1172 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1173 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1174 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1175 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1176 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1177 adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1178 break;
1179 case CHIP_ARCTURUS:
1180 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1181 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1182 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1183 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1184 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1185 adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1186 break;
1187 case CHIP_ALDEBARAN:
1188 adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;
1189 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1190 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1191 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1192 if (!adev->gmc.xgmi.connected_to_cpu)
1193 adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
1194 if (1 & adev->smuio.funcs->get_die_id(adev))
1195 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1196 else
1197 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1198 break;
1199 default:
1200 break;
1201 }
1202 }
1203
gmc_v9_0_set_mmhub_funcs(struct amdgpu_device * adev)1204 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1205 {
1206 switch (adev->asic_type) {
1207 case CHIP_ARCTURUS:
1208 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1209 break;
1210 case CHIP_ALDEBARAN:
1211 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1212 break;
1213 default:
1214 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1215 break;
1216 }
1217 }
1218
gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device * adev)1219 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1220 {
1221 switch (adev->asic_type) {
1222 case CHIP_VEGA20:
1223 adev->mmhub.ras_funcs = &mmhub_v1_0_ras_funcs;
1224 break;
1225 case CHIP_ARCTURUS:
1226 adev->mmhub.ras_funcs = &mmhub_v9_4_ras_funcs;
1227 break;
1228 case CHIP_ALDEBARAN:
1229 adev->mmhub.ras_funcs = &mmhub_v1_7_ras_funcs;
1230 break;
1231 default:
1232 /* mmhub ras is not available */
1233 break;
1234 }
1235 }
1236
gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device * adev)1237 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1238 {
1239 adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1240 }
1241
gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device * adev)1242 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1243 {
1244 adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs;
1245 }
1246
gmc_v9_0_set_mca_funcs(struct amdgpu_device * adev)1247 static void gmc_v9_0_set_mca_funcs(struct amdgpu_device *adev)
1248 {
1249 switch (adev->asic_type) {
1250 case CHIP_ALDEBARAN:
1251 if (!adev->gmc.xgmi.connected_to_cpu)
1252 adev->mca.funcs = &mca_v3_0_funcs;
1253 break;
1254 default:
1255 break;
1256 }
1257 }
1258
gmc_v9_0_early_init(void * handle)1259 static int gmc_v9_0_early_init(void *handle)
1260 {
1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262
1263 if (adev->asic_type == CHIP_VEGA20 ||
1264 adev->asic_type == CHIP_ARCTURUS)
1265 adev->gmc.xgmi.supported = true;
1266
1267 if (adev->asic_type == CHIP_ALDEBARAN) {
1268 adev->gmc.xgmi.supported = true;
1269 adev->gmc.xgmi.connected_to_cpu =
1270 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1271 }
1272
1273 gmc_v9_0_set_gmc_funcs(adev);
1274 gmc_v9_0_set_irq_funcs(adev);
1275 gmc_v9_0_set_umc_funcs(adev);
1276 gmc_v9_0_set_mmhub_funcs(adev);
1277 gmc_v9_0_set_mmhub_ras_funcs(adev);
1278 gmc_v9_0_set_gfxhub_funcs(adev);
1279 gmc_v9_0_set_hdp_ras_funcs(adev);
1280 gmc_v9_0_set_mca_funcs(adev);
1281
1282 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1283 adev->gmc.shared_aperture_end =
1284 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1285 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1286 adev->gmc.private_aperture_end =
1287 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1288
1289 return 0;
1290 }
1291
gmc_v9_0_late_init(void * handle)1292 static int gmc_v9_0_late_init(void *handle)
1293 {
1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295 int r;
1296
1297 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1298 if (r)
1299 return r;
1300
1301 /*
1302 * Workaround performance drop issue with VBIOS enables partial
1303 * writes, while disables HBM ECC for vega10.
1304 */
1305 if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
1306 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1307 if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
1308 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1309 }
1310 }
1311
1312 if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1313 if (adev->mmhub.ras_funcs &&
1314 adev->mmhub.ras_funcs->reset_ras_error_count)
1315 adev->mmhub.ras_funcs->reset_ras_error_count(adev);
1316
1317 if (adev->hdp.ras_funcs &&
1318 adev->hdp.ras_funcs->reset_ras_error_count)
1319 adev->hdp.ras_funcs->reset_ras_error_count(adev);
1320 }
1321
1322 r = amdgpu_gmc_ras_late_init(adev);
1323 if (r)
1324 return r;
1325
1326 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1327 }
1328
gmc_v9_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)1329 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1330 struct amdgpu_gmc *mc)
1331 {
1332 u64 base = adev->mmhub.funcs->get_fb_location(adev);
1333
1334 /* add the xgmi offset of the physical node */
1335 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1336 if (adev->gmc.xgmi.connected_to_cpu) {
1337 amdgpu_gmc_sysvm_location(adev, mc);
1338 } else {
1339 amdgpu_gmc_vram_location(adev, mc, base);
1340 amdgpu_gmc_gart_location(adev, mc);
1341 amdgpu_gmc_agp_location(adev, mc);
1342 }
1343 /* base offset of vram pages */
1344 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1345
1346 /* XXX: add the xgmi offset of the physical node? */
1347 adev->vm_manager.vram_base_offset +=
1348 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1349 }
1350
1351 /**
1352 * gmc_v9_0_mc_init - initialize the memory controller driver params
1353 *
1354 * @adev: amdgpu_device pointer
1355 *
1356 * Look up the amount of vram, vram width, and decide how to place
1357 * vram and gart within the GPU's physical address space.
1358 * Returns 0 for success.
1359 */
gmc_v9_0_mc_init(struct amdgpu_device * adev)1360 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1361 {
1362 int r;
1363
1364 /* size in MB on si */
1365 adev->gmc.mc_vram_size =
1366 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1367 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1368
1369 if (!(adev->flags & AMD_IS_APU) &&
1370 !adev->gmc.xgmi.connected_to_cpu) {
1371 r = amdgpu_device_resize_fb_bar(adev);
1372 if (r)
1373 return r;
1374 }
1375 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1376 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1377
1378 #ifdef CONFIG_X86_64
1379 /*
1380 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1381 * interface can use VRAM through here as it appears system reserved
1382 * memory in host address space.
1383 *
1384 * For APUs, VRAM is just the stolen system memory and can be accessed
1385 * directly.
1386 *
1387 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1388 */
1389
1390 /* check whether both host-gpu and gpu-gpu xgmi links exist */
1391 if (((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) ||
1392 (adev->gmc.xgmi.supported &&
1393 adev->gmc.xgmi.connected_to_cpu)) {
1394 adev->gmc.aper_base =
1395 adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1396 adev->gmc.xgmi.physical_node_id *
1397 adev->gmc.xgmi.node_segment_size;
1398 adev->gmc.aper_size = adev->gmc.real_vram_size;
1399 }
1400
1401 #endif
1402 /* In case the PCI BAR is larger than the actual amount of vram */
1403 adev->gmc.visible_vram_size = adev->gmc.aper_size;
1404 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1405 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1406
1407 /* set the gart size */
1408 if (amdgpu_gart_size == -1) {
1409 switch (adev->asic_type) {
1410 case CHIP_VEGA10: /* all engines support GPUVM */
1411 case CHIP_VEGA12: /* all engines support GPUVM */
1412 case CHIP_VEGA20:
1413 case CHIP_ARCTURUS:
1414 case CHIP_ALDEBARAN:
1415 default:
1416 adev->gmc.gart_size = 512ULL << 20;
1417 break;
1418 case CHIP_RAVEN: /* DCE SG support */
1419 case CHIP_RENOIR:
1420 adev->gmc.gart_size = 1024ULL << 20;
1421 break;
1422 }
1423 } else {
1424 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1425 }
1426
1427 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1428
1429 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1430
1431 return 0;
1432 }
1433
gmc_v9_0_gart_init(struct amdgpu_device * adev)1434 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1435 {
1436 int r;
1437
1438 if (adev->gart.bo) {
1439 WARN(1, "VEGA10 PCIE GART already initialized\n");
1440 return 0;
1441 }
1442
1443 if (adev->gmc.xgmi.connected_to_cpu) {
1444 adev->gmc.vmid0_page_table_depth = 1;
1445 adev->gmc.vmid0_page_table_block_size = 12;
1446 } else {
1447 adev->gmc.vmid0_page_table_depth = 0;
1448 adev->gmc.vmid0_page_table_block_size = 0;
1449 }
1450
1451 /* Initialize common gart structure */
1452 r = amdgpu_gart_init(adev);
1453 if (r)
1454 return r;
1455 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1456 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1457 AMDGPU_PTE_EXECUTABLE;
1458
1459 r = amdgpu_gart_table_vram_alloc(adev);
1460 if (r)
1461 return r;
1462
1463 if (adev->gmc.xgmi.connected_to_cpu) {
1464 r = amdgpu_gmc_pdb0_alloc(adev);
1465 }
1466
1467 return r;
1468 }
1469
1470 /**
1471 * gmc_v9_0_save_registers - saves regs
1472 *
1473 * @adev: amdgpu_device pointer
1474 *
1475 * This saves potential register values that should be
1476 * restored upon resume
1477 */
gmc_v9_0_save_registers(struct amdgpu_device * adev)1478 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1479 {
1480 if (adev->asic_type == CHIP_RAVEN)
1481 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1482 }
1483
gmc_v9_0_sw_init(void * handle)1484 static int gmc_v9_0_sw_init(void *handle)
1485 {
1486 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1487 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1488
1489 adev->gfxhub.funcs->init(adev);
1490
1491 adev->mmhub.funcs->init(adev);
1492 if (adev->mca.funcs)
1493 adev->mca.funcs->init(adev);
1494
1495 spin_lock_init(&adev->gmc.invalidate_lock);
1496
1497 r = amdgpu_atomfirmware_get_vram_info(adev,
1498 &vram_width, &vram_type, &vram_vendor);
1499 if (amdgpu_sriov_vf(adev))
1500 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1501 * and DF related registers is not readable, seems hardcord is the
1502 * only way to set the correct vram_width
1503 */
1504 adev->gmc.vram_width = 2048;
1505 else if (amdgpu_emu_mode != 1)
1506 adev->gmc.vram_width = vram_width;
1507
1508 if (!adev->gmc.vram_width) {
1509 int chansize, numchan;
1510
1511 /* hbm memory channel size */
1512 if (adev->flags & AMD_IS_APU)
1513 chansize = 64;
1514 else
1515 chansize = 128;
1516
1517 numchan = adev->df.funcs->get_hbm_channel_number(adev);
1518 adev->gmc.vram_width = numchan * chansize;
1519 }
1520
1521 adev->gmc.vram_type = vram_type;
1522 adev->gmc.vram_vendor = vram_vendor;
1523 switch (adev->asic_type) {
1524 case CHIP_RAVEN:
1525 adev->num_vmhubs = 2;
1526
1527 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1528 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1529 } else {
1530 /* vm_size is 128TB + 512GB for legacy 3-level page support */
1531 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1532 adev->gmc.translate_further =
1533 adev->vm_manager.num_level > 1;
1534 }
1535 break;
1536 case CHIP_VEGA10:
1537 case CHIP_VEGA12:
1538 case CHIP_VEGA20:
1539 case CHIP_RENOIR:
1540 case CHIP_ALDEBARAN:
1541 adev->num_vmhubs = 2;
1542
1543
1544 /*
1545 * To fulfill 4-level page support,
1546 * vm size is 256TB (48bit), maximum size of Vega10,
1547 * block size 512 (9bit)
1548 */
1549 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1550 if (amdgpu_sriov_vf(adev))
1551 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1552 else
1553 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1554 break;
1555 case CHIP_ARCTURUS:
1556 adev->num_vmhubs = 3;
1557
1558 /* Keep the vm size same with Vega20 */
1559 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1560 break;
1561 default:
1562 break;
1563 }
1564
1565 /* This interrupt is VMC page fault.*/
1566 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1567 &adev->gmc.vm_fault);
1568 if (r)
1569 return r;
1570
1571 if (adev->asic_type == CHIP_ARCTURUS) {
1572 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1573 &adev->gmc.vm_fault);
1574 if (r)
1575 return r;
1576 }
1577
1578 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1579 &adev->gmc.vm_fault);
1580
1581 if (r)
1582 return r;
1583
1584 if (!amdgpu_sriov_vf(adev) &&
1585 !adev->gmc.xgmi.connected_to_cpu) {
1586 /* interrupt sent to DF. */
1587 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1588 &adev->gmc.ecc_irq);
1589 if (r)
1590 return r;
1591 }
1592
1593 /* Set the internal MC address mask
1594 * This is the max address of the GPU's
1595 * internal address space.
1596 */
1597 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1598
1599 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1600 if (r) {
1601 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1602 return r;
1603 }
1604 adev->need_swiotlb = drm_need_swiotlb(44);
1605
1606 if (adev->gmc.xgmi.supported) {
1607 r = adev->gfxhub.funcs->get_xgmi_info(adev);
1608 if (r)
1609 return r;
1610 }
1611
1612 r = gmc_v9_0_mc_init(adev);
1613 if (r)
1614 return r;
1615
1616 amdgpu_gmc_get_vbios_allocations(adev);
1617
1618 /* Memory manager */
1619 r = amdgpu_bo_init(adev);
1620 if (r)
1621 return r;
1622
1623 r = gmc_v9_0_gart_init(adev);
1624 if (r)
1625 return r;
1626
1627 /*
1628 * number of VMs
1629 * VMID 0 is reserved for System
1630 * amdgpu graphics/compute will use VMIDs 1..n-1
1631 * amdkfd will use VMIDs n..15
1632 *
1633 * The first KFD VMID is 8 for GPUs with graphics, 3 for
1634 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
1635 * for video processing.
1636 */
1637 adev->vm_manager.first_kfd_vmid =
1638 (adev->asic_type == CHIP_ARCTURUS ||
1639 adev->asic_type == CHIP_ALDEBARAN) ? 3 : 8;
1640
1641 amdgpu_vm_manager_init(adev);
1642
1643 gmc_v9_0_save_registers(adev);
1644
1645 return 0;
1646 }
1647
gmc_v9_0_sw_fini(void * handle)1648 static int gmc_v9_0_sw_fini(void *handle)
1649 {
1650 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1651
1652 amdgpu_gmc_ras_fini(adev);
1653 amdgpu_gem_force_release(adev);
1654 amdgpu_vm_manager_fini(adev);
1655 amdgpu_gart_table_vram_free(adev);
1656 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0);
1657 amdgpu_bo_fini(adev);
1658
1659 return 0;
1660 }
1661
gmc_v9_0_init_golden_registers(struct amdgpu_device * adev)1662 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1663 {
1664
1665 switch (adev->asic_type) {
1666 case CHIP_VEGA10:
1667 if (amdgpu_sriov_vf(adev))
1668 break;
1669 fallthrough;
1670 case CHIP_VEGA20:
1671 soc15_program_register_sequence(adev,
1672 golden_settings_mmhub_1_0_0,
1673 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1674 soc15_program_register_sequence(adev,
1675 golden_settings_athub_1_0_0,
1676 ARRAY_SIZE(golden_settings_athub_1_0_0));
1677 break;
1678 case CHIP_VEGA12:
1679 break;
1680 case CHIP_RAVEN:
1681 /* TODO for renoir */
1682 soc15_program_register_sequence(adev,
1683 golden_settings_athub_1_0_0,
1684 ARRAY_SIZE(golden_settings_athub_1_0_0));
1685 break;
1686 default:
1687 break;
1688 }
1689 }
1690
1691 /**
1692 * gmc_v9_0_restore_registers - restores regs
1693 *
1694 * @adev: amdgpu_device pointer
1695 *
1696 * This restores register values, saved at suspend.
1697 */
gmc_v9_0_restore_registers(struct amdgpu_device * adev)1698 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1699 {
1700 if (adev->asic_type == CHIP_RAVEN) {
1701 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
1702 WARN_ON(adev->gmc.sdpif_register !=
1703 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
1704 }
1705 }
1706
1707 /**
1708 * gmc_v9_0_gart_enable - gart enable
1709 *
1710 * @adev: amdgpu_device pointer
1711 */
gmc_v9_0_gart_enable(struct amdgpu_device * adev)1712 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1713 {
1714 int r;
1715
1716 if (adev->gmc.xgmi.connected_to_cpu)
1717 amdgpu_gmc_init_pdb0(adev);
1718
1719 if (adev->gart.bo == NULL) {
1720 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1721 return -EINVAL;
1722 }
1723
1724 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
1725 goto skip_pin_bo;
1726
1727 r = amdgpu_gart_table_vram_pin(adev);
1728 if (r)
1729 return r;
1730
1731 skip_pin_bo:
1732 r = adev->gfxhub.funcs->gart_enable(adev);
1733 if (r)
1734 return r;
1735
1736 r = adev->mmhub.funcs->gart_enable(adev);
1737 if (r)
1738 return r;
1739
1740 DRM_INFO("PCIE GART of %uM enabled.\n",
1741 (unsigned)(adev->gmc.gart_size >> 20));
1742 if (adev->gmc.pdb0_bo)
1743 DRM_INFO("PDB0 located at 0x%016llX\n",
1744 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
1745 DRM_INFO("PTB located at 0x%016llX\n",
1746 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1747
1748 adev->gart.ready = true;
1749 return 0;
1750 }
1751
gmc_v9_0_hw_init(void * handle)1752 static int gmc_v9_0_hw_init(void *handle)
1753 {
1754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1755 bool value;
1756 int r, i;
1757
1758 /* The sequence of these two function calls matters.*/
1759 gmc_v9_0_init_golden_registers(adev);
1760
1761 if (adev->mode_info.num_crtc) {
1762 /* Lockout access through VGA aperture*/
1763 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1764 /* disable VGA render */
1765 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1766 }
1767
1768 if (adev->mmhub.funcs->update_power_gating)
1769 adev->mmhub.funcs->update_power_gating(adev, true);
1770
1771 adev->hdp.funcs->init_registers(adev);
1772
1773 /* After HDP is initialized, flush HDP.*/
1774 adev->hdp.funcs->flush_hdp(adev, NULL);
1775
1776 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1777 value = false;
1778 else
1779 value = true;
1780
1781 if (!amdgpu_sriov_vf(adev)) {
1782 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1783 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1784 }
1785 for (i = 0; i < adev->num_vmhubs; ++i)
1786 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1787
1788 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1789 adev->umc.funcs->init_registers(adev);
1790
1791 r = gmc_v9_0_gart_enable(adev);
1792
1793 return r;
1794 }
1795
1796 /**
1797 * gmc_v9_0_gart_disable - gart disable
1798 *
1799 * @adev: amdgpu_device pointer
1800 *
1801 * This disables all VM page table.
1802 */
gmc_v9_0_gart_disable(struct amdgpu_device * adev)1803 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1804 {
1805 adev->gfxhub.funcs->gart_disable(adev);
1806 adev->mmhub.funcs->gart_disable(adev);
1807 amdgpu_gart_table_vram_unpin(adev);
1808 }
1809
gmc_v9_0_hw_fini(void * handle)1810 static int gmc_v9_0_hw_fini(void *handle)
1811 {
1812 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1813
1814 gmc_v9_0_gart_disable(adev);
1815
1816 if (amdgpu_sriov_vf(adev)) {
1817 /* full access mode, so don't touch any GMC register */
1818 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1819 return 0;
1820 }
1821
1822 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1823
1824 return 0;
1825 }
1826
gmc_v9_0_suspend(void * handle)1827 static int gmc_v9_0_suspend(void *handle)
1828 {
1829 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1830
1831 return gmc_v9_0_hw_fini(adev);
1832 }
1833
gmc_v9_0_resume(void * handle)1834 static int gmc_v9_0_resume(void *handle)
1835 {
1836 int r;
1837 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1838
1839 r = gmc_v9_0_hw_init(adev);
1840 if (r)
1841 return r;
1842
1843 amdgpu_vmid_reset_all(adev);
1844
1845 return 0;
1846 }
1847
gmc_v9_0_is_idle(void * handle)1848 static bool gmc_v9_0_is_idle(void *handle)
1849 {
1850 /* MC is always ready in GMC v9.*/
1851 return true;
1852 }
1853
gmc_v9_0_wait_for_idle(void * handle)1854 static int gmc_v9_0_wait_for_idle(void *handle)
1855 {
1856 /* There is no need to wait for MC idle in GMC v9.*/
1857 return 0;
1858 }
1859
gmc_v9_0_soft_reset(void * handle)1860 static int gmc_v9_0_soft_reset(void *handle)
1861 {
1862 /* XXX for emulation.*/
1863 return 0;
1864 }
1865
gmc_v9_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1866 static int gmc_v9_0_set_clockgating_state(void *handle,
1867 enum amd_clockgating_state state)
1868 {
1869 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1870
1871 adev->mmhub.funcs->set_clockgating(adev, state);
1872
1873 athub_v1_0_set_clockgating(adev, state);
1874
1875 return 0;
1876 }
1877
gmc_v9_0_get_clockgating_state(void * handle,u32 * flags)1878 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1879 {
1880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1881
1882 adev->mmhub.funcs->get_clockgating(adev, flags);
1883
1884 athub_v1_0_get_clockgating(adev, flags);
1885 }
1886
gmc_v9_0_set_powergating_state(void * handle,enum amd_powergating_state state)1887 static int gmc_v9_0_set_powergating_state(void *handle,
1888 enum amd_powergating_state state)
1889 {
1890 return 0;
1891 }
1892
1893 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1894 .name = "gmc_v9_0",
1895 .early_init = gmc_v9_0_early_init,
1896 .late_init = gmc_v9_0_late_init,
1897 .sw_init = gmc_v9_0_sw_init,
1898 .sw_fini = gmc_v9_0_sw_fini,
1899 .hw_init = gmc_v9_0_hw_init,
1900 .hw_fini = gmc_v9_0_hw_fini,
1901 .suspend = gmc_v9_0_suspend,
1902 .resume = gmc_v9_0_resume,
1903 .is_idle = gmc_v9_0_is_idle,
1904 .wait_for_idle = gmc_v9_0_wait_for_idle,
1905 .soft_reset = gmc_v9_0_soft_reset,
1906 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1907 .set_powergating_state = gmc_v9_0_set_powergating_state,
1908 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1909 };
1910
1911 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1912 {
1913 .type = AMD_IP_BLOCK_TYPE_GMC,
1914 .major = 9,
1915 .minor = 0,
1916 .rev = 0,
1917 .funcs = &gmc_v9_0_ip_funcs,
1918 };
1919