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Searched refs:amdgpu_sriov_vf (Results 1 – 25 of 73) sorted by relevance

123

/drivers/gpu/drm/amd/amdgpu/
Dnv.c186 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
722 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
724 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
733 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
743 if (!amdgpu_sriov_vf(adev)) { in nv_set_ip_blocks()
752 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
761 !amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
764 if (!amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
770 if (!amdgpu_sriov_vf(adev)) { in nv_set_ip_blocks()
782 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in nv_set_ip_blocks()
[all …]
Damdgpu_virt.h254 #define amdgpu_sriov_vf(adev) \ macro
264 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
267 (amdgpu_sriov_vf((adev)) && \
271 (amdgpu_sriov_vf((adev)) && \
275 (amdgpu_sriov_vf((adev)) && \
279 (amdgpu_sriov_vf((adev)) && \
Dsoc15.c773 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
815 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
841 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
846 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
852 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { in soc15_set_ip_blocks()
866 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
878 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
888 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
894 if (amdgpu_sriov_vf(adev)) { in soc15_set_ip_blocks()
900 if (!amdgpu_sriov_vf(adev)) in soc15_set_ip_blocks()
[all …]
Dpsp_v11_0_8.c63 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_stop()
94 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_create()
176 if (amdgpu_sriov_vf(adev)) in psp_v11_0_8_ring_get_wptr()
188 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_set_wptr()
Damdgpu_psp.c72 if (amdgpu_sriov_vf(adev)) in psp_check_pmfw_centralized_cstate_management()
261 if (!amdgpu_sriov_vf(adev)) { in psp_sw_init()
267 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { in psp_sw_init()
318 amdgpu_sriov_vf(adev) ? in psp_sw_init()
498 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); in psp_cmd_submit_buf()
556 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_cmd_buf()
618 if (!amdgpu_sriov_vf(psp->adev) && in psp_tmr_init()
629 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; in psp_tmr_init()
657 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) in psp_tmr_load()
677 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_unload_cmd_buf()
[all …]
Dpsp_v3_1.c229 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_create()
291 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
302 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
378 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_get_wptr()
389 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_set_wptr()
Dmmhub_v1_0.c113 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_system_aperture_regs()
159 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_cache_regs()
211 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_disable_identity_aperture()
302 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_update_power_gating()
313 if (amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_enable()
359 if (!amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_disable()
378 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_fault_enable_default()
529 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_clockgating()
554 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_get_clockgating()
Dpsp_v12_0.c265 if (amdgpu_sriov_vf(psp->adev)) { in psp_v12_0_ring_create()
317 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
328 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
395 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_get_wptr()
407 if (amdgpu_sriov_vf(adev)) { in psp_v12_0_ring_set_wptr()
Dgmc_v9_0.c576 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_process_interrupt()
664 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_set_irq_funcs()
705 (!amdgpu_sriov_vf(adev)) && in gmc_v9_0_use_invalidate_semaphore()
769 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v9_0_flush_gpu_tlb()
866 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; in gmc_v9_0_flush_gpu_tlb_pasid()
1305 if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) { in gmc_v9_0_late_init()
1499 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1550 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1584 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_sw_init()
1667 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_init_golden_registers()
[all …]
Dathub_v1_0.c68 if (amdgpu_sriov_vf(adev)) in athub_v1_0_set_clockgating()
93 if (amdgpu_sriov_vf(adev)) in athub_v1_0_get_clockgating()
Damdgpu_device.c1202 if (amdgpu_sriov_vf(adev)) in amdgpu_device_resize_fb_bar()
1277 if (amdgpu_sriov_vf(adev)) in amdgpu_device_need_post()
2145 if (amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_early_init()
2255 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) in amdgpu_device_ip_early_init()
2257 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) in amdgpu_device_ip_early_init()
2299 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_early_init()
2321 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || in amdgpu_device_ip_hw_init_phase1()
2396 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) in amdgpu_device_fw_loading()
2443 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_init()
2464 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_init()
[all …]
Dgmc_v10_0.c129 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
160 if (!amdgpu_sriov_vf(adev)) in gmc_v10_0_process_interrupt()
182 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_set_irq_funcs()
200 (!amdgpu_sriov_vf(adev))); in gmc_v10_0_use_invalidate_semaphore()
330 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v10_0_flush_gpu_tlb()
417 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; in gmc_v10_0_flush_gpu_tlb_pasid()
912 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_sw_init()
1025 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) in gmc_v10_0_gart_enable()
1108 if (amdgpu_sriov_vf(adev)) { in gmc_v10_0_hw_fini()
Dpsp_v13_0.c250 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_stop()
281 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_create()
363 if (amdgpu_sriov_vf(adev)) in psp_v13_0_ring_get_wptr()
375 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_set_wptr()
Dsdma_v5_0.c208 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_init_golden_registers()
251 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12)) in sdma_v5_0_init_microcode()
658 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_ctx_switch_enable()
672 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_ctx_switch_enable()
696 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_enable()
731 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
783 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_0_gfx_resume()
808 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
814 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume()
837 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume()
[all …]
Damdgpu_vf_error.c36 if (!amdgpu_sriov_vf(adev)) in amdgpu_vf_error_put()
57 if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) || in amdgpu_vf_error_trans_all()
Dmmhub_v2_0.c227 if (!amdgpu_sriov_vf(adev)) { in mmhub_v2_0_init_system_aperture_regs()
285 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_init_cache_regs()
346 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_disable_identity_aperture()
482 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_fault_enable_default()
670 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_clockgating()
697 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_get_clockgating()
Damdgpu_virt.c217 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) in amdgpu_virt_alloc_mm_table()
244 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) in amdgpu_virt_free_mm_table()
709 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) in amdgpu_detect_virtualization()
716 if (amdgpu_sriov_vf(adev)) { in amdgpu_detect_virtualization()
754 if (!amdgpu_sriov_vf(adev) || in amdgpu_virt_enable_access_debugfs()
768 if (amdgpu_sriov_vf(adev)) in amdgpu_virt_disable_access_debugfs()
776 if (amdgpu_sriov_vf(adev)) { in amdgpu_virt_get_sriov_vf_mode()
Dpsp_v11_0.c174 if (amdgpu_sriov_vf(adev)) in psp_v11_0_init_microcode()
437 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
448 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
466 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_create()
739 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_get_wptr()
751 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_set_wptr()
Dnavi10_ih.c123 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
133 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
167 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_toggle_ring_interrupts()
283 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_enable_ring()
498 if (amdgpu_sriov_vf(adev)) in navi10_ih_set_rptr()
Dvi.c490 if (amdgpu_sriov_vf(adev)) { in vi_init_golden_registers()
1699 if (amdgpu_sriov_vf(adev)) { in vi_common_early_init()
1711 if (amdgpu_sriov_vf(adev)) in vi_common_late_init()
1721 if (amdgpu_sriov_vf(adev)) in vi_common_sw_init()
1755 if (amdgpu_sriov_vf(adev)) in vi_common_hw_fini()
1999 if (amdgpu_sriov_vf(adev)) in vi_common_set_clockgating_state()
2048 if (amdgpu_sriov_vf(adev)) in vi_common_get_clockgating_state()
2125 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
2133 if (!amdgpu_sriov_vf(adev)) { in vi_set_ip_blocks()
2145 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
[all …]
Dvega10_ih.c111 if (amdgpu_sriov_vf(adev)) { in vega10_ih_toggle_ring_interrupts()
226 if (amdgpu_sriov_vf(adev)) { in vega10_ih_enable_ring()
292 if (!amdgpu_sriov_vf(adev)) in vega10_ih_irq_init()
421 if (amdgpu_sriov_vf(adev)) in vega10_ih_set_rptr()
Dvcn_v2_0.c73 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_early_init()
165 if (!amdgpu_sriov_vf(adev)) in vcn_v2_0_sw_init()
232 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_hw_init()
240 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_hw_init()
333 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_mc_resume()
491 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_disable_clock_gating()
651 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_enable_clock_gating()
705 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_disable_static_power_gating()
754 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_enable_static_power_gating()
1299 if (amdgpu_sriov_vf(adev)) in vcn_v2_0_set_clockgating_state()
[all …]
Dgfxhub_v2_1.c213 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_init_cache_regs()
274 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_disable_identity_aperture()
354 if (amdgpu_sriov_vf(adev)) { in gfxhub_v2_1_gart_enable()
417 if (amdgpu_sriov_vf(adev)) in gfxhub_v2_1_set_fault_enable_default()
Dvega20_ih.c115 if (amdgpu_sriov_vf(adev)) { in vega20_ih_toggle_ring_interrupts()
230 if (amdgpu_sriov_vf(adev)) { in vega20_ih_enable_ring()
343 if (!amdgpu_sriov_vf(adev)) in vega20_ih_irq_init()
473 if (amdgpu_sriov_vf(adev)) in vega20_ih_set_rptr()
Dsdma_v5_2.c177 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID)) in sdma_v5_2_init_microcode()
662 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_2_gfx_resume()
684 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_gfx_resume()
713 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_gfx_resume()
734 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ in sdma_v5_2_gfx_resume()
852 if (amdgpu_sriov_vf(adev)) { in sdma_v5_2_start()
1350 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_hw_fini()
1621 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_set_clockgating_state()
1654 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_get_clockgating_state()

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