| /drivers/clk/ux500/ |
| D | u8500_of_clk.c | 18 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
19 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
20 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
24 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
26 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
27 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
29 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, in ux500_twocell_get()
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| D | clk-sysctrl.c | 38 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_prepare() local
40 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], in clk_sysctrl_prepare()
41 clk->reg_bits[0]); in clk_sysctrl_prepare()
43 if (!ret && clk->enable_delay_us) in clk_sysctrl_prepare()
44 usleep_range(clk->enable_delay_us, clk->enable_delay_us + in clk_sysctrl_prepare()
45 (clk->enable_delay_us >> 2)); in clk_sysctrl_prepare()
52 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_unprepare() local
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) in clk_sysctrl_unprepare()
54 dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n", in clk_sysctrl_unprepare()
61 struct clk_sysctrl *clk = to_clk_sysctrl(hw); in clk_sysctrl_recalc_rate() local
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| /drivers/clk/imx/ |
| D | clk-imx5.c | 128 static struct clk *clk[IMX5_CLK_END]; variable
133 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in mx5_clocks_common_init()
134 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in mx5_clocks_common_init()
135 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in mx5_clocks_common_init()
136 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); in mx5_clocks_common_init()
137 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0); in mx5_clocks_common_init()
139 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, in mx5_clocks_common_init()
141 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); in mx5_clocks_common_init()
142 clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); in mx5_clocks_common_init()
143 clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); in mx5_clocks_common_init()
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| D | clk-vf610.c | 113 static struct clk *clk[VF610_CLK_END]; variable
131 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
134 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
137 if (IS_ERR(clk)) in vf610_get_fixed_clock()
138 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
139 return clk; in vf610_get_fixed_clock()
184 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in vf610_clocks_init()
185 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); in vf610_clocks_init()
186 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); in vf610_clocks_init()
187 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); in vf610_clocks_init()
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| D | clk-imx27.c | 49 static struct clk *clk[IMX27_CLK_MAX]; variable
56 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
57 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
58 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); in _mx27_clocks_init()
59 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); in _mx27_clocks_init()
60 clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx27_clocks_init()
61 clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); in _mx27_clocks_init()
62 …clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY… in _mx27_clocks_init()
63 …clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_… in _mx27_clocks_init()
64 clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); in _mx27_clocks_init()
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| D | Makefile | 3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-cpu.o
8 mxc-clk-objs += clk-divider-gate.o
9 mxc-clk-objs += clk-fixup-div.o
10 mxc-clk-objs += clk-fixup-mux.o
11 mxc-clk-objs += clk-frac-pll.o
12 mxc-clk-objs += clk-gate2.o
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| D | clk-imx25.c | 74 static struct clk *clk[clk_max]; variable
80 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
81 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
82 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
83 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); in __mx25_clocks_init()
84 …clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)… in __mx25_clocks_init()
85 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
86 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
87 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); in __mx25_clocks_init()
88 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
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| D | clk-imx35.c | 83 static struct clk *clk[clk_max]; variable
107 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
108 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx35_clocks_init()
109 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
110 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
112 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
115 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); in _mx35_clocks_init()
117 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); in _mx35_clocks_init()
119 if (clk_get_rate(clk[arm]) > 400000000) in _mx35_clocks_init()
130 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); in _mx35_clocks_init()
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| D | clk-scu.c | 88 u8 clk; member
93 u8 clk; member
129 u8 clk; member
147 u8 clk; member
164 u8 clk; member
230 struct clk_scu *clk = to_clk_scu(hw); in clk_scu_recalc_rate() local
240 msg.data.req.resource = cpu_to_le16(clk->rsrc_id); in clk_scu_recalc_rate()
241 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
274 struct clk_scu *clk = to_clk_scu(hw); in clk_scu_atf_set_cpu_rate() local
278 if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53) in clk_scu_atf_set_cpu_rate()
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| D | clk-imx31.c | 51 static struct clk *clk[clk_max]; variable
56 clk[dummy] = imx_clk_fixed("dummy", 0); in _mx31_clocks_init()
57 clk[ckih] = imx_clk_fixed("ckih", fref); in _mx31_clocks_init()
58 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx31_clocks_init()
59 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
60 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
61 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); in _mx31_clocks_init()
62 …clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_… in _mx31_clocks_init()
63 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); in _mx31_clocks_init()
64 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
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| /drivers/sh/clk/ |
| D | cpg.c | 19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
32 iowrite8(value, clk->mapped_reg); in sh_clk_write()
33 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_write()
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| D | core.c | 39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, in clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, in clk_rate_table_round()
149 if (clk->nr_freqs < 1) in clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, in clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), in clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, in clk_rate_mult_range_round() argument
188 .arg = clk_get_parent(clk), in clk_rate_mult_range_round()
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| /drivers/clk/mmp/ |
| D | clk-mmp2.c | 79 struct clk *clk; in mmp2_clk_init() local
80 struct clk *vctcxo; in mmp2_clk_init()
103 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in mmp2_clk_init()
104 clk_register_clkdev(clk, "clk32", NULL); in mmp2_clk_init()
109 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000); in mmp2_clk_init()
110 clk_register_clkdev(clk, "pll1", NULL); in mmp2_clk_init()
112 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000); in mmp2_clk_init()
113 clk_register_clkdev(clk, "usb_pll", NULL); in mmp2_clk_init()
115 clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000); in mmp2_clk_init()
116 clk_register_clkdev(clk, "pll2", NULL); in mmp2_clk_init()
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| D | clk-pxa168.c | 72 struct clk *clk; in pxa168_clk_init() local
73 struct clk *uart_pll; in pxa168_clk_init()
96 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in pxa168_clk_init()
97 clk_register_clkdev(clk, "clk32", NULL); in pxa168_clk_init()
99 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); in pxa168_clk_init()
100 clk_register_clkdev(clk, "vctcxo", NULL); in pxa168_clk_init()
102 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa168_clk_init()
103 clk_register_clkdev(clk, "pll1", NULL); in pxa168_clk_init()
105 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa168_clk_init()
107 clk_register_clkdev(clk, "pll1_2", NULL); in pxa168_clk_init()
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| D | clk-pxa910.c | 70 struct clk *clk; in pxa910_clk_init() local
71 struct clk *uart_pll; in pxa910_clk_init()
101 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in pxa910_clk_init()
102 clk_register_clkdev(clk, "clk32", NULL); in pxa910_clk_init()
104 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); in pxa910_clk_init()
105 clk_register_clkdev(clk, "vctcxo", NULL); in pxa910_clk_init()
107 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa910_clk_init()
108 clk_register_clkdev(clk, "pll1", NULL); in pxa910_clk_init()
110 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", in pxa910_clk_init()
112 clk_register_clkdev(clk, "pll1_2", NULL); in pxa910_clk_init()
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| /drivers/clk/spear/ |
| D | spear3xx_clock.c | 143 struct clk *clk; in spear300_clk_init() local
145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
147 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
151 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
155 clk_register_clkdev(clk, NULL, "70000000.sdhci"); in spear300_clk_init()
157 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
159 clk_register_clkdev(clk, NULL, "a9000000.gpio"); in spear300_clk_init()
161 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
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| D | spear1310_clock.c | 388 struct clk *clk, *clk1; in spear1310_clk_init() local
390 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1310_clk_init()
391 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1310_clk_init()
393 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); in spear1310_clk_init()
394 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1310_clk_init()
396 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); in spear1310_clk_init()
397 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1310_clk_init()
399 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); in spear1310_clk_init()
400 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1310_clk_init()
402 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, in spear1310_clk_init()
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| D | spear1340_clock.c | 445 struct clk *clk, *clk1; in spear1340_clk_init() local
447 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1340_clk_init()
448 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1340_clk_init()
450 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); in spear1340_clk_init()
451 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1340_clk_init()
453 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); in spear1340_clk_init()
454 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1340_clk_init()
456 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); in spear1340_clk_init()
457 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1340_clk_init()
459 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, in spear1340_clk_init()
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| D | spear6xx_clock.c | 118 struct clk *clk, *clk1; in spear6xx_clk_init() local
120 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear6xx_clk_init()
121 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear6xx_clk_init()
123 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); in spear6xx_clk_init()
124 clk_register_clkdev(clk, "osc_30m_clk", NULL); in spear6xx_clk_init()
127 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, in spear6xx_clk_init()
129 clk_register_clkdev(clk, NULL, "rtc-spear"); in spear6xx_clk_init()
132 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, in spear6xx_clk_init()
134 clk_register_clkdev(clk, "pll3_clk", NULL); in spear6xx_clk_init()
136 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", in spear6xx_clk_init()
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| /drivers/clk/mediatek/ |
| D | Makefile | 2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
4 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
5 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
6 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
7 obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o
8 obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o
9 obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o
10 obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o
11 obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
12 obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | base.c | 41 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, in nvkm_clk_adjust() argument
44 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust()
79 nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, in nvkm_cstate_valid() argument
82 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_valid()
83 struct nvkm_volt *volt = clk->subdev.device->volt; in nvkm_cstate_valid()
89 switch (clk->boost_mode) { in nvkm_cstate_valid()
91 if (clk->base_khz && freq > clk->base_khz) in nvkm_cstate_valid()
95 if (clk->boost_khz && freq > clk->boost_khz) in nvkm_cstate_valid()
112 nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate, in nvkm_cstate_find_best() argument
115 struct nvkm_device *device = clk->subdev.device; in nvkm_cstate_find_best()
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| D | mcp77.c | 42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
97 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3; in mcp77_clk_read()
100 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); in mcp77_clk_read()
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| D | gm20b.c | 160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp() argument
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
173 gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll) in gm20b_pllg_write_mnp() argument
175 struct nvkm_device *device = clk->base.base.subdev.device; in gm20b_pllg_write_mnp()
179 gk20a_pllg_write_mnp(&clk->base, &pll->base); in gm20b_pllg_write_mnp()
189 gm20b_dvfs_calc_det_coeff(struct gm20b_clk *clk, s32 uv, in gm20b_dvfs_calc_det_coeff() argument
192 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_dvfs_calc_det_coeff()
193 const struct gm20b_clk_dvfs_params *p = clk->dvfs_params; in gm20b_dvfs_calc_det_coeff()
203 dvfs->dfs_ext_cal = DIV_ROUND_CLOSEST(uv - clk->uvdet_offs, in gm20b_dvfs_calc_det_coeff()
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| /drivers/clk/ |
| D | Makefile | 3 obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
4 obj-$(CONFIG_COMMON_CLK) += clk.o
5 obj-$(CONFIG_COMMON_CLK) += clk-divider.o
6 obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
7 obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
8 obj-$(CONFIG_COMMON_CLK) += clk-gate.o
9 obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o
10 obj-$(CONFIG_COMMON_CLK) += clk-mux.o
11 obj-$(CONFIG_COMMON_CLK) += clk-composite.o
12 obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
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| /drivers/clk/ti/ |
| D | autoidle.c | 47 static int _omap2_clk_deny_idle(struct clk_hw_omap *clk) in _omap2_clk_deny_idle() argument
49 if (clk->ops && clk->ops->deny_idle) { in _omap2_clk_deny_idle()
53 clk->autoidle_count++; in _omap2_clk_deny_idle()
54 if (clk->autoidle_count == 1) in _omap2_clk_deny_idle()
55 clk->ops->deny_idle(clk); in _omap2_clk_deny_idle()
62 static int _omap2_clk_allow_idle(struct clk_hw_omap *clk) in _omap2_clk_allow_idle() argument
64 if (clk->ops && clk->ops->allow_idle) { in _omap2_clk_allow_idle()
68 clk->autoidle_count--; in _omap2_clk_allow_idle()
69 if (clk->autoidle_count == 0) in _omap2_clk_allow_idle()
70 clk->ops->allow_idle(clk); in _omap2_clk_allow_idle()
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