Home
last modified time | relevance | path

Searched refs:clk_pol (Results 1 – 15 of 15) sorted by relevance

/drivers/media/platform/sti/c8sectpfe/
Dc8sectpfe-dvb.c82 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
89 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
96 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
/drivers/media/platform/omap3isp/
Domap3isp.h45 unsigned int clk_pol:1; member
Disp.c443 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT; in omap3isp_configure_bridge()
2072 buscfg->bus.parallel.clk_pol = in isp_parse_of_parallel_endpoint()
/drivers/media/dvb-frontends/
Dstv0367.h27 int clk_pol; member
Dmxl692_defs.h471 u8 clk_pol; member
Dlgs8gxx.c518 u8 serial, u8 clk_pol, u8 clk_gated) in lgs8gxx_set_mpeg_mode() argument
530 t |= clk_pol ? TS_CLK_INVERTED : TS_CLK_NORMAL; in lgs8gxx_set_mpeg_mode()
Dstv0367.c986 stv0367ter_set_clk_pol(state, state->config->clk_pol); in stv0367ter_init()
2299 switch (state->config->clk_pol) { in stv0367cab_init()
/drivers/video/fbdev/
Dmx3fb.c126 unsigned clk_pol:1; /* true = rising edge */ member
600 sig->clk_pol << DI_D3_CLK_POL_SHIFT | in sdc_init_panel()
832 sig_cfg.clk_pol = true; in __set_par()
/drivers/gpu/drm/imx/
Dipuv3-crtc.c300 sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags & in ipu_crtc_mode_set_nofb()
/drivers/media/i2c/
Dmt9v032.c332 if (mt9v032->pdata && mt9v032->pdata->clk_pol) { in __mt9v032_set_power()
1039 pdata->clk_pol = !!(endpoint.bus.parallel.flags & in mt9v032_get_pdata()
Dmt9t001.c302 if (pdata->clk_pol) { in mt9t001_s_stream()
/drivers/media/pci/ngene/
Dngene-cards.c368 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
375 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
/drivers/gpu/ipu-v3/
Dipu-di.c617 if (sig->clk_pol) in ipu_di_init_sync_panel()
/drivers/media/pci/cx23885/
Dcx23885-dvb.c839 .clk_pol = 0,
846 .clk_pol = 0,
/drivers/media/pci/ddbridge/
Dddbridge-core.c938 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,
945 .clk_pol = STV0367_CLOCKPOLARITY_DEFAULT,