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Searched refs:clk_type (Results 1 – 25 of 38) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/
Ddm_services_types.h82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ argument
83 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
84 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
85 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
87 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
88 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
89 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
90 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
91 (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
[all …]
Ddm_services.h191 enum dm_pp_clock_type clk_type,
196 enum dm_pp_clock_type clk_type,
201 enum dm_pp_clock_type clk_type,
/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dyellow_carp_ppt.c788 enum smu_clk_type clk_type, in yellow_carp_get_current_clk_freq() argument
793 switch (clk_type) { in yellow_carp_get_current_clk_freq()
817 enum smu_clk_type clk_type, in yellow_carp_get_dpm_level_count() argument
822 switch (clk_type) { in yellow_carp_get_dpm_level_count()
846 enum smu_clk_type clk_type, in yellow_carp_get_dpm_freq_by_index() argument
852 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
855 switch (clk_type) { in yellow_carp_get_dpm_freq_by_index()
890 enum smu_clk_type clk_type) in yellow_carp_clk_dpm_is_enabled() argument
894 switch (clk_type) { in yellow_carp_clk_dpm_is_enabled()
919 enum smu_clk_type clk_type, in yellow_carp_get_dpm_ultimate_freq() argument
[all …]
Dsmu_v13_0.c1009 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v13_0_display_clock_voltage_request() local
1016 switch (clk_type) { in smu_v13_0_display_clock_voltage_request()
1480 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v13_0_get_dpm_ultimate_freq() argument
1487 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v13_0_get_dpm_ultimate_freq()
1488 switch (clk_type) { in smu_v13_0_get_dpm_ultimate_freq()
1516 clk_type); in smu_v13_0_get_dpm_ultimate_freq()
1540 enum smu_clk_type clk_type, in smu_v13_0_set_soft_freq_limited_range() argument
1548 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v13_0_set_soft_freq_limited_range()
1553 clk_type); in smu_v13_0_set_soft_freq_limited_range()
1557 if (clk_type == SMU_GFXCLK) in smu_v13_0_set_soft_freq_limited_range()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c533 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in vangogh_get_dpm_clk_limited() argument
538 if (!clk_table || clk_type >= SMU_CLK_COUNT) in vangogh_get_dpm_clk_limited()
541 switch (clk_type) { in vangogh_get_dpm_clk_limited()
577 enum smu_clk_type clk_type, char *buf) in vangogh_print_legacy_clk_levels() argument
594 switch (clk_type) { in vangogh_print_legacy_clk_levels()
649 switch (clk_type) { in vangogh_print_legacy_clk_levels()
656 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; in vangogh_print_legacy_clk_levels()
657 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); in vangogh_print_legacy_clk_levels()
679 enum smu_clk_type clk_type, char *buf) in vangogh_print_clk_levels() argument
696 switch (clk_type) { in vangogh_print_clk_levels()
[all …]
Dsmu_v11_0.c1089 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request() local
1096 switch (clk_type) { in smu_v11_0_display_clock_voltage_request()
1732 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v11_0_get_dpm_ultimate_freq() argument
1739 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v11_0_get_dpm_ultimate_freq()
1740 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq()
1768 clk_type); in smu_v11_0_get_dpm_ultimate_freq()
1792 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range() argument
1800 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v11_0_set_soft_freq_limited_range()
1805 clk_type); in smu_v11_0_set_soft_freq_limited_range()
1809 if (clk_type == SMU_GFXCLK) in smu_v11_0_set_soft_freq_limited_range()
[all …]
Dcyan_skillfish_ppt.c275 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq() argument
280 switch (clk_type) { in cyan_skillfish_get_current_clk_freq()
306 enum smu_clk_type clk_type, in cyan_skillfish_print_clk_levels() argument
314 switch (clk_type) { in cyan_skillfish_print_clk_levels()
343 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
Dnavi10_ppt.c1194 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table() argument
1202 clk_type); in navi10_get_current_clk_freq_by_table()
1234 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in navi10_is_support_fine_grained_dpm() argument
1242 clk_type); in navi10_is_support_fine_grained_dpm()
1265 enum smu_clk_type clk_type, char *buf) in navi10_print_clk_levels() argument
1284 switch (clk_type) { in navi10_print_clk_levels()
1294 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); in navi10_print_clk_levels()
1298 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); in navi10_print_clk_levels()
1302 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { in navi10_print_clk_levels()
1304 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); in navi10_print_clk_levels()
[all …]
Dsienna_cichlid_ppt.c1006 enum smu_clk_type clk_type, in sienna_cichlid_get_current_clk_freq_by_table() argument
1014 clk_type); in sienna_cichlid_get_current_clk_freq_by_table()
1056 …ool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in sienna_cichlid_is_support_fine_grained_dpm() argument
1065 clk_type); in sienna_cichlid_is_support_fine_grained_dpm()
1089 enum smu_clk_type clk_type, char *buf) in sienna_cichlid_print_clk_levels() argument
1110 switch (clk_type) { in sienna_cichlid_print_clk_levels()
1122 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); in sienna_cichlid_print_clk_levels()
1127 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) in sienna_cichlid_print_clk_levels()
1130 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); in sienna_cichlid_print_clk_levels()
1134 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { in sienna_cichlid_print_clk_levels()
[all …]
/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c193 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in renoir_get_dpm_clk_limited() argument
198 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_get_dpm_clk_limited()
201 switch (clk_type) { in renoir_get_dpm_clk_limited()
272 enum smu_clk_type clk_type, in renoir_get_dpm_ultimate_freq() argument
280 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in renoir_get_dpm_ultimate_freq()
281 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
316 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
328 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in renoir_get_dpm_ultimate_freq()
333 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); in renoir_get_dpm_ultimate_freq()
344 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
[all …]
Dsmu_v12_0.c212 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v12_0_set_soft_freq_limited_range() argument
217 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v12_0_set_soft_freq_limited_range()
220 switch (clk_type) { in smu_v12_0_set_soft_freq_limited_range()
/drivers/clk/imx/
Dclk-scu.c31 u8 clk_type; member
50 u8 clk_type; member
241 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
315 msg.clk = clk->clk_type; in clk_scu_set_rate()
333 msg.data.req.clk = clk->clk_type; in clk_scu_get_parent()
360 msg.clk = clk->clk_type; in clk_scu_set_parent()
405 clk->clk_type, true, false); in clk_scu_prepare()
420 clk->clk_type, false, false); in clk_scu_unprepare()
452 u32 rsrc_id, u8 clk_type) in __imx_clk_scu() argument
464 clk->clk_type = clk_type; in __imx_clk_scu()
[all …]
Dclk-scu.h33 int num_parents, u32 rsrc_id, u8 clk_type);
37 u32 rsrc_id, u8 clk_type);
51 u8 clk_type) in imx_clk_scu() argument
53 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
57 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
59 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
/drivers/gpu/drm/amd/pm/swsmu/
Damdgpu_smu.c54 enum smu_clk_type clk_type,
117 enum smu_clk_type clk_type, in smu_set_soft_freq_range() argument
127 clk_type, in smu_set_soft_freq_range()
137 enum smu_clk_type clk_type, in smu_get_dpm_freq_range() argument
150 clk_type, in smu_get_dpm_freq_range()
387 enum smu_clk_type clk_type; in smu_restore_dpm_user_profile() local
389 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { in smu_restore_dpm_user_profile()
394 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && in smu_restore_dpm_user_profile()
395 smu->user_dpm_profile.clk_mask[clk_type]) { in smu_restore_dpm_user_profile()
396 ret = smu_force_smuclk_levels(smu, clk_type, in smu_restore_dpm_user_profile()
[all …]
Dsmu_cmn.h54 enum smu_clk_type clk_type);
/drivers/gpu/drm/amd/pm/inc/
Dsmu_v13_0.h220 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
223 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
227 enum smu_clk_type clk_type,
238 enum smu_clk_type clk_type,
243 enum smu_clk_type clk_type,
247 enum smu_clk_type clk_type,
251 enum smu_clk_type clk_type,
Dsmu_v11_0.h262 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
265 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
269 enum smu_clk_type clk_type,
280 enum smu_clk_type clk_type,
285 enum smu_clk_type clk_type,
289 enum smu_clk_type clk_type,
293 enum smu_clk_type clk_type,
Damdgpu_smu.h611 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
619 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
642 enum smu_clk_type clk_type,
1160 …int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, u…
1166 …int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t m…
1382 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1385 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
Dsmu_v12_0.h58 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c114 enum dm_pp_clock_type clk_type, in get_default_clock_levels() argument
123 switch (clk_type) { in get_default_clock_levels()
297 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type() argument
308 dc_to_pp_clock_type(clk_type), &pp_clks)) { in dm_pp_get_clock_levels_by_type()
310 get_default_clock_levels(clk_type, dc_clks); in dm_pp_get_clock_levels_by_type()
315 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); in dm_pp_get_clock_levels_by_type()
341 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { in dm_pp_get_clock_levels_by_type()
353 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { in dm_pp_get_clock_levels_by_type()
369 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_latency() argument
380 dc_to_pp_clock_type(clk_type), in dm_pp_get_clock_levels_by_type_with_latency()
[all …]
/drivers/phy/
Dphy-xgene.c534 enum clk_type_t clk_type; /* Input clock selection */ member
705 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
718 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
728 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
738 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
759 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
805 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1136 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1236 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1253 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument
[all …]
/drivers/input/
Devdev.c50 enum input_clock_type clk_type; member
147 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
178 enum input_clock_type clk_type; in evdev_set_clk_type() local
183 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
186 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
189 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
195 if (client->clk_type != clk_type) { in evdev_set_clk_type()
196 client->clk_type = clk_type; in evdev_set_clk_type()
260 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c98 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; in dce12_update_clocks()
113 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; in dce12_update_clocks()
/drivers/nfc/s3fwrn5/
Dnci.h44 __u8 clk_type; member
/drivers/gpu/drm/amd/amdgpu/
Datombios_crtc.h41 u32 freq, u8 clk_type, u8 clk_src);

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