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Searched refs:ctrl_base (Results 1 – 25 of 29) sorted by relevance

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/drivers/phy/broadcom/
Dphy-brcm-usb-init.c440 static u32 brcmusb_usb_mdio_read(void __iomem *ctrl_base, u32 reg, int mode) in brcmusb_usb_mdio_read() argument
445 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_read()
447 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_read()
451 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_read()
455 return brcm_usb_readl(USB_CTRL_REG(ctrl_base, MDIO2)) & 0xffff; in brcmusb_usb_mdio_read()
458 static void brcmusb_usb_mdio_write(void __iomem *ctrl_base, u32 reg, in brcmusb_usb_mdio_write() argument
464 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_write()
466 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_write()
471 brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO)); in brcmusb_usb_mdio_write()
476 static void brcmusb_usb_phy_ldo_fix(void __iomem *ctrl_base) in brcmusb_usb_phy_ldo_fix() argument
[all …]
Dphy-brcm-sata.c74 void __iomem *ctrl_base; member
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
431 void __iomem *ctrl_base = brcm_sata_ctrl_base(port); in brcm_ns2_sata_init() local
462 writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1); in brcm_ns2_sata_init()
464 writel(0x0, ctrl_base + PHY_CTRL_1); in brcm_ns2_sata_init()
780 priv->ctrl_base = devm_platform_ioremap_resource_byname(pdev, "phy-ctrl"); in brcm_sata_phy_probe()
781 if (IS_ERR(priv->ctrl_base)) in brcm_sata_phy_probe()
782 return PTR_ERR(priv->ctrl_base); in brcm_sata_phy_probe()
/drivers/fsi/
Dfsi-master-aspeed.c34 static const u32 ctrl_base = 0x80000000; variable
228 opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0); in check_errors()
229 opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0); in check_errors()
230 opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0); in check_errors()
242 ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0, in check_errors()
340 ret = opb_writel(aspeed, ctrl_base + FSI_MCENP0 + (4 * idx), reg); in aspeed_master_link_enable()
344 ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg); in aspeed_master_link_enable()
401 opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); in aspeed_master_init()
406 opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); in aspeed_master_init()
409 opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg); in aspeed_master_init()
[all …]
/drivers/video/fbdev/riva/
Dnv_driver.c319 (volatile U032 __iomem *)(par->ctrl_base + 0x00680000); in riva_common_setup()
321 (volatile U032 __iomem *)(par->ctrl_base + 0x00100000); in riva_common_setup()
323 (volatile U032 __iomem *)(par->ctrl_base + 0x00002000); in riva_common_setup()
325 (volatile U032 __iomem *)(par->ctrl_base + 0x00400000); in riva_common_setup()
327 (volatile U032 __iomem *)(par->ctrl_base + 0x00101000); in riva_common_setup()
329 (volatile U032 __iomem *)(par->ctrl_base + 0x00009000); in riva_common_setup()
331 (volatile U032 __iomem *)(par->ctrl_base + 0x00000000); in riva_common_setup()
333 (volatile U032 __iomem *)(par->ctrl_base + 0x00800000); in riva_common_setup()
334 par->riva.PCIO0 = par->ctrl_base + 0x00601000; in riva_common_setup()
335 par->riva.PDIO0 = par->ctrl_base + 0x00681000; in riva_common_setup()
[all …]
Drivafb.h48 u8 __iomem *ctrl_base; /* virtual control register base addr */ member
/drivers/staging/media/hantro/
Dimx8m_vpu_hw.c33 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
35 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
40 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
42 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
49 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
51 writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
68 writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE); in imx8mq_runtime_resume()
69 writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE); in imx8mq_runtime_resume()
70 writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE); in imx8mq_runtime_resume()
193 vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; in imx8mq_vpu_hw_init()
/drivers/mailbox/
Dmailbox-mpfs.c65 void __iomem *ctrl_base; member
77 status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); in mpfs_mbox_busy()
130 writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET); in mpfs_mbox_send_data()
160 status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); in mpfs_mbox_rx_data()
234 mbox->ctrl_base = devm_platform_get_and_ioremap_resource(pdev, 0, &regs); in mpfs_mbox_probe()
235 if (IS_ERR(mbox->ctrl_base)) in mpfs_mbox_probe()
236 return PTR_ERR(mbox->ctrl_base); in mpfs_mbox_probe()
244 mbox->mbox_base = mbox->ctrl_base + MAILBOX_REG_OFFSET; in mpfs_mbox_probe()
/drivers/usb/musb/
Dmusb_dsps.c173 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable()
199 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable()
269 musb_writel(musb->ctrl_base, wrp->coreintr_set, in dsps_check_status()
311 musb_writel(musb->ctrl_base, wrp->epintr_status, epintr); in dsps_musb_clear_ep_rxintr()
317 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt()
419 glue->regset.base = musb->ctrl_base; in dsps_musb_dbg_init()
440 musb->ctrl_base = reg_base; in dsps_musb_init()
477 musb_writel(musb->ctrl_base, wrp->phy_utmi, val); in dsps_musb_init()
515 void __iomem *ctrl_base = musb->ctrl_base; in dsps_musb_set_mode() local
518 reg = musb_readl(ctrl_base, wrp->mode); in dsps_musb_set_mode()
[all …]
Ddavinci.c83 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); in davinci_musb_enable()
87 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); in davinci_musb_enable()
92 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); in davinci_musb_enable()
101 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, in davinci_musb_enable()
115 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG, in davinci_musb_disable()
119 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0); in davinci_musb_disable()
213 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, in otg_timer()
249 void __iomem *tibase = musb->ctrl_base; in davinci_musb_interrupt()
359 void __iomem *tibase = musb->ctrl_base; in davinci_musb_init()
Dtusb6010.c46 void __iomem *tbase = musb->ctrl_base; in tusb_get_revision()
63 void __iomem *tbase = musb->ctrl_base; in tusb_print_revision()
96 void __iomem *tbase = musb->ctrl_base; in tusb_wbus_quirk()
328 void __iomem *tbase = musb->ctrl_base; in tusb_draw_power()
364 void __iomem *tbase = musb->ctrl_base; in tusb_set_clock_source()
391 void __iomem *tbase = musb->ctrl_base; in tusb_allow_idle()
428 void __iomem *tbase = musb->ctrl_base; in tusb_musb_vbus_status()
553 void __iomem *tbase = musb->ctrl_base; in tusb_musb_set_vbus()
630 void __iomem *tbase = musb->ctrl_base; in tusb_musb_set_mode()
822 void __iomem *tbase = musb->ctrl_base; in tusb_musb_interrupt()
[all …]
Dmusb_cppi41.c359 musb_writel(musb->ctrl_base, USB_CTRL_TX_MODE, new_mode); in cppi41_set_dma_mode()
362 musb_writel(musb->ctrl_base, USB_CTRL_RX_MODE, new_mode); in cppi41_set_dma_mode()
388 musb_writel(musb->ctrl_base, DA8XX_USB_MODE, new_mode); in da8xx_set_dma_mode()
407 musb_writel(controller->controller.musb->ctrl_base, in cppi41_set_autoreq_mode()
439 musb_writel(musb->ctrl_base, in cppi41_configure_channel()
449 musb_writel(musb->ctrl_base, in cppi41_configure_channel()
626 musb_writel(musb->ctrl_base, controller->tdown_reg, in cppi41_dma_channel_abort()
632 musb_writel(musb->ctrl_base, controller->tdown_reg, tdbit); in cppi41_dma_channel_abort()
Dda8xx.c86 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_enable()
105 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_disable()
164 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG, in otg_timer()
225 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_interrupt()
357 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_init()
448 void __iomem *reg_base = musb->ctrl_base; in da8xx_dma_controller_callback()
Dam35x.c83 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable()
103 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable()
152 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, in otg_timer()
200 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt()
333 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_init()
Dtusb6010_omap.c585 void __iomem *tbase = musb->ctrl_base; in tusb_dma_controller_create()
591 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); in tusb_dma_controller_create()
592 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); in tusb_dma_controller_create()
604 tusb_dma->tbase = musb->ctrl_base; in tusb_dma_controller_create()
Dcppi_dma.c601 cppi_rndis_update(tx, 0, musb->ctrl_base, rndis); in cppi_next_tx_segment()
770 void __iomem *tibase = musb->ctrl_base; in cppi_next_rx_segment()
811 cppi_rndis_update(rx, 1, musb->ctrl_base, is_rndis); in cppi_next_rx_segment()
1155 tibase = musb->ctrl_base; in cppi_interrupt()
/drivers/leds/
Dleds-sc27xx-bltc.c90 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_enable() local
102 return regmap_update_bits(regmap, ctrl_base, in sc27xx_led_enable()
110 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_disable() local
113 return regmap_update_bits(regmap, ctrl_base, in sc27xx_led_disable()
151 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_pattern_clear() local
161 err = regmap_update_bits(regmap, ctrl_base, in sc27xx_led_pattern_clear()
177 u32 ctrl_base = leds->priv->base + SC27XX_LEDS_CTRL; in sc27xx_led_pattern_set() local
229 err = regmap_update_bits(regmap, ctrl_base, in sc27xx_led_pattern_set()
/drivers/spi/
Dspi-ti-qspi.c48 struct regmap *ctrl_base; member
534 if (qspi->ctrl_base) { in ti_qspi_enable_memory_map()
535 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_enable_memory_map()
548 if (qspi->ctrl_base) in ti_qspi_disable_memory_map()
549 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_disable_memory_map()
827 qspi->ctrl_base = in ti_qspi_probe()
830 if (IS_ERR(qspi->ctrl_base)) { in ti_qspi_probe()
831 ret = PTR_ERR(qspi->ctrl_base); in ti_qspi_probe()
/drivers/dma/
Ddma-jz4780.c150 void __iomem *ctrl_base; member
197 return readl(jzdma->ctrl_base + reg); in jz4780_dma_ctrl_readl()
203 writel(val, jzdma->ctrl_base + reg); in jz4780_dma_ctrl_writel()
868 jzdma->ctrl_base = devm_ioremap_resource(dev, res); in jz4780_dma_probe()
869 if (IS_ERR(jzdma->ctrl_base)) in jz4780_dma_probe()
870 return PTR_ERR(jzdma->ctrl_base); in jz4780_dma_probe()
877 jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET; in jz4780_dma_probe()
Dfsl-qdma.c210 void __iomem *ctrl_base; member
587 void __iomem *block, *ctrl = fsl_qdma->ctrl_base; in fsl_qdma_halt()
769 void __iomem *block, *ctrl = fsl_qdma->ctrl_base; in fsl_qdma_queue_handler()
874 void __iomem *block, *ctrl = fsl_qdma->ctrl_base; in fsl_qdma_reg_init()
1187 fsl_qdma->ctrl_base = devm_ioremap_resource(&pdev->dev, res); in fsl_qdma_probe()
1188 if (IS_ERR(fsl_qdma->ctrl_base)) in fsl_qdma_probe()
1189 return PTR_ERR(fsl_qdma->ctrl_base); in fsl_qdma_probe()
/drivers/clk/samsung/
Dclk-cpu.c369 base = cpuclk->ctrl_base; in exynos_cpuclk_notifier_cb()
392 base = cpuclk->ctrl_base; in exynos5433_cpuclk_notifier_cb()
433 cpuclk->ctrl_base = ctx->reg_base + offset; in exynos_register_cpu_clock()
Dclk-cpu.h50 void __iomem *ctrl_base; member
/drivers/perf/
Darm-cci.c101 void __iomem *ctrl_base; member
375 rev = readl_relaxed(cci_pmu->ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK; in probe_cci400_revision()
673 val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) | CCI_PMCR_CEN; in __cci_pmu_enable_nosync()
674 writel(val, cci_pmu->ctrl_base + CCI_PMCR); in __cci_pmu_enable_nosync()
690 val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN; in __cci_pmu_disable()
691 writel(val, cci_pmu->ctrl_base + CCI_PMCR); in __cci_pmu_disable()
795 return (readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & in pmu_get_max_counters()
1608 cci_pmu->ctrl_base = *(void __iomem **)dev->platform_data; in cci_pmu_alloc()
/drivers/gpu/drm/msm/dsi/
Ddsi_host.c105 void __iomem *ctrl_base; member
195 return msm_readl(msm_host->ctrl_base + reg); in dsi_read()
199 msm_writel(data, msm_host->ctrl_base + reg); in dsi_write()
228 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); in dsi_get_config()
1579 if (!msm_host->ctrl_base) in dsi_host_irq()
1863 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", "DSI CTRL", &msm_host->ctrl_size); in msm_dsi_host_init()
1864 if (IS_ERR(msm_host->ctrl_base)) { in msm_dsi_host_init()
1866 ret = PTR_ERR(msm_host->ctrl_base); in msm_dsi_host_init()
1887 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; in msm_dsi_host_init()
2544 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); in msm_dsi_host_snapshot()
/drivers/net/ethernet/ti/
Ddavinci_emac.c317 void __iomem *ctrl_base; member
363 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
364 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
1845 priv->ctrl_base = in davinci_emac_probe()
1847 if (IS_ERR(priv->ctrl_base)) { in davinci_emac_probe()
1848 rc = PTR_ERR(priv->ctrl_base); in davinci_emac_probe()
1852 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; in davinci_emac_probe()
/drivers/net/ethernet/hisilicon/
Dhix5hd2_gmac.c249 void __iomem *ctrl_base; member
315 writel_relaxed(val, priv->ctrl_base); in hix5hd2_config_port()
1126 priv->ctrl_base = devm_platform_ioremap_resource(pdev, 1); in hix5hd2_dev_probe()
1127 if (IS_ERR(priv->ctrl_base)) { in hix5hd2_dev_probe()
1128 ret = PTR_ERR(priv->ctrl_base); in hix5hd2_dev_probe()

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