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Searched refs:dpll_hw_state (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dpll.c788 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
792 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
794 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
862 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
867 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
918 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
1048 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1049 crtc_state->dpll_hw_state.fp0 = fp; in ilk_compute_dpll()
1050 crtc_state->dpll_hw_state.fp1 = fp2; in ilk_compute_dpll()
1062 memset(&crtc_state->dpll_hw_state, 0, in ilk_crtc_compute_clock()
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Dintel_dpll_mgr.c531 &crtc_state->dpll_hw_state, in ibx_get_dpll()
541 pll, &crtc_state->dpll_hw_state); in ibx_get_dpll()
907 crtc_state->dpll_hw_state.wrpll = val; in hsw_ddi_wrpll_get_dpll()
910 &crtc_state->dpll_hw_state, in hsw_ddi_wrpll_get_dpll()
1026 crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | in hsw_ddi_spll_get_dpll()
1029 return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, in hsw_ddi_spll_get_dpll()
1065 memset(&crtc_state->dpll_hw_state, 0, in hsw_get_dpll()
1066 sizeof(crtc_state->dpll_hw_state)); in hsw_get_dpll()
1081 pll, &crtc_state->dpll_hw_state); in hsw_get_dpll()
1600 memset(&crtc_state->dpll_hw_state, 0, in skl_ddi_hdmi_pll_dividers()
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Dintel_display.c3831 crtc_state->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
3833 crtc_state->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
4817 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
4845 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
4978 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
4991 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, in i9xx_get_pipe_config()
4994 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
4996 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
5000 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
5970 &pipe_config->dpll_hw_state); in ilk_get_pipe_config()
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Dintel_display_types.h1038 struct intel_dpll_hw_state dpll_hw_state; member
Dintel_ddi.c3708 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()
3777 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()