| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dpp.h | 32 struct dpp { struct
131 struct dpp *dpp_base, const struct pwl_params *params);
133 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
136 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
140 struct dpp *dpp_base,
143 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
145 void (*dpp_reset)(struct dpp *dpp);
147 void (*dpp_set_scaler)(struct dpp *dpp,
151 struct dpp *dpp,
156 struct dpp *dpp,
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dpp_cm.c | 43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
92 struct dcn10_dpp *dpp, in program_gamut_remap() argument
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
129 dpp->base.ctx, in program_gamut_remap()
139 dpp->base.ctx, in program_gamut_remap()
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| D | dcn10_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state()
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state() local
123 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp) in dpp_set_gamut_remap_bypass() argument
133 struct dpp *dpp, in dpp1_get_optimal_number_of_taps() argument
139 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && in dpp1_get_optimal_number_of_taps()
145 dpp->ctx->dc->debug.max_downscale_src_width != 0 && in dpp1_get_optimal_number_of_taps()
146 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp1_get_optimal_number_of_taps()
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| D | dcn10_dpp_dscl.c | 43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
89 struct dcn10_dpp *dpp, in dpp1_dscl_set_overscan() argument
117 struct dcn10_dpp *dpp, const struct scaler_data *data) in dpp1_dscl_set_otg_blank() argument
168 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode()
202 struct dpp *dpp_base, in dpp1_power_on_dscl()
205 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl() local
207 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { in dpp1_power_on_dscl()
216 struct dcn10_dpp *dpp, in dpp1_dscl_set_lb() argument
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| D | dcn10_hw_sequencer.c | 294 struct dpp *dpp = pool->dpps[i]; in dcn10_log_hw_state() local
297 dpp->funcs->dpp_read_state(dpp, &s); in dcn10_log_hw_state()
304 dpp->inst, in dcn10_log_hw_state()
1108 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn10_plane_atomic_disconnect()
1148 struct dpp *dpp, in dcn10_plane_atomic_power_down() argument
1159 hws->funcs.dpp_pg_control(hws, dpp->inst, false); in dcn10_plane_atomic_power_down()
1164 dpp->funcs->dpp_reset(dpp); in dcn10_plane_atomic_power_down()
1179 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn10_plane_atomic_disable() local
1186 dpp->funcs->dpp_dppclk_control(dpp, false, false); in dcn10_plane_atomic_disable()
1197 pipe_ctx->plane_res.dpp, in dcn10_plane_atomic_disable()
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| D | dcn10_resource.c | 635 static void dcn10_dpp_destroy(struct dpp **dpp) in dcn10_dpp_destroy() argument
637 kfree(TO_DCN10_DPP(*dpp)); in dcn10_dpp_destroy()
638 *dpp = NULL; in dcn10_dpp_destroy()
641 static struct dpp *dcn10_dpp_create( in dcn10_dpp_create()
645 struct dcn10_dpp *dpp = in dcn10_dpp_create() local
648 if (!dpp) in dcn10_dpp_create()
651 dpp1_construct(dpp, ctx, inst, in dcn10_dpp_create()
653 return &dpp->base; in dcn10_dpp_create()
1174 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1431 dc->caps.color.dpp.dcn_arch = 1; in dcn10_resource_construct()
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| D | dcn10_dpp.h | 30 #define TO_DCN10_DPP(dpp)\ argument
31 container_of(dpp, struct dcn10_dpp, base)
1353 struct dpp base;
1378 struct dpp *dpp_base,
1382 struct dpp *dpp_base,
1389 struct dpp *dpp_base,
1404 struct dpp *dpp_base,
1408 struct dpp *dpp_base,
1412 struct dpp *dpp_base,
1416 struct dpp *dpp_base,
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| D | dcn10_hw_sequencer_debug.c | 342 struct dpp *dpp = pool->dpps[i]; in dcn10_get_cm_states() local
345 dpp->funcs->dpp_read_state(dpp, &s); in dcn10_get_cm_states()
352 dpp->inst, s.igam_input_format, in dcn10_get_cm_states()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dpp_cm.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 struct dpp *dpp_base) in dpp3_enable_cm_block()
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block() local
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current()
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current() local
84 struct dpp *dpp_base, in dpp3_program_gammcor_lut()
90 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut() local
133 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut()
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| D | dcn30_dpp.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 void dpp30_read_state(struct dpp *dpp_base, in dpp30_read_state()
47 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp30_read_state() local
56 struct dpp *dpp_base, in dpp3_program_post_csc()
61 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc() local
101 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc()
102 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; in dpp3_program_post_csc()
103 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; in dpp3_program_post_csc()
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| D | dcn30_dpp.h | 30 #define TO_DCN30_DPP(dpp)\ argument
31 container_of(dpp, struct dcn3_dpp, base)
559 struct dpp base;
585 struct dpp *dpp_base, const struct pwl_params *params);
588 struct dpp *dpp_base,
592 struct dpp *dpp_base,
596 struct dpp *dpp_base,
600 struct dpp *dpp_base,
603 void dpp3_set_pre_degam(struct dpp *dpp_base,
607 struct dpp *dpp_base,
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| D | dcn30_resource.c | 878 void dcn30_dpp_destroy(struct dpp **dpp) in dcn30_dpp_destroy() argument
880 kfree(TO_DCN20_DPP(*dpp)); in dcn30_dpp_destroy()
881 *dpp = NULL; in dcn30_dpp_destroy()
884 static struct dpp *dcn30_dpp_create( in dcn30_dpp_create()
888 struct dcn3_dpp *dpp = in dcn30_dpp_create() local
891 if (!dpp) in dcn30_dpp_create()
894 if (dpp3_construct(dpp, ctx, inst, in dcn30_dpp_create()
896 return &dpp->base; in dcn30_dpp_create()
899 kfree(dpp); in dcn30_dpp_create()
1776 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dpp_cm.c | 37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 struct dpp *dpp_base) in dpp2_enable_cm_block()
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block() local
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse()
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse() local
86 struct dpp *dpp_base, in dpp2_program_degamma_lut()
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut() local
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl()
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| D | dcn20_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state()
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state() local
76 struct dpp *dpp_base, in dpp2_power_on_obuf()
79 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf() local
91 struct dpp *dpp_base, in dpp2_dummy_program_input_lut()
96 struct dpp *dpp_base, in dpp2_cnv_setup()
103 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup() local
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| D | dcn20_dpp.h | 30 #define TO_DCN20_DPP(dpp)\ argument
31 container_of(dpp, struct dcn20_dpp, base)
679 struct dpp base;
709 void dpp20_read_state(struct dpp *dpp_base,
713 struct dpp *dpp_base,
717 struct dpp *dpp_base,
721 struct dpp *dpp_base,
725 struct dpp *dpp_base,
731 struct dpp *dpp_base, const struct pwl_params *params);
734 struct dpp *dpp_base,
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| D | dcn20_hwseq.c | 571 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable() local
585 dpp->funcs->dpp_dppclk_control(dpp, false, false); in dcn20_plane_atomic_disable()
590 pipe_ctx->plane_res.dpp, in dcn20_plane_atomic_disable()
835 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_blend_lut()
857 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_shaper_3dlut()
888 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_input_transfer_func()
1068 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); in dcn20_power_on_plane()
1328 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp in dcn20_detect_pipe_changes()
1406 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_update_dchubp_dpp() local
1411 dpp->funcs->dpp_dppclk_control(dpp, false, true); in dcn20_update_dchubp_dpp()
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| D | dcn20_resource.h | 73 void dcn20_dpp_destroy(struct dpp **dpp);
75 struct dpp *dcn20_dpp_create(
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| D | dcn20_resource.c | 1098 void dcn20_dpp_destroy(struct dpp **dpp) in dcn20_dpp_destroy() argument
1100 kfree(TO_DCN20_DPP(*dpp)); in dcn20_dpp_destroy()
1101 *dpp = NULL; in dcn20_dpp_destroy()
1104 struct dpp *dcn20_dpp_create( in dcn20_dpp_create()
1108 struct dcn20_dpp *dpp = in dcn20_dpp_create() local
1111 if (!dpp) in dcn20_dpp_create()
1114 if (dpp2_construct(dpp, ctx, inst, in dcn20_dpp_create()
1116 return &dpp->base; in dcn20_dpp_create()
1119 kfree(dpp); in dcn20_dpp_create()
1882 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 631 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn303_dpp_create()
633 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); in dcn303_dpp_create() local
635 if (!dpp) in dcn303_dpp_create()
638 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
639 return &dpp->base; in dcn303_dpp_create()
642 kfree(dpp); in dcn303_dpp_create()
1470 dc->caps.color.dpp.dcn_arch = 1; in dcn303_resource_construct()
1471 dc->caps.color.dpp.input_lut_shared = 0; in dcn303_resource_construct()
1472 dc->caps.color.dpp.icsc = 1; in dcn303_resource_construct()
1473 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn303_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 672 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn302_dpp_create()
674 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); in dcn302_dpp_create() local
676 if (!dpp) in dcn302_dpp_create()
679 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
680 return &dpp->base; in dcn302_dpp_create()
683 kfree(dpp); in dcn302_dpp_create()
1527 dc->caps.color.dpp.dcn_arch = 1; in dcn302_resource_construct()
1528 dc->caps.color.dpp.input_lut_shared = 0; in dcn302_resource_construct()
1529 dc->caps.color.dpp.icsc = 1; in dcn302_resource_construct()
1530 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn302_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 897 void dcn301_dpp_destroy(struct dpp **dpp) in dcn301_dpp_destroy() argument
899 kfree(TO_DCN20_DPP(*dpp)); in dcn301_dpp_destroy()
900 *dpp = NULL; in dcn301_dpp_destroy()
903 struct dpp *dcn301_dpp_create( in dcn301_dpp_create()
907 struct dcn3_dpp *dpp = in dcn301_dpp_create() local
910 if (!dpp) in dcn301_dpp_create()
913 if (dpp3_construct(dpp, ctx, inst, in dcn301_dpp_create()
915 return &dpp->base; in dcn301_dpp_create()
918 kfree(dpp); in dcn301_dpp_create()
1786 dc->caps.color.dpp.dcn_arch = 1; in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 983 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
985 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
986 *dpp = NULL; in dcn31_dpp_destroy()
989 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
993 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
996 if (!dpp) in dcn31_dpp_create()
999 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
1001 return &dpp->base; in dcn31_dpp_create()
1004 kfree(dpp); in dcn31_dpp_create()
2021 dc->caps.color.dpp.dcn_arch = 1; in dcn31_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 730 static struct dpp *dcn21_dpp_create( in dcn21_dpp_create()
734 struct dcn20_dpp *dpp = in dcn21_dpp_create() local
737 if (!dpp) in dcn21_dpp_create()
740 if (dpp2_construct(dpp, ctx, inst, in dcn21_dpp_create()
742 return &dpp->base; in dcn21_dpp_create()
745 kfree(dpp); in dcn21_dpp_create()
1998 dc->caps.color.dpp.dcn_arch = 1; in dcn21_resource_construct()
1999 dc->caps.color.dpp.input_lut_shared = 0; in dcn21_resource_construct()
2000 dc->caps.color.dpp.icsc = 1; in dcn21_resource_construct()
2001 dc->caps.color.dpp.dgam_ram = 1; in dcn21_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer_private.h | 64 struct dpp;
110 struct dpp *dpp,
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| D | core_types.h | 214 struct dpp *dpps[MAX_PIPES];
319 struct dpp *dpp; member
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