| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
110 int dpp_inst, dppclk_khz, prev_dppclk_khz; in dcn20_update_clocks_update_dpp_dto() local
116 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
120 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
129 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dentist()
287 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn2_update_clocks()
288 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in dcn2_update_clocks()
290 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; in dcn2_update_clocks()
302 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dppclk_khz; in dcn2_update_clocks()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 109 int dpp_inst, dppclk_khz, prev_dppclk_khz; in rn_update_clocks_update_dpp_dto() local
115 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; in rn_update_clocks_update_dpp_dto()
119 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in rn_update_clocks_update_dpp_dto()
121 clk_mgr->dccg, dpp_inst, dppclk_khz); in rn_update_clocks_update_dpp_dto()
181 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0) in rn_update_clocks()
182 new_clocks->dppclk_khz = 100000; in rn_update_clocks()
188 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) { in rn_update_clocks()
189 new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz; in rn_update_clocks()
193 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { in rn_update_clocks()
194 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) in rn_update_clocks()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 205 if (new_clocks->dppclk_khz < 100000) in dcn31_update_clocks()
206 new_clocks->dppclk_khz = 100000; in dcn31_update_clocks()
209 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn31_update_clocks()
210 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in dcn31_update_clocks()
212 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn31_update_clocks()
229 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); in dcn31_update_clocks()
233 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); in dcn31_update_clocks()
244 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; in dcn31_update_clocks()
303 else if (a->dppclk_khz != b->dppclk_khz) in dcn31_are_clock_states_equal()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 152 if (new_clocks->dppclk_khz < 100000) in vg_update_clocks()
153 new_clocks->dppclk_khz = 100000; in vg_update_clocks()
156 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in vg_update_clocks()
157 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in vg_update_clocks()
159 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in vg_update_clocks()
173 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); in vg_update_clocks()
177 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); in vg_update_clocks()
179 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) in vg_update_clocks()
482 else if (a->dppclk_khz != b->dppclk_khz) in vg_are_clock_states_equal()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 44 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; in rv1_determine_dppclk_threshold()
47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
96 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; in ramp_up_dispclk_with_dpp()
186 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; in ramp_up_dispclk_with_dpp()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 322 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { in dcn3_update_clocks()
323 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) in dcn3_update_clocks()
326 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn3_update_clocks()
327 …30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); in dcn3_update_clocks()
457 else if (a->dppclk_khz != b->dppclk_khz) in dcn3_are_clock_states_equal()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_trace.h | 493 __field(int, dppclk_khz)
512 __entry->dppclk_khz = clk->dppclk_khz;
536 __entry->dppclk_khz,
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_debug.c | 353 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
361 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
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| D | dc.c | 3613 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz; in get_clock_requirements_for_state()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 292 int dppclk_khz; member
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 462 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_log_hw_state()
2618 context->bw_ctx.bw.dcn.clk.dppclk_khz <= in dcn10_update_dchubp_dpp()
2630 pipe_ctx->plane_res.bw.dppclk_khz); in dcn10_update_dchubp_dpp()
2632 dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ? in dcn10_update_dchubp_dpp()
3692 current_clocks->dppclk_khz = clk_khz; in dcn10_set_clock()
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| D | dcn10_hw_sequencer_debug.c | 478 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
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| /drivers/gpu/drm/amd/display/dmub/inc/ |
| D | dmub_cmd.h | 891 uint32_t dppclk_khz; /**< dppclk kHz */ member
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 378 int dppclk_khz; member
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 3104 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dcn20_calculate_dlg_params()
3123 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn20_calculate_dlg_params()
3124 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn20_calculate_dlg_params()
3125 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = in dcn20_calculate_dlg_params()
3131 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dcn20_calculate_dlg_params()
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| D | dcn20_hwseq.c | 1333 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) in dcn20_detect_pipe_changes()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 1191 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / in dcn_validate_bandwidth()
1441 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz); in dcn_find_dcfclk_suits_all()
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