Home
last modified time | relevance | path

Searched refs:hccr (Results 1 – 10 of 10) sorted by relevance

/drivers/scsi/qla2xxx/
Dqla_dbg.c139 wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT); in qla27xx_dump_mpi_ram()
158 wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT); in qla27xx_dump_mpi_ram()
159 rd_reg_dword(&reg->hccr); in qla27xx_dump_mpi_ram()
165 wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT); in qla27xx_dump_mpi_ram()
166 rd_reg_dword(&reg->hccr); in qla27xx_dump_mpi_ram()
225 wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT); in qla24xx_dump_ram()
241 wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT); in qla24xx_dump_ram()
242 rd_reg_dword(&reg->hccr); in qla24xx_dump_ram()
248 wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT); in qla24xx_dump_ram()
249 rd_reg_dword(&reg->hccr); in qla24xx_dump_ram()
[all …]
Dqla_isr.c332 uint16_t hccr; in qla2100_intr_handler() local
351 hccr = rd_reg_word(&reg->hccr); in qla2100_intr_handler()
352 if (qla2x00_check_reg16_for_disconnect(vha, hccr)) in qla2100_intr_handler()
354 if (hccr & HCCR_RISC_PAUSE) { in qla2100_intr_handler()
363 wrt_reg_word(&reg->hccr, HCCR_RESET_RISC); in qla2100_intr_handler()
364 rd_reg_word(&reg->hccr); in qla2100_intr_handler()
373 wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT); in qla2100_intr_handler()
374 rd_reg_word(&reg->hccr); in qla2100_intr_handler()
398 wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT); in qla2100_intr_handler()
399 rd_reg_word(&reg->hccr); in qla2100_intr_handler()
[all …]
Dqla_init.c2903 wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC); in qla2300_pci_config()
2905 if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0) in qla2300_pci_config()
2926 wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC); in qla2300_pci_config()
2928 if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0) in qla2300_pci_config()
3091 wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC); in qla2x00_reset_chip()
3094 if ((rd_reg_word(&reg->hccr) & in qla2x00_reset_chip()
3100 rd_reg_word(&reg->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
3142 wrt_reg_word(&reg->hccr, HCCR_RESET_RISC); in qla2x00_reset_chip()
3143 rd_reg_word(&reg->hccr); /* PCI Posting. */ in qla2x00_reset_chip()
3146 wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC); in qla2x00_reset_chip()
[all …]
Dqla_dbg.h14 __be16 hccr; member
38 __be16 hccr; member
Dqla_mbx.c270 wrt_reg_dword(&reg->isp24.hccr, HCCRX_SET_HOST_INT); in qla2x00_mailbox_command()
272 wrt_reg_word(&reg->isp.hccr, HCCR_SET_HOST_INT); in qla2x00_mailbox_command()
329 wrt_reg_dword(&reg->isp24.hccr, HCCRX_SET_HOST_INT); in qla2x00_mailbox_command()
331 wrt_reg_word(&reg->isp.hccr, HCCR_SET_HOST_INT); in qla2x00_mailbox_command()
419 uint32_t ictrl, host_status, hccr; in qla2x00_mailbox_command() local
430 hccr = rd_reg_dword(&reg->isp24.hccr); in qla2x00_mailbox_command()
436 mb[7], host_status, hccr); in qla2x00_mailbox_command()
5518 wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT); in qla81xx_write_mpi_register()
5532 wrt_reg_dword(&reg->hccr, in qla81xx_write_mpi_register()
5534 rd_reg_dword(&reg->hccr); in qla81xx_write_mpi_register()
Dqla_sup.c2323 wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC); in qla2x00_suspend_hba()
2324 rd_reg_word(&reg->hccr); in qla2x00_suspend_hba()
2327 if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0) in qla2x00_suspend_hba()
Dqla_fw.h1226 __le32 hccr; /* Host command & control register. */ member
Dqla_def.h882 __le16 hccr; /* Host command & control register. */ member
Dqla_iocb.c479 rd_reg_dword_relaxed(&ha->iobase->isp24.hccr); in qla2x00_start_iocbs()
Dqla_os.c7821 stat = rd_reg_word(&reg->hccr); in qla2xxx_pci_mmio_enabled()