| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_hdp.c | 37 if (!adev->hdp.ras_if) { in amdgpu_hdp_ras_late_init()
38 adev->hdp.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); in amdgpu_hdp_ras_late_init()
39 if (!adev->hdp.ras_if) in amdgpu_hdp_ras_late_init()
41 adev->hdp.ras_if->block = AMDGPU_RAS_BLOCK__HDP; in amdgpu_hdp_ras_late_init()
42 adev->hdp.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_hdp_ras_late_init()
43 adev->hdp.ras_if->sub_block_index = 0; in amdgpu_hdp_ras_late_init()
45 ih_info.head = fs_info.head = *adev->hdp.ras_if; in amdgpu_hdp_ras_late_init()
46 r = amdgpu_ras_late_init(adev, adev->hdp.ras_if, in amdgpu_hdp_ras_late_init()
48 if (r || !amdgpu_ras_is_supported(adev, adev->hdp.ras_if->block)) { in amdgpu_hdp_ras_late_init()
49 kfree(adev->hdp.ras_if); in amdgpu_hdp_ras_late_init()
[all …]
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| D | amdgpu_gmc.c | 467 if (adev->hdp.ras_funcs && in amdgpu_gmc_ras_late_init()
468 adev->hdp.ras_funcs->ras_late_init) { in amdgpu_gmc_ras_late_init()
469 r = adev->hdp.ras_funcs->ras_late_init(adev); in amdgpu_gmc_ras_late_init()
512 if (adev->hdp.ras_funcs && in amdgpu_gmc_ras_fini()
513 adev->hdp.ras_funcs->ras_fini) in amdgpu_gmc_ras_fini()
514 adev->hdp.ras_funcs->ras_fini(adev); in amdgpu_gmc_ras_fini()
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| D | soc15.c | 788 adev->hdp.funcs = &hdp_v4_0_funcs; in soc15_set_ip_blocks()
1575 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1592 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1601 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1621 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1622 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
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| D | gmc_v9_0.c | 1244 adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs; in gmc_v9_0_set_hdp_ras_funcs()
1317 if (adev->hdp.ras_funcs && in gmc_v9_0_late_init()
1318 adev->hdp.ras_funcs->reset_ras_error_count) in gmc_v9_0_late_init()
1319 adev->hdp.ras_funcs->reset_ras_error_count(adev); in gmc_v9_0_late_init()
1771 adev->hdp.funcs->init_registers(adev); in gmc_v9_0_hw_init()
1774 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v9_0_hw_init()
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| D | amdgpu_ras.c | 871 if (adev->hdp.ras_funcs && in amdgpu_ras_query_error_status()
872 adev->hdp.ras_funcs->query_ras_error_count) in amdgpu_ras_query_error_status()
873 adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data); in amdgpu_ras_query_error_status()
957 if (adev->hdp.ras_funcs && in amdgpu_ras_reset_error_status()
958 adev->hdp.ras_funcs->reset_ras_error_count) in amdgpu_ras_reset_error_status()
959 adev->hdp.ras_funcs->reset_ras_error_count(adev); in amdgpu_ras_reset_error_status()
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| D | gmc_v10_0.c | 324 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v10_0_flush_gpu_tlb()
1041 adev->hdp.funcs->init_registers(adev); in gmc_v10_0_gart_enable()
1044 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v10_0_gart_enable()
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| D | nv.c | 699 adev->hdp.funcs = &hdp_v5_0_funcs; in nv_set_ip_blocks()
1404 adev->hdp.funcs->update_clock_gating(adev, in nv_common_set_clockgating_state()
1431 adev->hdp.funcs->get_clock_gating_state(adev, flags); in nv_common_get_clockgating_state()
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| D | amdgpu.h | 959 struct amdgpu_hdp hdp; member
1262 …((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->f…
1264 …invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_h…
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| D | psp_v11_0.c | 705 adev->hdp.funcs->flush_hdp(adev, NULL); in psp_v11_0_memory_training()
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| D | sdma_v4_0.c | 894 int mem_space, int hdp, in sdma_v4_0_wait_reg_mem() argument
900 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | in sdma_v4_0_wait_reg_mem()
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| D | gfx_v10_0.c | 6023 adev->hdp.funcs->flush_hdp(adev, NULL); in gfx_v10_0_cp_gfx_load_pfp_microcode()
6101 adev->hdp.funcs->flush_hdp(adev, NULL); in gfx_v10_0_cp_gfx_load_ce_microcode()
6178 adev->hdp.funcs->flush_hdp(adev, NULL); in gfx_v10_0_cp_gfx_load_me_microcode()
6553 adev->hdp.funcs->flush_hdp(adev, NULL); in gfx_v10_0_cp_compute_load_microcode()
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| /drivers/char/ |
| D | hpet.c | 727 static int hpet_is_known(struct hpet_data *hdp) in hpet_is_known() argument
732 if (hpetp->hp_hpet_phys == hdp->hd_phys_address) in hpet_is_known()
835 int hpet_alloc(struct hpet_data *hdp) in hpet_alloc() argument
852 if (hpet_is_known(hdp)) { in hpet_alloc()
858 hpetp = kzalloc(struct_size(hpetp, hp_dev, hdp->hd_nirqs), in hpet_alloc()
865 hpetp->hp_hpet = hdp->hd_address; in hpet_alloc()
866 hpetp->hp_hpet_phys = hdp->hd_phys_address; in hpet_alloc()
868 hpetp->hp_ntimer = hdp->hd_nirqs; in hpet_alloc()
870 for (i = 0; i < hdp->hd_nirqs; i++) in hpet_alloc()
871 hpetp->hp_dev[i].hd_hdwirq = hdp->hd_irq[i]; in hpet_alloc()
[all …]
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| /drivers/video/fbdev/ |
| D | carminefb.c | 64 u32 hdp; member
107 .hdp = 640,
119 .hdp = 800,
133 if (car_modes[i].hdp == var->xres && in carmine_find_mode()
258 width = par->res->hdp * 4 / CARMINE_DISP_WIDTH_UNIT; in carmine_init_display_param()
275 window_size |= par->res->hdp; in carmine_init_display_param()
371 u32 hdp, vdp, htp, hsp, hsw, vtr, vsp, vsw; in set_display_parameters() local
377 hdp = par->res->hdp - 1; in set_display_parameters()
389 (hdp << CARMINE_DISP_HDB_SHIFT) | hdp); in set_display_parameters()
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| /drivers/net/ethernet/ti/ |
| D | davinci_cpdma.c | 110 void __iomem *hdp, *cp, *rxfree; member
393 chan_write(chan, hdp, desc_phys(pool, chan->head)); in cpdma_chan_on()
907 chan->hdp = ctlr->params.rxhdp + offset; in cpdma_chan_create()
915 chan->hdp = ctlr->params.txhdp + offset; in cpdma_chan_create()
997 chan_write(chan, hdp, desc_dma); in __cpdma_chan_submit()
1011 chan_write(chan, hdp, desc_dma); in __cpdma_chan_submit()
1260 chan_write(chan, hdp, desc_phys(pool, chan->head)); in __cpdma_chan_process()
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