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Searched refs:irqmask (Results 1 – 25 of 44) sorted by relevance

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/drivers/gpu/drm/msm/disp/
Dmdp_kms.c24 uint32_t irqmask = mdp_kms->vblank_mask; in update_irq() local
29 irqmask |= irq->irqmask; in update_irq()
31 mdp_kms->funcs->set_irqmask(mdp_kms, irqmask, mdp_kms->cur_irq_mask); in update_irq()
32 mdp_kms->cur_irq_mask = irqmask; in update_irq()
54 if (handler->irqmask & status) { in mdp_dispatch_irqs()
56 handler->irq(handler, handler->irqmask & status); in mdp_dispatch_irqs()
87 void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask) in mdp_irq_wait() argument
92 .irqmask = irqmask, in mdp_irq_wait()
Dmdp_kms.h22 void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask,
64 uint32_t irqmask; member
71 void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask);
/drivers/clocksource/
Dtimer-atmel-st.c21 static u32 irqmask; variable
53 sr &= irqmask; in at91rm9200_timer_interrupt()
108 irqmask = 0; in clkevt32k_shutdown()
109 regmap_write(regmap_st, AT91_ST_IER, irqmask); in clkevt32k_shutdown()
121 irqmask = AT91_ST_ALMS; in clkevt32k_set_oneshot()
123 regmap_write(regmap_st, AT91_ST_IER, irqmask); in clkevt32k_set_oneshot()
132 irqmask = AT91_ST_PITS; in clkevt32k_set_periodic()
134 regmap_write(regmap_st, AT91_ST_IER, irqmask); in clkevt32k_set_periodic()
/drivers/irqchip/
Dirq-i8259.c114 int irqmask = 1 << irq; in i8259A_irq_real() local
118 value = inb(PIC_MASTER_CMD) & irqmask; in i8259A_irq_real()
123 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); in i8259A_irq_real()
136 unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; in mask_and_ack_8259A() local
139 irqmask = 1 << irq; in mask_and_ack_8259A()
156 if (cached_irq_mask & irqmask) in mask_and_ack_8259A()
158 cached_irq_mask |= irqmask; in mask_and_ack_8259A()
191 if (!(spurious_irq_mask & irqmask)) { in mask_and_ack_8259A()
193 spurious_irq_mask |= irqmask; in mask_and_ack_8259A()
/drivers/gpu/drm/omapdrm/
Domap_irq.c14 u32 irqmask; member
23 u32 irqmask = priv->irq_mask; in omap_irq_update() local
28 irqmask |= wait->irqmask; in omap_irq_update()
30 DBG("irqmask=%08x", irqmask); in omap_irq_update()
32 dispc_write_irqenable(priv->dispc, irqmask); in omap_irq_update()
42 u32 irqmask, int count) in omap_irq_wait_init() argument
49 wait->irqmask = irqmask; in omap_irq_wait_init()
241 if (wait->irqmask & irqstatus) in omap_irq_handler()
Domap_irq.h25 u32 irqmask, int count);
/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_irq.c13 void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, in mdp4_set_irqmask() argument
17 irqmask ^ (irqmask & old_irqmask)); in mdp4_set_irqmask()
18 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); in mdp4_set_irqmask()
51 error_handler->irqmask = MDP4_IRQ_PRIMARY_INTF_UDERRUN | in mdp4_irq_postinstall()
Dmdp4_crtc.c562 return mdp4_crtc->vblank.irqmask; in mdp4_crtc_vblank()
647 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma); in mdp4_crtc_init()
650 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma); in mdp4_crtc_init()
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_irq.c15 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, in mdp5_set_irqmask() argument
19 irqmask ^ (irqmask & old_irqmask)); in mdp5_set_irqmask()
20 mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask); in mdp5_set_irqmask()
58 error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN | in mdp5_irq_postinstall()
/drivers/net/wireless/mediatek/mt76/mt7915/
Dpci.c37 mdev->mmio.irqmask &= ~clear; in mt7915_dual_hif_set_irq_mask()
38 mdev->mmio.irqmask |= set; in mt7915_dual_hif_set_irq_mask()
41 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); in mt7915_dual_hif_set_irq_mask()
42 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); in mt7915_dual_hif_set_irq_mask()
107 intr &= dev->mt76.mmio.irqmask; in mt7915_irq_tasklet()
112 intr1 &= dev->mt76.mmio.irqmask; in mt7915_irq_tasklet()
118 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7915_irq_tasklet()
/drivers/gpio/
Dgpio-sa1100.c20 u32 irqmask; member
118 grer = sgc->irqrising & sgc->irqmask; in sa1100_update_edge_regs()
119 gfer = sgc->irqfalling & sgc->irqmask; in sa1100_update_edge_regs()
165 sgc->irqmask &= ~mask; in sa1100_gpio_mask()
175 sgc->irqmask |= mask; in sa1100_gpio_unmask()
/drivers/net/wireless/mediatek/mt76/
Dmmio.c74 dev->mmio.irqmask &= ~clear; in mt76_set_irq_mask()
75 dev->mmio.irqmask |= set; in mt76_set_irq_mask()
77 mt76_mmio_wr(dev, addr, dev->mmio.irqmask); in mt76_set_irq_mask()
Dmt76x02_mmio.c257 intr &= dev->mt76.mmio.irqmask; in mt76x02_irq_handler()
263 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt76x02_irq_handler()
426 u32 mask = dev->mt76.mmio.irqmask; in mt76x02_watchdog_reset()
/drivers/regulator/
Dlp8755.c46 unsigned int irqmask; member
291 && (pchip->irqmask & (0x04 << icnt)) in lp8755_irq_handler()
308 if ((flag1 & 0x01) && (pchip->irqmask & 0x01)) in lp8755_irq_handler()
317 if ((flag1 & 0x02) && (pchip->irqmask & 0x02)) in lp8755_irq_handler()
347 pchip->irqmask = regval; in lp8755_int_config()
/drivers/net/wireless/mediatek/mt76/mt7603/
Dcore.c24 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7603_irq_handler()
26 intr &= dev->mt76.mmio.irqmask; in mt7603_irq_handler()
/drivers/ata/
Dpata_hpt3x2n.c495 u8 irqmask; in hpt3x2n_init_one() local
544 pci_read_config_byte(dev, 0x5A, &irqmask); in hpt3x2n_init_one()
545 irqmask &= ~0x10; in hpt3x2n_init_one()
546 pci_write_config_byte(dev, 0x5a, irqmask); in hpt3x2n_init_one()
Dpata_icside.c67 unsigned int irqmask; member
389 info->irqmask = 1; in pata_icside_register_v5()
450 ec->irqmask = info->irqmask; in pata_icside_add_ports()
Dpata_hpt37x.c826 u8 irqmask; in hpt37x_init_one() local
918 pci_read_config_byte(dev, 0x5A, &irqmask); in hpt37x_init_one()
919 irqmask &= ~0x10; in hpt37x_init_one()
920 pci_write_config_byte(dev, 0x5a, irqmask); in hpt37x_init_one()
/drivers/media/rc/
Dwinbond-cir.c198 u8 irqmask; member
248 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) in wbcir_set_irqmask() argument
250 if (data->irqmask == irqmask) in wbcir_set_irqmask()
254 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); in wbcir_set_irqmask()
255 data->irqmask = irqmask; in wbcir_set_irqmask()
462 status &= data->irqmask; in wbcir_irq_handler()
/drivers/media/pci/tw5864/
Dtw5864-core.c79 tw_writel(TW5864_INTR_ENABLE_L, dev->irqmask & 0xffff); in tw5864_irqmask_apply()
80 tw_writel(TW5864_INTR_ENABLE_H, (dev->irqmask >> 16)); in tw5864_irqmask_apply()
88 dev->irqmask = 0; in tw5864_interrupts_disable()
/drivers/video/fbdev/omap2/omapfb/dss/
Ddispc-compat.h13 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
Ddispc-compat.c631 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, in omap_dispc_wait_for_irq_interruptible_timeout() argument
640 irqmask); in omap_dispc_wait_for_irq_interruptible_timeout()
648 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); in omap_dispc_wait_for_irq_interruptible_timeout()
/drivers/net/wireless/mediatek/mt76/mt7615/
Dmmio.c113 intr &= dev->mt76.mmio.irqmask; in mt7615_irq_tasklet()
116 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7615_irq_tasklet()
/drivers/net/ethernet/nvidia/
Dforcedeth.c783 u32 irqmask; member
3654 if (np->irqmask != NVREG_IRQMASK_CPU) { in nv_change_interrupt_mode()
3655 np->irqmask = NVREG_IRQMASK_CPU; in nv_change_interrupt_mode()
3664 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { in nv_change_interrupt_mode()
3665 np->irqmask = NVREG_IRQMASK_THROUGHPUT; in nv_change_interrupt_mode()
3687 if (!(np->events & np->irqmask)) in nv_nic_irq()
3720 if (!(np->events & np->irqmask)) in nv_nic_irq_optimized()
3749 if (!(events & np->irqmask)) in nv_nic_irq_tx()
3829 np->nic_poll_irq = np->irqmask; in nv_napi_poll()
3843 writel(np->irqmask, base + NvRegIrqMask); in nv_napi_poll()
[all …]
/drivers/net/wireless/mediatek/mt76/mt7921/
Dpci.c55 intr &= dev->mt76.mmio.irqmask; in mt7921_irq_tasklet()
58 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7921_irq_tasklet()

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