1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc.
3 *
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9
10 #include "mt7921.h"
11 #include "mac.h"
12 #include "mcu.h"
13 #include "../trace.h"
14
15 static const struct pci_device_id mt7921_pci_device_table[] = {
16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961) },
17 { },
18 };
19
20 static void
mt7921_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)21 mt7921_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
22 {
23 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
24
25 if (q == MT_RXQ_MAIN)
26 mt7921_irq_enable(dev, MT_INT_RX_DONE_DATA);
27 else if (q == MT_RXQ_MCU_WA)
28 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM2);
29 else
30 mt7921_irq_enable(dev, MT_INT_RX_DONE_WM);
31 }
32
mt7921_irq_handler(int irq,void * dev_instance)33 static irqreturn_t mt7921_irq_handler(int irq, void *dev_instance)
34 {
35 struct mt7921_dev *dev = dev_instance;
36
37 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
38
39 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
40 return IRQ_NONE;
41
42 tasklet_schedule(&dev->irq_tasklet);
43
44 return IRQ_HANDLED;
45 }
46
mt7921_irq_tasklet(unsigned long data)47 static void mt7921_irq_tasklet(unsigned long data)
48 {
49 struct mt7921_dev *dev = (struct mt7921_dev *)data;
50 u32 intr, mask = 0;
51
52 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
53
54 intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA);
55 intr &= dev->mt76.mmio.irqmask;
56 mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr);
57
58 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
59
60 mask |= intr & MT_INT_RX_DONE_ALL;
61 if (intr & MT_INT_TX_DONE_MCU)
62 mask |= MT_INT_TX_DONE_MCU;
63
64 if (intr & MT_INT_MCU_CMD) {
65 u32 intr_sw;
66
67 intr_sw = mt76_rr(dev, MT_MCU_CMD);
68 /* ack MCU2HOST_SW_INT_STA */
69 mt76_wr(dev, MT_MCU_CMD, intr_sw);
70 if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) {
71 mask |= MT_INT_RX_DONE_DATA;
72 intr |= MT_INT_RX_DONE_DATA;
73 }
74 }
75
76 mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0);
77
78 if (intr & MT_INT_TX_DONE_ALL)
79 napi_schedule(&dev->mt76.tx_napi);
80
81 if (intr & MT_INT_RX_DONE_WM)
82 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
83
84 if (intr & MT_INT_RX_DONE_WM2)
85 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
86
87 if (intr & MT_INT_RX_DONE_DATA)
88 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
89 }
90
__mt7921_reg_addr(struct mt7921_dev * dev,u32 addr)91 static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
92 {
93 static const struct {
94 u32 phys;
95 u32 mapped;
96 u32 size;
97 } fixed_map[] = {
98 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
99 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
100 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
101 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
102 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
103 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
104 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
105 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
106 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
107 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
108 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
109 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
110 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
111 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
112 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
113 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
114 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
115 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
116 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
117 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
118 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
119 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
120 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
121 { 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */
122 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
123 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
124 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
125 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
126 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
127 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
128 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
129 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
130 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
131 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
132 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
133 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
134 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
135 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
136 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
137 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
138 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
139 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
140 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
141 };
142 int i;
143
144 if (addr < 0x100000)
145 return addr;
146
147 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
148 u32 ofs;
149
150 if (addr < fixed_map[i].phys)
151 continue;
152
153 ofs = addr - fixed_map[i].phys;
154 if (ofs > fixed_map[i].size)
155 continue;
156
157 return fixed_map[i].mapped + ofs;
158 }
159
160 if ((addr >= 0x18000000 && addr < 0x18c00000) ||
161 (addr >= 0x70000000 && addr < 0x78000000) ||
162 (addr >= 0x7c000000 && addr < 0x7c400000))
163 return mt7921_reg_map_l1(dev, addr);
164
165 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
166 addr);
167
168 return 0;
169 }
170
mt7921_rr(struct mt76_dev * mdev,u32 offset)171 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
172 {
173 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
174 u32 addr = __mt7921_reg_addr(dev, offset);
175
176 return dev->bus_ops->rr(mdev, addr);
177 }
178
mt7921_wr(struct mt76_dev * mdev,u32 offset,u32 val)179 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
180 {
181 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
182 u32 addr = __mt7921_reg_addr(dev, offset);
183
184 dev->bus_ops->wr(mdev, addr, val);
185 }
186
mt7921_rmw(struct mt76_dev * mdev,u32 offset,u32 mask,u32 val)187 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
188 {
189 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
190 u32 addr = __mt7921_reg_addr(dev, offset);
191
192 return dev->bus_ops->rmw(mdev, addr, mask, val);
193 }
194
mt7921_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)195 static int mt7921_pci_probe(struct pci_dev *pdev,
196 const struct pci_device_id *id)
197 {
198 static const struct mt76_driver_ops drv_ops = {
199 /* txwi_size = txd size + txp size */
200 .txwi_size = MT_TXD_SIZE + sizeof(struct mt7921_txp_common),
201 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
202 MT_DRV_AMSDU_OFFLOAD,
203 .survey_flags = SURVEY_INFO_TIME_TX |
204 SURVEY_INFO_TIME_RX |
205 SURVEY_INFO_TIME_BSS_RX,
206 .token_size = MT7921_TOKEN_SIZE,
207 .tx_prepare_skb = mt7921_tx_prepare_skb,
208 .tx_complete_skb = mt7921_tx_complete_skb,
209 .rx_skb = mt7921_queue_rx_skb,
210 .rx_poll_complete = mt7921_rx_poll_complete,
211 .sta_ps = mt7921_sta_ps,
212 .sta_add = mt7921_mac_sta_add,
213 .sta_assoc = mt7921_mac_sta_assoc,
214 .sta_remove = mt7921_mac_sta_remove,
215 .update_survey = mt7921_update_channel,
216 };
217 struct mt76_bus_ops *bus_ops;
218 struct mt7921_dev *dev;
219 struct mt76_dev *mdev;
220 int ret;
221 u16 cmd;
222
223 ret = pcim_enable_device(pdev);
224 if (ret)
225 return ret;
226
227 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
228 if (ret)
229 return ret;
230
231 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
232 if (!(cmd & PCI_COMMAND_MEMORY)) {
233 cmd |= PCI_COMMAND_MEMORY;
234 pci_write_config_word(pdev, PCI_COMMAND, cmd);
235 }
236 pci_set_master(pdev);
237
238 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
239 if (ret < 0)
240 return ret;
241
242 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
243 if (ret)
244 goto err_free_pci_vec;
245
246 mt76_pci_disable_aspm(pdev);
247
248 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7921_ops,
249 &drv_ops);
250 if (!mdev) {
251 ret = -ENOMEM;
252 goto err_free_pci_vec;
253 }
254
255 dev = container_of(mdev, struct mt7921_dev, mt76);
256
257 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
258 tasklet_init(&dev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev);
259
260 dev->bus_ops = dev->mt76.bus;
261 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
262 GFP_KERNEL);
263 if (!bus_ops) {
264 ret = -ENOMEM;
265 goto err_free_dev;
266 }
267
268 bus_ops->rr = mt7921_rr;
269 bus_ops->wr = mt7921_wr;
270 bus_ops->rmw = mt7921_rmw;
271 dev->mt76.bus = bus_ops;
272
273 ret = __mt7921e_mcu_drv_pmctrl(dev);
274 if (ret)
275 goto err_free_dev;
276
277 mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) |
278 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
279 dev_err(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
280
281 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
282
283 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
284
285 ret = devm_request_irq(mdev->dev, pdev->irq, mt7921_irq_handler,
286 IRQF_SHARED, KBUILD_MODNAME, dev);
287 if (ret)
288 goto err_free_dev;
289
290 ret = mt7921_register_device(dev);
291 if (ret)
292 goto err_free_irq;
293
294 return 0;
295
296 err_free_irq:
297 devm_free_irq(&pdev->dev, pdev->irq, dev);
298 err_free_dev:
299 mt76_free_device(&dev->mt76);
300 err_free_pci_vec:
301 pci_free_irq_vectors(pdev);
302
303 return ret;
304 }
305
mt7921_pci_remove(struct pci_dev * pdev)306 static void mt7921_pci_remove(struct pci_dev *pdev)
307 {
308 struct mt76_dev *mdev = pci_get_drvdata(pdev);
309 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
310
311 mt7921_unregister_device(dev);
312 devm_free_irq(&pdev->dev, pdev->irq, dev);
313 pci_free_irq_vectors(pdev);
314 }
315
316 #ifdef CONFIG_PM
mt7921_pci_suspend(struct pci_dev * pdev,pm_message_t state)317 static int mt7921_pci_suspend(struct pci_dev *pdev, pm_message_t state)
318 {
319 struct mt76_dev *mdev = pci_get_drvdata(pdev);
320 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
321 struct mt76_connac_pm *pm = &dev->pm;
322 bool hif_suspend;
323 int i, err;
324
325 pm->suspended = true;
326 cancel_delayed_work_sync(&pm->ps_work);
327 cancel_work_sync(&pm->wake_work);
328
329 err = mt7921_mcu_drv_pmctrl(dev);
330 if (err < 0)
331 goto restore_suspend;
332
333 hif_suspend = !test_bit(MT76_STATE_SUSPEND, &dev->mphy.state);
334 if (hif_suspend) {
335 err = mt76_connac_mcu_set_hif_suspend(mdev, true);
336 if (err)
337 goto restore_suspend;
338 }
339
340 /* always enable deep sleep during suspend to reduce
341 * power consumption
342 */
343 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
344
345 napi_disable(&mdev->tx_napi);
346 mt76_worker_disable(&mdev->tx_worker);
347
348 mt76_for_each_q_rx(mdev, i) {
349 napi_disable(&mdev->napi[i]);
350 }
351
352 pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
353
354 /* wait until dma is idle */
355 mt76_poll(dev, MT_WFDMA0_GLO_CFG,
356 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
357 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
358
359 /* put dma disabled */
360 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
361 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
362
363 /* disable interrupt */
364 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
365 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
366 synchronize_irq(pdev->irq);
367 tasklet_kill(&dev->irq_tasklet);
368
369 err = mt7921_mcu_fw_pmctrl(dev);
370 if (err)
371 goto restore_napi;
372
373 pci_save_state(pdev);
374 err = pci_set_power_state(pdev, pci_choose_state(pdev, state));
375 if (err)
376 goto restore_napi;
377
378 return 0;
379
380 restore_napi:
381 mt76_for_each_q_rx(mdev, i) {
382 napi_enable(&mdev->napi[i]);
383 }
384 napi_enable(&mdev->tx_napi);
385
386 if (!pm->ds_enable)
387 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
388
389 if (hif_suspend)
390 mt76_connac_mcu_set_hif_suspend(mdev, false);
391
392 restore_suspend:
393 pm->suspended = false;
394
395 return err;
396 }
397
mt7921_pci_resume(struct pci_dev * pdev)398 static int mt7921_pci_resume(struct pci_dev *pdev)
399 {
400 struct mt76_dev *mdev = pci_get_drvdata(pdev);
401 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
402 struct mt76_connac_pm *pm = &dev->pm;
403 int i, err;
404
405 pm->suspended = false;
406 err = pci_set_power_state(pdev, PCI_D0);
407 if (err)
408 return err;
409
410 pci_restore_state(pdev);
411
412 err = mt7921_mcu_drv_pmctrl(dev);
413 if (err < 0)
414 return err;
415
416 mt7921_wpdma_reinit_cond(dev);
417
418 /* enable interrupt */
419 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
420 mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
421 MT_INT_MCU_CMD);
422 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
423
424 /* put dma enabled */
425 mt76_set(dev, MT_WFDMA0_GLO_CFG,
426 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
427
428 mt76_worker_enable(&mdev->tx_worker);
429 mt76_for_each_q_rx(mdev, i) {
430 napi_enable(&mdev->napi[i]);
431 napi_schedule(&mdev->napi[i]);
432 }
433 napi_enable(&mdev->tx_napi);
434 napi_schedule(&mdev->tx_napi);
435
436 /* restore previous ds setting */
437 if (!pm->ds_enable)
438 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
439
440 if (!test_bit(MT76_STATE_SUSPEND, &dev->mphy.state))
441 err = mt76_connac_mcu_set_hif_suspend(mdev, false);
442
443 return err;
444 }
445 #endif /* CONFIG_PM */
446
447 struct pci_driver mt7921_pci_driver = {
448 .name = KBUILD_MODNAME,
449 .id_table = mt7921_pci_device_table,
450 .probe = mt7921_pci_probe,
451 .remove = mt7921_pci_remove,
452 #ifdef CONFIG_PM
453 .suspend = mt7921_pci_suspend,
454 .resume = mt7921_pci_resume,
455 #endif /* CONFIG_PM */
456 };
457
458 module_pci_driver(mt7921_pci_driver);
459
460 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
461 MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
462 MODULE_FIRMWARE(MT7921_ROM_PATCH);
463 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
464 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
465 MODULE_LICENSE("Dual BSD/GPL");
466