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Searched refs:mmIH_VMID_0_LUT (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/oss/
Dosssys_4_0_offset.h28 #define mmIH_VMID_0_LUT macro
Dosssys_4_0_1_offset.h28 #define mmIH_VMID_0_LUT macro
Dosssys_5_0_0_offset.h28 #define mmIH_VMID_0_LUT macro
Dosssys_4_2_0_offset.h30 #define mmIH_VMID_0_LUT macro
Doss_2_4_d.h27 #define mmIH_VMID_0_LUT 0xe00 macro
Doss_3_0_1_d.h27 #define mmIH_VMID_0_LUT 0xe00 macro
Doss_3_0_d.h27 #define mmIH_VMID_0_LUT 0xe00 macro
Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50 macro
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v9.c148 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
867 mmIH_VMID_0_LUT) + vmid); in kgd_gfx_v9_get_cu_occupancy()
Damdgpu_amdkfd_gfx_v8.c121 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
Damdgpu_amdkfd_gfx_v7.c163 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
Damdgpu_amdkfd_gfx_v10.c143 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_set_pasid_vmid_mapping()
Damdgpu_amdkfd_gfx_v10_3.c116 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, value); in set_pasid_vmid_mapping_v10_3()
Dgmc_v10_0.c520 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; in gmc_v10_0_emit_pasid_mapping()
Dgmc_v9_0.c997 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; in gmc_v9_0_emit_pasid_mapping()
Dgmc_v7_0.c502 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v7_0_emit_pasid_mapping()
Dgmc_v8_0.c701 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v8_0_emit_pasid_mapping()