| /drivers/input/keyboard/ |
| D | imx_keypad.c | 48 void __iomem *mmio_base; member
93 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
95 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
97 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
99 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
103 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
105 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
112 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
114 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
126 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
[all …]
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| D | pxa930_rotary.c | 23 void __iomem *mmio_base; member
31 uint32_t sbcr = __raw_readl(r->mmio_base + SBCR); in clear_sbcr()
33 __raw_writel(sbcr | SBCR_ERSB, r->mmio_base + SBCR); in clear_sbcr()
34 __raw_writel(sbcr & ~SBCR_ERSB, r->mmio_base + SBCR); in clear_sbcr()
43 ercr = __raw_readl(r->mmio_base + ERCR) & 0xf; in rotary_irq()
110 r->mmio_base = ioremap(res->start, resource_size(res)); in pxa930_rotary_probe()
111 if (r->mmio_base == NULL) { in pxa930_rotary_probe()
166 iounmap(r->mmio_base); in pxa930_rotary_probe()
178 iounmap(r->mmio_base); in pxa930_rotary_remove()
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| /drivers/pwm/ |
| D | pwm-tiecap.c | 37 void __iomem *mmio_base; member
75 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
80 writew(value, pc->mmio_base + ECCTL2); in ecap_pwm_config()
84 writel(duty_cycles, pc->mmio_base + CAP2); in ecap_pwm_config()
85 writel(period_cycles, pc->mmio_base + CAP1); in ecap_pwm_config()
92 writel(duty_cycles, pc->mmio_base + CAP4); in ecap_pwm_config()
93 writel(period_cycles, pc->mmio_base + CAP3); in ecap_pwm_config()
97 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
100 writew(value, pc->mmio_base + ECCTL2); in ecap_pwm_config()
116 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_set_polarity()
[all …]
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| D | pwm-tiehrpwm.c | 110 void __iomem *mmio_base; member
211 ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); in configure_polarity()
278 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); in ehrpwm_pwm_config()
285 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW); in ehrpwm_pwm_config()
287 ehrpwm_write(pc->mmio_base, TBPRD, period_cycles); in ehrpwm_pwm_config()
290 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, in ehrpwm_pwm_config()
300 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); in ehrpwm_pwm_config()
338 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, in ehrpwm_pwm_enable()
341 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); in ehrpwm_pwm_enable()
372 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, in ehrpwm_pwm_disable()
[all …]
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| D | pwm-imx1.c | 31 void __iomem *mmio_base; member
86 max = readl(imx->mmio_base + MX1_PWMP); in pwm_imx1_config()
89 writel(max - p, imx->mmio_base + MX1_PWMS); in pwm_imx1_config()
104 value = readl(imx->mmio_base + MX1_PWMC); in pwm_imx1_enable()
106 writel(value, imx->mmio_base + MX1_PWMC); in pwm_imx1_enable()
116 value = readl(imx->mmio_base + MX1_PWMC); in pwm_imx1_disable()
118 writel(value, imx->mmio_base + MX1_PWMC); in pwm_imx1_disable()
158 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_imx1_probe()
159 if (IS_ERR(imx->mmio_base)) in pwm_imx1_probe()
160 return PTR_ERR(imx->mmio_base); in pwm_imx1_probe()
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| D | pwm-imx27.c | 85 void __iomem *mmio_base; member
133 val = readl(imx->mmio_base + MX3_PWMCR); in pwm_imx27_get_state()
153 val = readl(imx->mmio_base + MX3_PWMPR); in pwm_imx27_get_state()
165 val = readl(imx->mmio_base + MX3_PWMSAR); in pwm_imx27_get_state()
182 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); in pwm_imx27_sw_reset()
185 cr = readl(imx->mmio_base + MX3_PWMCR); in pwm_imx27_sw_reset()
202 sr = readl(imx->mmio_base + MX3_PWMSR); in pwm_imx27_wait_fifo_slot()
209 sr = readl(imx->mmio_base + MX3_PWMSR); in pwm_imx27_wait_fifo_slot()
265 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); in pwm_imx27_apply()
266 writel(period_cycles, imx->mmio_base + MX3_PWMPR); in pwm_imx27_apply()
[all …]
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| D | pwm-pxa.c | 48 void __iomem *mmio_base; member
96 writel(prescale, pc->mmio_base + offset + PWMCR); in pxa_pwm_config()
97 writel(dc, pc->mmio_base + offset + PWMDCR); in pxa_pwm_config()
98 writel(pv, pc->mmio_base + offset + PWMPCR); in pxa_pwm_config()
194 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_probe()
195 if (IS_ERR(pc->mmio_base)) in pwm_probe()
196 return PTR_ERR(pc->mmio_base); in pwm_probe()
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| D | pwm-spear.c | 54 void __iomem *mmio_base; member
67 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl()
74 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel()
206 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in spear_pwm_probe()
207 if (IS_ERR(pc->mmio_base)) in spear_pwm_probe()
208 return PTR_ERR(pc->mmio_base); in spear_pwm_probe()
234 val = readl_relaxed(pc->mmio_base + PWMMCR); in spear_pwm_probe()
236 writel_relaxed(val, pc->mmio_base + PWMMCR); in spear_pwm_probe()
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| /drivers/edac/ |
| D | al_mc_edac.c | 57 void __iomem *mmio_base; member
83 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ce()
88 ecccaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR0); in handle_ce()
89 ecccaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR1); in handle_ce()
90 ecccsyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND0); in handle_ce()
91 ecccsyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND1); in handle_ce()
92 ecccsyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND2); in handle_ce()
95 al_mc->mmio_base + AL_MC_ECC_CLEAR); in handle_ce()
128 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ue()
133 eccuaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR0); in handle_ue()
[all …]
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| /drivers/input/mouse/ |
| D | pxa930_trkball.c | 44 void __iomem *mmio_base; member
58 tbcntr = __raw_readl(trkball->mmio_base + TBCNTR); in pxa930_trkball_interrupt()
60 if (tbcntr == __raw_readl(trkball->mmio_base + TBCNTR)) { in pxa930_trkball_interrupt()
69 __raw_writel(TBSBC_TBSBC, trkball->mmio_base + TBSBC); in pxa930_trkball_interrupt()
70 __raw_writel(0, trkball->mmio_base + TBSBC); in pxa930_trkball_interrupt()
80 __raw_writel(v, trkball->mmio_base + TBCR); in write_tbcr()
83 if (__raw_readl(trkball->mmio_base + TBCR) == v) in write_tbcr()
101 tbcr = __raw_readl(trkball->mmio_base + TBCR); in pxa930_trkball_config()
107 tbcr = __raw_readl(trkball->mmio_base + TBCR); in pxa930_trkball_config()
111 __raw_writel(TBSBC_TBSBC, trkball->mmio_base + TBSBC); in pxa930_trkball_config()
[all …]
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| /drivers/ata/ |
| D | sata_sil.c | 254 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_bmdma_stop() local
255 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_stop()
280 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_bmdma_start() local
281 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_start()
349 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_set_mode() local
350 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; in sil_set_mode()
510 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; in sil_interrupt() local
518 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); in sil_interrupt()
539 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_freeze() local
543 writel(0, mmio_base + sil_port[ap->port_no].sien); in sil_freeze()
[all …]
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| D | pata_pdc2027x.c | 473 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_read_counter() local
479 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; in pdc_read_counter()
480 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; in pdc_read_counter()
483 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; in pdc_read_counter()
484 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; in pdc_read_counter()
514 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_adjust_pll() local
533 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
573 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
574 ioread16(mmio_base + PDC_PLL_CTL); /* flush */ in pdc_adjust_pll()
584 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
[all …]
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| D | sata_qstor.c | 192 u8 __iomem *mmio_base = qs_mmio_base(ap->host); in qs_freeze() local
194 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ in qs_freeze()
200 u8 __iomem *mmio_base = qs_mmio_base(ap->host); in qs_thaw() local
203 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */ in qs_thaw()
361 u8 __iomem *mmio_base = qs_mmio_base(host); in qs_intr_pkt() local
364 u32 sff0 = readl(mmio_base + QS_HST_SFF); in qs_intr_pkt()
365 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4); in qs_intr_pkt()
471 void __iomem *mmio_base = qs_mmio_base(ap->host); in qs_port_start() local
472 void __iomem *chan = mmio_base + (ap->port_no * 0x4000); in qs_port_start()
493 void __iomem *mmio_base = qs_mmio_base(host); in qs_host_stop() local
[all …]
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| D | pata_sil680.c | 345 void __iomem *mmio_base; in sil680_init_one() local
385 mmio_base = host->iomap[SIL680_MMIO_BAR]; in sil680_init_one()
386 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; in sil680_init_one()
387 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; in sil680_init_one()
388 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; in sil680_init_one()
389 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; in sil680_init_one()
391 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; in sil680_init_one()
392 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; in sil680_init_one()
393 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; in sil680_init_one()
394 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; in sil680_init_one()
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| /drivers/clk/mmp/ |
| D | clk-audio.c | 59 void __iomem *mmio_base; member
123 aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_recalc_rate()
131 aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_recalc_rate()
214 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_set_rate()
218 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_set_rate()
255 priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
265 priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
278 priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
286 priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
299 priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
[all …]
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| /drivers/net/wireless/broadcom/b43/ |
| D | pio.h | 72 u16 mmio_base; member
101 u16 mmio_base; member
111 return b43_read16(q->dev, q->mmio_base + offset); in b43_piotx_read16()
116 return b43_read32(q->dev, q->mmio_base + offset); in b43_piotx_read32()
122 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piotx_write16()
128 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piotx_write32()
134 return b43_read16(q->dev, q->mmio_base + offset); in b43_piorx_read16()
139 return b43_read32(q->dev, q->mmio_base + offset); in b43_piorx_read32()
145 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piorx_write16()
151 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piorx_write32()
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| /drivers/usb/host/ |
| D | ohci-pxa27x.c | 124 void __iomem *mmio_base; member
143 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); in pxa27x_ohci_select_pmm()
144 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB); in pxa27x_ohci_select_pmm()
168 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); in pxa27x_ohci_select_pmm()
169 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB); in pxa27x_ohci_select_pmm()
224 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); in pxa27x_setup_hc()
225 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); in pxa27x_setup_hc()
257 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); in pxa27x_setup_hc()
258 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); in pxa27x_setup_hc()
263 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); in pxa27x_reset_hc()
[all …]
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| /drivers/thermal/ |
| D | thermal_mmio.c | 12 void __iomem *mmio_base; member
13 u32 (*read_mmio)(void __iomem *mmio_base);
18 static u32 thermal_mmio_readb(void __iomem *mmio_base) in thermal_mmio_readb() argument
20 return readb(mmio_base); in thermal_mmio_readb()
29 t = sensor->read_mmio(sensor->mmio_base) & sensor->mask; in thermal_mmio_get_temperature()
56 sensor->mmio_base = devm_ioremap_resource(&pdev->dev, resource); in thermal_mmio_probe()
57 if (IS_ERR(sensor->mmio_base)) in thermal_mmio_probe()
58 return PTR_ERR(sensor->mmio_base); in thermal_mmio_probe()
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| /drivers/soundwire/ |
| D | intel_init.c | 63 link->mmio_base = res->mmio_base; in intel_link_dev_register()
64 link->registers = res->mmio_base + SDW_LINK_BASE in intel_link_dev_register()
66 link->shim = res->mmio_base + res->shim_base; in intel_link_dev_register()
67 link->alh = res->mmio_base + res->alh_base; in intel_link_dev_register()
137 void sdw_intel_enable_irq(void __iomem *mmio_base, bool enable) in sdw_intel_enable_irq() argument
141 val = readl(mmio_base + HDA_DSP_REG_ADSPIC2); in sdw_intel_enable_irq()
148 writel(val, mmio_base + HDA_DSP_REG_ADSPIC2); in sdw_intel_enable_irq()
160 sdw_intel_enable_irq(ctx->mmio_base, true); in sdw_intel_thread()
216 ctx->mmio_base = res->mmio_base; in sdw_intel_probe_controller()
307 caps = ioread32(ctx->mmio_base + ctx->shim_base + SDW_SHIM_LCAP); in sdw_intel_startup_controller()
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| /drivers/rtc/ |
| D | rtc-ep93xx.c | 29 void __iomem *mmio_base; member
39 comp = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_SWCOMP); in ep93xx_rtc_get_swcomp()
57 time = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_DATA); in ep93xx_rtc_read_time()
68 writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD); in ep93xx_rtc_set_time()
131 ep93xx_rtc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in ep93xx_rtc_probe()
132 if (IS_ERR(ep93xx_rtc->mmio_base)) in ep93xx_rtc_probe()
133 return PTR_ERR(ep93xx_rtc->mmio_base); in ep93xx_rtc_probe()
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| /drivers/video/fbdev/mb862xx/ |
| D | mb862xxfbdrv.c | 633 par->host = par->mmio_base; in mb862xx_gdc_init()
634 par->i2c = par->mmio_base + MB862XX_I2C_BASE; in mb862xx_gdc_init()
635 par->disp = par->mmio_base + MB862XX_DISP_BASE; in mb862xx_gdc_init()
636 par->cap = par->mmio_base + MB862XX_CAP_BASE; in mb862xx_gdc_init()
637 par->draw = par->mmio_base + MB862XX_DRAW_BASE; in mb862xx_gdc_init()
638 par->geo = par->mmio_base + MB862XX_GEO_BASE; in mb862xx_gdc_init()
639 par->pio = par->mmio_base + MB862XX_PIO_BASE; in mb862xx_gdc_init()
725 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len); in of_platform_mb862xx_probe()
726 if (par->mmio_base == NULL) { in of_platform_mb862xx_probe()
772 iounmap(par->mmio_base); in of_platform_mb862xx_probe()
[all …]
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| /drivers/net/ethernet/broadcom/ |
| D | bgmac.c | 46 if (!ring->mmio_base) in bgmac_dma_tx_reset()
53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, in bgmac_dma_tx_reset()
56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); in bgmac_dma_tx_reset()
68 ring->mmio_base, val); in bgmac_dma_tx_reset()
71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); in bgmac_dma_tx_reset()
73 ring->mmio_base + BGMAC_DMA_TX_STATUS, in bgmac_dma_tx_reset()
77 ring->mmio_base); in bgmac_dma_tx_reset()
79 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); in bgmac_dma_tx_reset()
82 ring->mmio_base); in bgmac_dma_tx_reset()
91 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); in bgmac_dma_tx_enable()
[all …]
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| /drivers/iommu/amd/ |
| D | init.c | 281 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
389 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
393 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
409 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
416 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
425 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
429 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
438 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
440 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
447 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
[all …]
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| /drivers/thermal/intel/int340x_thermal/ |
| D | processor_thermal_mbox.c | 35 data = readl(proc_priv->mmio_base + MBOX_OFFSET_INTERFACE); in wait_for_mbox_ready()
61 writel(data, (proc_priv->mmio_base + MBOX_OFFSET_DATA)); in send_mbox_write_cmd()
64 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_write_cmd()
89 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_read_cmd()
96 *resp = readl(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
98 *resp = readq(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
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| /drivers/platform/mellanox/ |
| D | mlxbf-pmc.c | 109 void __iomem *mmio_base; member
643 return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_config_l3_counters()
665 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_l3_counter()
670 pmcaddr = pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_l3_counter()
742 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_counter()
756 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_counter()
767 if (mlxbf_pmc_write(pmc->block[blk_num].mmio_base + in mlxbf_pmc_program_counter()
783 status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + in mlxbf_pmc_read_l3_counter()
791 status = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + in mlxbf_pmc_read_l3_counter()
831 status = mlxbf_pmc_write(pmc->block[blk_num].mmio_base + perfcfg_offset, in mlxbf_pmc_read_counter()
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