| /drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| D | usergf119.c | 41 int align, struct nvkm_gpuobj **pgpuobj) in gf119_dmaobj_bind() argument
47 ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj); in gf119_dmaobj_bind()
49 nvkm_kmap(*pgpuobj); in gf119_dmaobj_bind()
50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gf119_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8); in gf119_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8); in gf119_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in gf119_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in gf119_dmaobj_bind()
55 nvkm_wo32(*pgpuobj, 0x14, 0x00000000); in gf119_dmaobj_bind()
56 nvkm_done(*pgpuobj); in gf119_dmaobj_bind()
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| D | usergf100.c | 42 int align, struct nvkm_gpuobj **pgpuobj) in gf100_dmaobj_bind() argument
48 ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj); in gf100_dmaobj_bind()
50 nvkm_kmap(*pgpuobj); in gf100_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gf100_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); in gf100_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); in gf100_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | in gf100_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in gf100_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); in gf100_dmaobj_bind()
58 nvkm_done(*pgpuobj); in gf100_dmaobj_bind()
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| D | usergv100.c | 39 int align, struct nvkm_gpuobj **pgpuobj) in gv100_dmaobj_bind() argument
47 ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj); in gv100_dmaobj_bind()
49 nvkm_kmap(*pgpuobj); in gv100_dmaobj_bind()
50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in gv100_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(start)); in gv100_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x08, upper_32_bits(start)); in gv100_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, lower_32_bits(limit)); in gv100_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x10, upper_32_bits(limit)); in gv100_dmaobj_bind()
55 nvkm_done(*pgpuobj); in gv100_dmaobj_bind()
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| D | usernv50.c | 42 int align, struct nvkm_gpuobj **pgpuobj) in nv50_dmaobj_bind() argument
48 ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj); in nv50_dmaobj_bind()
50 nvkm_kmap(*pgpuobj); in nv50_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); in nv50_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); in nv50_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); in nv50_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | in nv50_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in nv50_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); in nv50_dmaobj_bind()
58 nvkm_done(*pgpuobj); in nv50_dmaobj_bind()
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| D | usernv04.c | 42 int align, struct nvkm_gpuobj **pgpuobj) in nv04_dmaobj_bind() argument
55 return nvkm_gpuobj_wrap(pgt, pgpuobj); in nv04_dmaobj_bind()
62 ret = nvkm_gpuobj_new(device, 16, align, false, parent, pgpuobj); in nv04_dmaobj_bind()
64 nvkm_kmap(*pgpuobj); in nv04_dmaobj_bind()
65 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20)); in nv04_dmaobj_bind()
66 nvkm_wo32(*pgpuobj, 0x04, length); in nv04_dmaobj_bind()
67 nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
68 nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset); in nv04_dmaobj_bind()
69 nvkm_done(*pgpuobj); in nv04_dmaobj_bind()
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| D | user.c | 48 int align, struct nvkm_gpuobj **pgpuobj) in nvkm_dmaobj_bind() argument
51 return dmaobj->func->bind(dmaobj, gpuobj, align, pgpuobj); in nvkm_dmaobj_bind()
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| /drivers/gpu/drm/nouveau/nvkm/engine/cipher/ |
| D | g84.c | 35 int align, struct nvkm_gpuobj **pgpuobj) in g84_cipher_oclass_bind() argument
38 align, false, parent, pgpuobj); in g84_cipher_oclass_bind()
40 nvkm_kmap(*pgpuobj); in g84_cipher_oclass_bind()
41 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in g84_cipher_oclass_bind()
42 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in g84_cipher_oclass_bind()
43 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in g84_cipher_oclass_bind()
44 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in g84_cipher_oclass_bind()
45 nvkm_done(*pgpuobj); in g84_cipher_oclass_bind()
57 int align, struct nvkm_gpuobj **pgpuobj) in g84_cipher_cclass_bind() argument
60 align, true, parent, pgpuobj); in g84_cipher_cclass_bind()
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| /drivers/gpu/drm/nouveau/nvkm/core/ |
| D | gpuobj.c | 215 nvkm_gpuobj_del(struct nvkm_gpuobj **pgpuobj) in nvkm_gpuobj_del() argument
217 struct nvkm_gpuobj *gpuobj = *pgpuobj; in nvkm_gpuobj_del()
223 kfree(*pgpuobj); in nvkm_gpuobj_del()
224 *pgpuobj = NULL; in nvkm_gpuobj_del()
230 struct nvkm_gpuobj *parent, struct nvkm_gpuobj **pgpuobj) in nvkm_gpuobj_new() argument
235 if (!(gpuobj = *pgpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL))) in nvkm_gpuobj_new()
240 nvkm_gpuobj_del(pgpuobj); in nvkm_gpuobj_new()
250 nvkm_gpuobj_wrap(struct nvkm_memory *memory, struct nvkm_gpuobj **pgpuobj) in nvkm_gpuobj_wrap() argument
252 if (!(*pgpuobj = kzalloc(sizeof(**pgpuobj), GFP_KERNEL))) in nvkm_gpuobj_wrap()
255 (*pgpuobj)->addr = nvkm_memory_addr(memory); in nvkm_gpuobj_wrap()
[all …]
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| D | oproxy.c | 91 int align, struct nvkm_gpuobj **pgpuobj) in nvkm_oproxy_bind() argument
94 parent, align, pgpuobj); in nvkm_oproxy_bind()
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| D | object.c | 171 int align, struct nvkm_gpuobj **pgpuobj) in nvkm_object_bind() argument
174 return object->func->bind(object, gpuobj, align, pgpuobj); in nvkm_object_bind()
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | nv40.c | 45 int align, struct nvkm_gpuobj **pgpuobj) in nv40_gr_object_bind() argument
48 false, parent, pgpuobj); in nv40_gr_object_bind()
50 nvkm_kmap(*pgpuobj); in nv40_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv40_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv40_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv40_gr_object_bind()
55 nvkm_mo32(*pgpuobj, 0x08, 0x01000000, 0x01000000); in nv40_gr_object_bind()
57 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv40_gr_object_bind()
58 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); in nv40_gr_object_bind()
59 nvkm_done(*pgpuobj); in nv40_gr_object_bind()
[all …]
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| D | nv50.c | 44 int align, struct nvkm_gpuobj **pgpuobj) in nv50_gr_object_bind() argument
47 align, false, parent, pgpuobj); in nv50_gr_object_bind()
49 nvkm_kmap(*pgpuobj); in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
54 nvkm_done(*pgpuobj); in nv50_gr_object_bind()
70 int align, struct nvkm_gpuobj **pgpuobj) in nv50_gr_chan_bind() argument
74 align, true, parent, pgpuobj); in nv50_gr_chan_bind()
[all …]
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| D | nv04.c | 1044 int align, struct nvkm_gpuobj **pgpuobj) in nv04_gr_object_bind() argument
1047 false, parent, pgpuobj); in nv04_gr_object_bind()
1049 nvkm_kmap(*pgpuobj); in nv04_gr_object_bind()
1050 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv04_gr_object_bind()
1052 nvkm_mo32(*pgpuobj, 0x00, 0x00080000, 0x00080000); in nv04_gr_object_bind()
1054 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv04_gr_object_bind()
1055 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv04_gr_object_bind()
1056 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv04_gr_object_bind()
1057 nvkm_done(*pgpuobj); in nv04_gr_object_bind()
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| D | gf100.c | 321 int align, struct nvkm_gpuobj **pgpuobj) in gf100_gr_chan_bind() argument
328 align, false, parent, pgpuobj); in gf100_gr_chan_bind()
332 nvkm_kmap(*pgpuobj); in gf100_gr_chan_bind()
334 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); in gf100_gr_chan_bind()
337 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); in gf100_gr_chan_bind()
338 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8); in gf100_gr_chan_bind()
340 nvkm_wo32(*pgpuobj, 0xf4, 0); in gf100_gr_chan_bind()
341 nvkm_wo32(*pgpuobj, 0xf8, 0); in gf100_gr_chan_bind()
342 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); in gf100_gr_chan_bind()
343 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr)); in gf100_gr_chan_bind()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/mpeg/ |
| D | nv50.c | 38 int align, struct nvkm_gpuobj **pgpuobj) in nv50_mpeg_cclass_bind() argument
41 align, true, parent, pgpuobj); in nv50_mpeg_cclass_bind()
43 nvkm_kmap(*pgpuobj); in nv50_mpeg_cclass_bind()
44 nvkm_wo32(*pgpuobj, 0x70, 0x00801ec1); in nv50_mpeg_cclass_bind()
45 nvkm_wo32(*pgpuobj, 0x7c, 0x0000037c); in nv50_mpeg_cclass_bind()
46 nvkm_done(*pgpuobj); in nv50_mpeg_cclass_bind()
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| D | nv31.c | 40 int align, struct nvkm_gpuobj **pgpuobj) in nv31_mpeg_object_bind() argument
43 false, parent, pgpuobj); in nv31_mpeg_object_bind()
45 nvkm_kmap(*pgpuobj); in nv31_mpeg_object_bind()
46 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv31_mpeg_object_bind()
47 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv31_mpeg_object_bind()
48 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv31_mpeg_object_bind()
49 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv31_mpeg_object_bind()
50 nvkm_done(*pgpuobj); in nv31_mpeg_object_bind()
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| D | nv44.c | 53 int align, struct nvkm_gpuobj **pgpuobj) in nv44_mpeg_chan_bind() argument
57 align, true, parent, pgpuobj); in nv44_mpeg_chan_bind()
59 chan->inst = (*pgpuobj)->addr; in nv44_mpeg_chan_bind()
60 nvkm_kmap(*pgpuobj); in nv44_mpeg_chan_bind()
61 nvkm_wo32(*pgpuobj, 0x78, 0x02001ec1); in nv44_mpeg_chan_bind()
62 nvkm_done(*pgpuobj); in nv44_mpeg_chan_bind()
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| /drivers/gpu/drm/nouveau/nvkm/engine/ |
| D | xtensa.c | 45 int align, struct nvkm_gpuobj **pgpuobj) in nvkm_xtensa_cclass_bind() argument
48 true, parent, pgpuobj); in nvkm_xtensa_cclass_bind()
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| D | falcon.c | 47 int align, struct nvkm_gpuobj **pgpuobj) in nvkm_falcon_cclass_bind() argument
50 align, true, parent, pgpuobj); in nvkm_falcon_cclass_bind()
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