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Searched refs:phyclk_mhz (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c174 .phyclk_mhz = 600.0,
185 .phyclk_mhz = 600.0,
196 .phyclk_mhz = 600.0,
207 .phyclk_mhz = 600.0,
218 .phyclk_mhz = 810.0,
229 .phyclk_mhz = 810.0,
240 .phyclk_mhz = 810.0,
251 .phyclk_mhz = 1325.0,
263 .phyclk_mhz = 1325.0,
1581 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz; in construct_low_pstate_lvl()
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/drivers/gpu/drm/amd/amdgpu/
Damdgpu_socbb.h34 uint32_t phyclk_mhz; member
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c239 .phyclk_mhz = 540.0,
250 .phyclk_mhz = 600.0,
261 .phyclk_mhz = 810.0,
272 .phyclk_mhz = 810.0,
283 .phyclk_mhz = 810.0,
295 .phyclk_mhz = 810.0,
350 .phyclk_mhz = 540.0,
361 .phyclk_mhz = 600.0,
372 .phyclk_mhz = 810.0,
383 .phyclk_mhz = 810.0,
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/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c179 .phyclk_mhz = 600.0,
190 .phyclk_mhz = 600.0,
201 .phyclk_mhz = 810.0,
213 .phyclk_mhz = 810.0,
225 .phyclk_mhz = 810.0,
1611 clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in dcn301_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h93 unsigned int phyclk_mhz; member
/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c141 .phyclk_mhz = 810.0,
1246 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn303_update_bw_bounding_box()
1247 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn303_update_bw_bounding_box()
1256 max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; in dcn303_update_bw_bounding_box()
1332 dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; in dcn303_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c159 .phyclk_mhz = 300.0,
1316 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn302_update_bw_bounding_box()
1317 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn302_update_bw_bounding_box()
1326 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; in dcn302_update_bw_bounding_box()
1404 dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; in dcn302_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c175 .phyclk_mhz = 600.0,
184 .phyclk_mhz = 810.0,
193 .phyclk_mhz = 810.0,
202 .phyclk_mhz = 810.0,
211 .phyclk_mhz = 810.0,
1916 clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in dcn31_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c211 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
485 unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000; in dcn30_notify_link_rate_change()
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_structs.h67 double phyclk_mhz; member
Ddisplay_mode_vba.c282 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c177 .phyclk_mhz = 300.0,
2414 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn30_update_bw_bounding_box()
2415 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn30_update_bw_bounding_box()
2425 max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; in dcn30_update_bw_bounding_box()
2505 dcn3_0_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; in dcn30_update_bw_bounding_box()