| /drivers/media/platform/cadence/ |
| D | cdns-csi2rx.c | 70 struct clk *pixel_clk[CSI2RX_STREAMS_MAX]; member
153 ret = clk_prepare_enable(csi2rx->pixel_clk[i]); in csi2rx_start()
178 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); in csi2rx_start()
196 clk_disable_unprepare(csi2rx->pixel_clk[i]); in csi2rx_stop()
357 csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name); in csi2rx_get_resources()
358 if (IS_ERR(csi2rx->pixel_clk[i])) { in csi2rx_get_resources()
360 return PTR_ERR(csi2rx->pixel_clk[i]); in csi2rx_get_resources()
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| D | cdns-csi2tx.c | 107 struct clk *pixel_clk[CSI2TX_STREAMS_MAX]; member
487 csi2tx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name); in csi2tx_get_resources()
488 if (IS_ERR(csi2tx->pixel_clk[i])) { in csi2tx_get_resources()
491 return PTR_ERR(csi2tx->pixel_clk[i]); in csi2tx_get_resources()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_audio.c | 524 unsigned int h_active, h_total, hblank_delta, pixel_clk; in calc_hblank_early_prog() local
531 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; in calc_hblank_early_prog()
543 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
546 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; in calc_hblank_early_prog()
547 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); in calc_hblank_early_prog()
552 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
555 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000), in calc_hblank_early_prog()
558 mul_u32_u32(64 * pixel_clk, 1000000)); in calc_hblank_early_prog()
561 …hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_… in calc_hblank_early_prog()
568 unsigned int h_active, h_total, pixel_clk; in calc_samples_room() local
[all …]
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| /drivers/gpu/drm/mediatek/ |
| D | mtk_dpi.c | 68 struct clk *pixel_clk; member
391 clk_disable_unprepare(dpi->pixel_clk); in mtk_dpi_power_off()
408 ret = clk_prepare_enable(dpi->pixel_clk); in mtk_dpi_power_on()
451 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); in mtk_dpi_set_display_mode()
453 clk_set_rate(dpi->pixel_clk, vm.pixelclock); in mtk_dpi_set_display_mode()
456 vm.pixelclock = clk_get_rate(dpi->pixel_clk); in mtk_dpi_set_display_mode()
859 dpi->pixel_clk = devm_clk_get(dev, "pixel"); in mtk_dpi_probe()
860 if (IS_ERR(dpi->pixel_clk)) { in mtk_dpi_probe()
861 ret = PTR_ERR(dpi->pixel_clk); in mtk_dpi_probe()
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| /drivers/gpu/drm/stm/ |
| D | ltdc.c | 476 result = clk_round_rate(ldev->pixel_clk, target); in ltdc_crtc_mode_valid()
512 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { in ltdc_crtc_mode_fixup()
517 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; in ltdc_crtc_mode_fixup()
1194 clk_disable_unprepare(ldev->pixel_clk); in ltdc_suspend()
1204 ret = clk_prepare_enable(ldev->pixel_clk); in ltdc_resume()
1234 ldev->pixel_clk = devm_clk_get(dev, "lcd"); in ltdc_load()
1235 if (IS_ERR(ldev->pixel_clk)) { in ltdc_load()
1236 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) in ltdc_load()
1238 return PTR_ERR(ldev->pixel_clk); in ltdc_load()
1241 if (clk_prepare_enable(ldev->pixel_clk)) { in ltdc_load()
[all …]
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| D | ltdc.h | 34 struct clk *pixel_clk; /* lcd pixel clock */ member
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| /drivers/gpu/drm/msm/edp/ |
| D | edp_ctrl.c | 65 struct clk *pixel_clk; member
155 ctrl->pixel_clk = msm_clk_get(pdev, "pixel"); in edp_clk_init()
156 if (IS_ERR(ctrl->pixel_clk)) { in edp_clk_init()
157 ret = PTR_ERR(ctrl->pixel_clk); in edp_clk_init()
159 ctrl->pixel_clk = NULL; in edp_clk_init()
237 ret = clk_set_rate(ctrl->pixel_clk, in edp_clk_enable()
245 ret = clk_prepare_enable(ctrl->pixel_clk); in edp_clk_enable()
263 clk_disable_unprepare(ctrl->pixel_clk); in edp_clk_enable()
282 clk_disable_unprepare(ctrl->pixel_clk); in edp_clk_disable()
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_host.c | 113 struct clk *pixel_clk; member
398 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); in dsi_clk_init()
399 if (IS_ERR(msm_host->pixel_clk)) { in dsi_clk_init()
400 ret = PTR_ERR(msm_host->pixel_clk); in dsi_clk_init()
403 msm_host->pixel_clk = NULL; in dsi_clk_init()
423 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); in dsi_clk_init()
514 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_6g()
555 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
573 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
608 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_v2()
[all …]
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| /drivers/gpu/drm/bridge/synopsys/ |
| D | dw-hdmi.c | 574 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) in hdmi_compute_n() argument
586 if (pixel_clk == 25175000) in hdmi_compute_n()
588 else if (pixel_clk == 27027000) in hdmi_compute_n()
590 else if (pixel_clk == 74176000 || pixel_clk == 148352000) in hdmi_compute_n()
598 if (pixel_clk == 25175000) in hdmi_compute_n()
600 else if (pixel_clk == 74176000) in hdmi_compute_n()
602 else if (pixel_clk == 148352000) in hdmi_compute_n()
610 if (pixel_clk == 25175000) in hdmi_compute_n()
612 else if (pixel_clk == 27027000) in hdmi_compute_n()
614 else if (pixel_clk == 74176000) in hdmi_compute_n()
[all …]
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | clock_source.h | 176 unsigned int pixel_clk,
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| /drivers/gpu/drm/aspeed/ |
| D | aspeed_gfx_crtc.c | 93 clk_set_rate(priv->pixel_clk, m->crtc_clock * 1000); in aspeed_gfx_crtc_mode_set_nofb()
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| /drivers/gpu/ipu-v3/ |
| D | ipu-csi.c | 192 static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk, in ipu_csi_set_testgen_mclk() argument
198 div_ratio = (ipu_clk / pixel_clk) - 1; in ipu_csi_set_testgen_mclk()
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| /drivers/gpu/drm/amd/display/include/ |
| D | grph_object_ctrl_defs.h | 128 uint32_t pixel_clk; /* in KHz */ member
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| D | command_table.c | 1541 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v2() local
1545 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v2()
1591 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v3() local
1595 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v3()
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| D | bios_parser.c | 1236 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_2()
1354 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_3()
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| D | bios_parser2.c | 1132 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; in get_embedded_panel_info_v2_1()
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| /drivers/video/fbdev/ |
| D | mx3fb.c | 506 uint32_t pixel_clk, in sdc_init_panel() argument
567 div = clk_get_rate(ipu_clk) * 16 / pixel_clk; in sdc_init_panel()
580 pixel_clk, div >> 4, (div & 7) * 125); in sdc_init_panel()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.c | 1114 unsigned int pixel_clk, in dcn20_override_dp_pix_clk() argument
1120 REG_WRITE(PHASE[inst], pixel_clk); in dcn20_override_dp_pix_clk()
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| /drivers/gpu/drm/i915/gvt/ |
| D | handlers.c | 676 u64 pixel_clk = 0; in vgpu_update_refresh_rate() local
681 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); in vgpu_update_refresh_rate()
682 pixel_clk *= MSEC_PER_SEC; in vgpu_update_refresh_rate()
685 …new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal… in vgpu_update_refresh_rate()
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