| /drivers/gpu/drm/amd/display/dc/ |
| D | dm_pp_smu.h | 48 struct pp_smu { struct
97 struct pp_smu pp_smu; member
103 void (*set_display_count)(struct pp_smu *pp, int count);
112 void (*set_wm_ranges)(struct pp_smu *pp,
118 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
124 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
129 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
134 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
137 void (*set_pme_wa_enable)(struct pp_smu *pp);
168 struct pp_smu pp_smu; member
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 198 struct pp_smu_funcs_rv *pp_smu = NULL; in rv1_update_clocks() local
205 ASSERT(clk_mgr->pp_smu); in rv1_update_clocks()
210 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_update_clocks()
223 if (pp_smu->set_display_count) in rv1_update_clocks()
224 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in rv1_update_clocks()
264 if (pp_smu->set_hard_min_fclk_by_freq && in rv1_update_clocks()
265 pp_smu->set_hard_min_dcfclk_by_freq && in rv1_update_clocks()
266 pp_smu->set_min_deep_sleep_dcfclk) { in rv1_update_clocks()
267 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
268 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
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| D | rv2_clk_mgr.c | 37 …gr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) in rv2_clk_mgr_construct() argument
40 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
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| D | rv2_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
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| D | rv1_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 214 struct pp_smu_funcs_nv *pp_smu = NULL; in dcn2_update_clocks() local
238 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
239 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
245 if (pp_smu && pp_smu->set_display_count) in dcn2_update_clocks()
246 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in dcn2_update_clocks()
255 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) in dcn2_update_clocks()
256 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
262 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) in dcn2_update_clocks()
263 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_… in dcn2_update_clocks()
268 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) in dcn2_update_clocks()
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| D | dcn20_clk_mgr.h | 43 struct pp_smu_funcs *pp_smu,
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| D | clk_mgr.c | 135 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg … in dc_clk_mgr_create() argument
221 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
226 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
230 rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
235 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
248 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
252 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
256 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
259 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
270 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_pp_smu.c | 492 static void pp_rv_set_wm_ranges(struct pp_smu *pp, in pp_rv_set_wm_ranges()
544 static void pp_rv_set_pme_wa_enable(struct pp_smu *pp) in pp_rv_set_pme_wa_enable()
555 static void pp_rv_set_active_display_count(struct pp_smu *pp, int count) in pp_rv_set_active_display_count()
568 static void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock) in pp_rv_set_min_deep_sleep_dcfclk()
581 static void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock) in pp_rv_set_hard_min_dcefclk_by_freq()
594 static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) in pp_rv_set_hard_min_fclk_by_freq()
607 static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp, in pp_nv_set_wm_ranges()
621 static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count) in pp_nv_set_display_count()
639 pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) in pp_nv_set_min_deep_sleep_dcfclk()
657 struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_dcefclk_by_freq()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 520 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; in rn_notify_wm_ranges() local
526 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) in rn_notify_wm_ranges()
527 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
930 struct pp_smu_funcs *pp_smu, in rn_clk_mgr_construct() argument
945 clk_mgr->pp_smu = pp_smu; in rn_clk_mgr_construct()
1006 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { in rn_clk_mgr_construct()
1007 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); in rn_clk_mgr_construct()
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| D | rn_clk_mgr.h | 38 struct pp_smu_funcs *pp_smu,
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 706 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1029 if (pool->base.pp_smu != NULL) in dcn21_resource_destruct()
1030 dcn21_pp_smu_destroy(&pool->base.pp_smu); in dcn21_resource_destruct()
1654 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn21_pp_smu_create() local
1656 if (!pp_smu) in dcn21_pp_smu_create()
1657 return pp_smu; in dcn21_pp_smu_create()
1659 dm_pp_get_funcs(ctx, pp_smu); in dcn21_pp_smu_create()
1661 if (pp_smu->ctx.ver != PP_SMU_VER_RN) in dcn21_pp_smu_create()
1662 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn21_pp_smu_create()
1665 return pp_smu; in dcn21_pp_smu_create()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1430 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1565 if (pool->base.pp_smu != NULL) in dcn20_resource_destruct()
1566 dcn20_pp_smu_destroy(&pool->base.pp_smu); in dcn20_resource_destruct()
3422 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); in dcn20_pp_smu_create() local
3424 if (!pp_smu) in dcn20_pp_smu_create()
3425 return pp_smu; in dcn20_pp_smu_create()
3427 dm_pp_get_funcs(ctx, pp_smu); in dcn20_pp_smu_create()
3429 if (pp_smu->ctx.ver != PP_SMU_VER_NV) in dcn20_pp_smu_create()
3430 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn20_pp_smu_create()
3432 return pp_smu; in dcn20_pp_smu_create()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 956 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); in dcn10_pp_smu_create() local
958 if (!pp_smu) in dcn10_pp_smu_create()
959 return pp_smu; in dcn10_pp_smu_create()
961 dm_pp_get_funcs(ctx, pp_smu); in dcn10_pp_smu_create()
962 return pp_smu; in dcn10_pp_smu_create()
1047 kfree(pool->base.pp_smu); in dcn10_resource_destruct()
1540 pool->base.pp_smu = dcn10_pp_smu_create(ctx); in dcn10_resource_construct()
1546 if (pool->base.pp_smu != NULL in dcn10_resource_construct()
1547 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) in dcn10_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.h | 33 struct pp_smu_funcs *pp_smu,
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| D | dcn30_clk_mgr.c | 534 struct pp_smu_funcs *pp_smu, in dcn3_clk_mgr_construct() argument
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.h | 44 struct pp_smu_funcs *pp_smu,
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| D | dcn31_clk_mgr.c | 632 struct pp_smu_funcs *pp_smu, in dcn31_clk_mgr_construct() argument
640 clk_mgr->base.pp_smu = pp_smu; in dcn31_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.h | 44 struct pp_smu_funcs *pp_smu,
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| D | vg_clk_mgr.c | 732 struct pp_smu_funcs *pp_smu, in vg_clk_mgr_construct() argument
740 clk_mgr->base.pp_smu = pp_smu; in vg_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 287 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg …
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| D | clk_mgr_internal.h | 217 struct pp_smu_funcs *pp_smu; member
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1532 struct pp_smu_funcs *pp_smu, in set_wm_ranges() argument
1572 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); in set_wm_ranges()
1877 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) in dcn301_resource_construct()
1878 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); in dcn301_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 220 struct pp_smu_funcs *pp_smu; member
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 1553 if (dc->res_pool->pp_smu) in dcn_bw_notify_pplib_of_wm_ranges()
1554 pp = &dc->res_pool->pp_smu->rv_funcs; in dcn_bw_notify_pplib_of_wm_ranges()
1608 pp->set_wm_ranges(&pp->pp_smu, &ranges); in dcn_bw_notify_pplib_of_wm_ranges()
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