| /drivers/gpu/drm/radeon/ |
| D | radeon_cursor.c | 35 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_lock_cursor() local
39 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
44 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
46 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
51 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
53 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); in radeon_lock_cursor()
58 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
64 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_hide_cursor() local
68 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor()
72 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor()
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| D | atombios_crtc.c | 44 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_overscan_setup() local
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
74 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
75 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
76 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
77 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
87 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_scaler_setup() local
91 to_radeon_encoder(radeon_crtc->encoder); in atombios_scaler_setup()
96 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup()
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| D | radeon_display.c | 51 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in avivo_crtc_load_lut() local
57 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
58 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
60 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
62 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
64 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
65 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
66 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
68 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); in avivo_crtc_load_lut()
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| D | radeon_legacy_crtc.c | 42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_overscan_setup() local
44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
54 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_legacy_rmx_mode_set() local
66 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; in radeon_legacy_rmx_mode_set()
129 switch (radeon_crtc->rmx_type) { in radeon_legacy_rmx_mode_set()
299 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_dpms() local
305 if (radeon_crtc->crtc_id) in radeon_crtc_dpms()
327 radeon_crtc->enabled = true; in radeon_crtc_dpms()
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| D | rs600.c | 121 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip() local
122 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in rs600_page_flip()
123 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
128 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
131 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rs600_page_flip()
134 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rs600_page_flip()
137 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
139 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
144 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
152 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
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| D | radeon_legacy_encoders.c | 190 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_lvds_mode_set() local
228 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_lvds_mode_set()
249 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_lvds_mode_set()
251 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_lvds_mode_set()
591 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_primary_dac_mode_set() local
597 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_primary_dac_mode_set()
637 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_primary_dac_mode_set()
639 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_primary_dac_mode_set()
788 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_tmds_int_mode_set() local
855 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_tmds_int_mode_set()
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| D | dce6_afmt.h | 32 struct radeon_crtc;
48 struct radeon_crtc *crtc, unsigned int clock);
50 struct radeon_crtc *crtc, unsigned int clock);
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| D | evergreen_hdmi.h | 37 struct radeon_crtc;
60 struct radeon_crtc *crtc, unsigned int clock);
62 struct radeon_crtc *crtc, unsigned int clock);
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| D | radeon_dp_mst.c | 332 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_dp_mst_prepare_pll() local
335 struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder); in radeon_dp_mst_prepare_pll()
344 radeon_crtc->bpc = radeon_connector->base.display_info.bpc; in radeon_dp_mst_prepare_pll()
346 radeon_crtc->bpc = 8; in radeon_dp_mst_prepare_pll()
351 radeon_crtc->ss_enabled = in radeon_dp_mst_prepare_pll()
352 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, in radeon_dp_mst_prepare_pll()
367 struct radeon_crtc *radeon_crtc; in radeon_mst_encoder_dpms() local
394 radeon_crtc = to_radeon_crtc(crtc); in radeon_mst_encoder_dpms()
411 mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id); in radeon_mst_encoder_dpms()
419 dig_enc->linkb, radeon_crtc->crtc_id); in radeon_mst_encoder_dpms()
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| D | atombios_encoders.c | 462 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_atom_get_bpc() local
463 bpc = radeon_crtc->bpc; in radeon_atom_get_bpc()
1056 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_dig_transmitter_setup2() local
1057 pll_id = radeon_crtc->pll_id; in atombios_dig_transmitter_setup2()
1544 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_yuv_setup() local
1560 (radeon_crtc->crtc_id << 18))); in atombios_yuv_setup()
1562 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); in atombios_yuv_setup()
1568 args.ucCRTC = radeon_crtc->crtc_id; in atombios_yuv_setup()
1867 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_set_encoder_crtc_source() local
1884 args.v1.ucCRTC = radeon_crtc->crtc_id; in atombios_set_encoder_crtc_source()
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| D | evergreen.c | 1295 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in dce4_program_fmt() local
1343 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
1417 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip() local
1418 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in evergreen_page_flip()
1421 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in evergreen_page_flip()
1424 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1427 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1429 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
1432 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); in evergreen_page_flip()
1445 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip_pending() local
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| D | radeon_legacy_tv.c | 242 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_get_std_mode() local
247 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); in radeon_legacy_tv_get_std_mode()
248 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_get_std_mode()
533 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_mode_set() local
550 radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_tv_mode_set()
596 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_mode_set()
599 if (radeon_crtc->rmx_type != RMX_OFF) in radeon_legacy_tv_mode_set()
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| D | r600.h | 34 struct radeon_crtc;
47 struct radeon_crtc *crtc, unsigned int clock);
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| D | radeon_mode.h | 46 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
247 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
327 struct radeon_crtc { struct
942 struct radeon_crtc *radeon_crtc);
944 struct radeon_crtc *radeon_crtc);
959 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
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| D | rv770.c | 812 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip() local
813 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in rv770_page_flip()
814 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
819 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
822 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rv770_page_flip()
825 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rv770_page_flip()
828 if (radeon_crtc->crtc_id) { in rv770_page_flip()
835 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
837 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
842 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
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| D | r600_dpm.c | 160 struct radeon_crtc *radeon_crtc; in r600_dpm_get_vblank_time() local
166 radeon_crtc = to_radeon_crtc(crtc); in r600_dpm_get_vblank_time()
167 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { in r600_dpm_get_vblank_time()
169 radeon_crtc->hw_mode.crtc_htotal * in r600_dpm_get_vblank_time()
170 (radeon_crtc->hw_mode.crtc_vblank_end - in r600_dpm_get_vblank_time()
171 radeon_crtc->hw_mode.crtc_vdisplay + in r600_dpm_get_vblank_time()
172 (radeon_crtc->v_border * 2)); in r600_dpm_get_vblank_time()
174 vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock; in r600_dpm_get_vblank_time()
187 struct radeon_crtc *radeon_crtc; in r600_dpm_get_vrefresh() local
192 radeon_crtc = to_radeon_crtc(crtc); in r600_dpm_get_vrefresh()
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| D | evergreen_hdmi.c | 76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in evergreen_hdmi_update_acr() local
77 bpc = radeon_crtc->bpc; in evergreen_hdmi_update_acr()
229 struct radeon_crtc *crtc, unsigned int clock) in dce4_hdmi_audio_set_dto()
272 struct radeon_crtc *crtc, unsigned int clock) in dce4_dp_audio_set_dto()
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| D | radeon_audio.h | 55 struct radeon_crtc *crtc, unsigned int clock);
91 struct radeon_crtc *crtc, unsigned int clock);
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| D | radeon_device.c | 1586 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_suspend_kms() local
1590 if (radeon_crtc->cursor_bo) { in radeon_suspend_kms()
1591 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); in radeon_suspend_kms()
1711 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_resume_kms() local
1713 if (radeon_crtc->cursor_bo) { in radeon_resume_kms()
1714 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); in radeon_resume_kms()
1722 &radeon_crtc->cursor_addr); in radeon_resume_kms()
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| D | r100.c | 164 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip() local
166 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in r100_page_flip()
172 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
179 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch); in r100_page_flip()
183 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
191 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
206 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip_pending() local
209 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
462 struct radeon_crtc *radeon_crtc; in r100_pm_prepare() local
467 radeon_crtc = to_radeon_crtc(crtc); in r100_pm_prepare()
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| D | si.c | 1967 struct radeon_crtc *radeon_crtc, in dce6_line_buffer_adjust() argument
1972 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust()
1986 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
1999 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust()
2011 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
2294 struct radeon_crtc *radeon_crtc, in dce6_program_watermarks() argument
2297 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce6_program_watermarks()
2309 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
2341 wm_high.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2343 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks()
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| D | radeon_pm.c | 1696 struct radeon_crtc *radeon_crtc; in radeon_pm_compute_clocks_old() local
1708 radeon_crtc = to_radeon_crtc(crtc); in radeon_pm_compute_clocks_old()
1709 if (radeon_crtc->enabled) { in radeon_pm_compute_clocks_old()
1710 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_old()
1769 struct radeon_crtc *radeon_crtc; in radeon_pm_compute_clocks_dpm() local
1784 radeon_crtc = to_radeon_crtc(crtc); in radeon_pm_compute_clocks_dpm()
1786 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_dpm()
1788 if (!radeon_crtc->connector) in radeon_pm_compute_clocks_dpm()
1791 radeon_connector = to_radeon_connector(radeon_crtc->connector); in radeon_pm_compute_clocks_dpm()
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| D | radeon_audio.c | 437 struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc); in radeon_audio_set_dto()
595 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_hdmi_set_color_depth() local
596 bpc = radeon_crtc->bpc; in radeon_hdmi_set_color_depth()
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| D | dce6_afmt.c | 270 struct radeon_crtc *crtc, unsigned int clock) in dce6_hdmi_audio_set_dto()
289 struct radeon_crtc *crtc, unsigned int clock) in dce6_dp_audio_set_dto()
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| D | cik.c | 8728 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in dce8_program_fmt() local
8784 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
8801 struct radeon_crtc *radeon_crtc, in dce8_line_buffer_adjust() argument
8805 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce8_line_buffer_adjust()
8814 if (radeon_crtc->base.enabled && mode) { in dce8_line_buffer_adjust()
8834 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust()
8846 if (radeon_crtc->base.enabled && mode) { in dce8_line_buffer_adjust()
9230 struct radeon_crtc *radeon_crtc, in dce8_program_watermarks() argument
9233 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce8_program_watermarks()
9240 if (radeon_crtc->base.enabled && num_heads && mode) { in dce8_program_watermarks()
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