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Searched refs:reg1 (Results 1 – 25 of 88) sorted by relevance

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/drivers/rtc/
Drtc-aspeed.c26 u32 reg1, reg2; in aspeed_rtc_read_time() local
35 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
38 tm->tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_read_time()
39 tm->tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_read_time()
40 tm->tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_read_time()
41 tm->tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_read_time()
56 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
62 reg1 = (tm->tm_mday << 24) | (tm->tm_hour << 16) | (tm->tm_min << 8) | in aspeed_rtc_set_time()
71 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
/drivers/media/dvb-frontends/
Dtua6100.c64 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; in tua6100_set_params() local
67 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; in tua6100_set_params()
82 reg1[1] = 0x2c; in tua6100_set_params()
84 reg1[1] = 0x0c; in tua6100_set_params()
87 reg1[1] |= 0x40; in tua6100_set_params()
89 reg1[1] |= 0x80; in tua6100_set_params()
107 reg1[1] |= (div >> 9) & 0x03; in tua6100_set_params()
108 reg1[2] = div >> 1; in tua6100_set_params()
109 reg1[3] = (div << 7); in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
Da8293.c21 u8 reg0, reg1; in a8293_set_voltage() local
50 reg1 = 0x82; in a8293_set_voltage()
51 if (reg1 != dev->reg[1]) { in a8293_set_voltage()
52 ret = i2c_master_send(client, &reg1, 1); in a8293_set_voltage()
55 dev->reg[1] = reg1; in a8293_set_voltage()
Dsi21xx.c222 static int si21_writeregs(struct si21xx_state *state, u8 reg1, in si21_writeregs() argument
237 msg.buf[0] = reg1; in si21_writeregs()
244 __func__, reg1, data[0], ret); in si21_writeregs()
307 static int si21_readregs(struct si21xx_state *state, u8 reg1, u8 *b, u8 len) in si21_readregs() argument
314 .buf = &reg1, in si21_readregs()
479 u8 reg1; in si21xx_init() local
486 reg1 = serit_sp1511lhb_inittab[i]; in si21xx_init()
488 if (reg1 == 0xff && val == 0xff) in si21xx_init()
490 si21_writeregs(state, reg1, &val, 1); in si21xx_init()
494 reg1 = 0x08; in si21xx_init()
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Dm88rs2000.c241 u8 reg0, reg1; in m88rs2000_send_diseqc_burst() local
246 reg1 = m88rs2000_readreg(state, 0xb2); in m88rs2000_send_diseqc_burst()
248 m88rs2000_writereg(state, 0xb2, reg1); in m88rs2000_send_diseqc_burst()
259 u8 reg0, reg1; in m88rs2000_set_tone() local
262 reg1 = m88rs2000_readreg(state, 0xb2); in m88rs2000_set_tone()
264 reg1 &= 0x3f; in m88rs2000_set_tone()
272 reg1 |= 0x80; in m88rs2000_set_tone()
277 m88rs2000_writereg(state, 0xb2, reg1); in m88rs2000_set_tone()
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv04.c49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog() argument
57 if (reg1 > 0x405c) in nv04_clk_pll_prog()
58 setPLL_double_highregs(devinit, reg1, pv); in nv04_clk_pll_prog()
60 setPLL_double_lowregs(devinit, reg1, pv); in nv04_clk_pll_prog()
62 setPLL_single(devinit, reg1, pv); in nv04_clk_pll_prog()
/drivers/gpu/drm/amd/display/dc/irq/dcn31/
Dirq_service_dcn31.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
210 .enable_reg = SRI(reg1, block, reg_num),\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
224 .enable_reg = SRI_DMUB(reg1),\
226 reg1 ## __ ## mask1 ## _MASK,\
228 reg1 ## __ ## mask1 ## _MASK,\
229 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn302/
Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 .enable_reg = SRI(reg1, block, reg_num),\
197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
214 .enable_reg = SRI_DMUB(reg1),\
216 reg1 ## __ ## mask1 ## _MASK,\
218 reg1 ## __ ## mask1 ## _MASK,\
219 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn30/
Dirq_service_dcn30.c222 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
223 .enable_reg = SRI(reg1, block, reg_num),\
225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
227 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
228 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
236 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
237 .enable_reg = SRI_DMUB(reg1),\
239 reg1 ## __ ## mask1 ## _MASK,\
241 reg1 ## __ ## mask1 ## _MASK,\
242 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c216 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
217 .enable_reg = SRI(reg1, block, reg_num),\
219 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
222 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
230 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
231 .enable_reg = SRI_DMUB(reg1),\
233 reg1 ## __ ## mask1 ## _MASK,\
235 reg1 ## __ ## mask1 ## _MASK,\
236 ~reg1 ## __ ## mask1 ## _MASK \
/drivers/mcb/
Dmcb-parse.c47 __le32 reg1; in chameleon_parse_gdd() local
54 reg1 = readl(&gdd->reg1); in chameleon_parse_gdd()
59 mdev->id = GDD_DEV(reg1); in chameleon_parse_gdd()
60 mdev->rev = GDD_REV(reg1); in chameleon_parse_gdd()
61 mdev->var = GDD_VAR(reg1); in chameleon_parse_gdd()
93 mdev->irq.start = GDD_IRQ(reg1); in chameleon_parse_gdd()
94 mdev->irq.end = GDD_IRQ(reg1); in chameleon_parse_gdd()
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c185 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) in new_ramdac580() argument
187 bool head_a = (reg1 == 0x680508); in new_ramdac580()
198 setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, in setPLL_double_highregs() argument
204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); in setPLL_double_highregs()
205 uint32_t oldpll1 = nvkm_rd32(device, reg1); in setPLL_double_highregs()
212 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); in setPLL_double_highregs()
220 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ in setPLL_double_highregs()
222 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); in setPLL_double_highregs()
246 switch (reg1) { in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/drivers/net/ethernet/netronome/nfp/bpf/
Dverifier.c85 const struct bpf_reg_state *reg1 = cur_regs(env) + BPF_REG_1; in nfp_bpf_map_update_value_ok() local
99 offmap = map_to_offmap(reg1->map_ptr); in nfp_bpf_map_update_value_ok()
159 u32 helper_tgt, const struct bpf_reg_state *reg1) in nfp_bpf_map_call_ok() argument
174 const struct bpf_reg_state *reg1 = cur_regs(env) + BPF_REG_1; in nfp_bpf_check_helper_call() local
203 bpf->helpers.map_lookup, reg1) || in nfp_bpf_check_helper_call()
211 bpf->helpers.map_update, reg1) || in nfp_bpf_check_helper_call()
221 bpf->helpers.map_delete, reg1) || in nfp_bpf_check_helper_call()
261 reg1 = cur_regs(env) + BPF_REG_4; in nfp_bpf_check_helper_call()
263 if (reg1->type != SCALAR_VALUE /* NULL ptr */ && in nfp_bpf_check_helper_call()
264 reg1->type != PTR_TO_STACK && in nfp_bpf_check_helper_call()
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn303/
Dirq_service_dcn303.c110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
111 .enable_reg = SRI(reg1, block, reg_num),\
112 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
114 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
115 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c105 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
106 .enable_reg = SRI(reg1, block, reg_num),\
108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
110 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
111 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/misc/cardreader/
Drtl8411.c41 u32 reg1 = 0; in rtl8411_fetch_vendor_settings() local
44 pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg1); in rtl8411_fetch_vendor_settings()
45 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); in rtl8411_fetch_vendor_settings()
47 if (!rtsx_vendor_setting_valid(reg1)) in rtl8411_fetch_vendor_settings()
50 pcr->aspm_en = rtsx_reg_to_aspm(reg1); in rtl8411_fetch_vendor_settings()
52 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); in rtl8411_fetch_vendor_settings()
54 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); in rtl8411_fetch_vendor_settings()
/drivers/tee/optee/
Doptee_private.h195 static inline void *reg_pair_to_ptr(u32 reg0, u32 reg1) in reg_pair_to_ptr() argument
197 return (void *)(unsigned long)(((u64)reg0 << 32) | reg1); in reg_pair_to_ptr()
200 static inline void reg_pair_from_64(u32 *reg0, u32 *reg1, u64 val) in reg_pair_from_64() argument
203 *reg1 = val; in reg_pair_from_64()
/drivers/gpu/drm/amd/display/dc/irq/dcn20/
Dirq_service_dcn20.c205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
206 .enable_reg = SRI(reg1, block, reg_num),\
208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
210 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
211 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
Dirq_service_dcn10.c203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
204 .enable_reg = SRI(reg1, block, reg_num),\
206 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
209 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/drivers/net/dsa/sja1105/
Dsja1105_dynamic_config.c585 u8 *reg1 = buf + 4; in sja1105et_mac_config_cmd_packing() local
587 sja1105_packing(reg1, &cmd->valid, 31, 31, size, op); in sja1105et_mac_config_cmd_packing()
588 sja1105_packing(reg1, &cmd->index, 26, 24, size, op); in sja1105et_mac_config_cmd_packing()
597 u8 *reg1 = buf + 4; in sja1105et_mac_config_entry_packing() local
600 sja1105_packing(reg1, &entry->speed, 30, 29, size, op); in sja1105et_mac_config_entry_packing()
601 sja1105_packing(reg1, &entry->drpdtag, 23, 23, size, op); in sja1105et_mac_config_entry_packing()
602 sja1105_packing(reg1, &entry->drpuntag, 22, 22, size, op); in sja1105et_mac_config_entry_packing()
603 sja1105_packing(reg1, &entry->retag, 21, 21, size, op); in sja1105et_mac_config_entry_packing()
604 sja1105_packing(reg1, &entry->dyn_learn, 20, 20, size, op); in sja1105et_mac_config_entry_packing()
605 sja1105_packing(reg1, &entry->egress, 19, 19, size, op); in sja1105et_mac_config_entry_packing()
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/drivers/net/ethernet/mellanox/mlxbf_gige/
Dmlxbf_gige_mdio.c88 u32 reg1, reg2; in calculate_i1clk() local
91 reg1 = readl(priv->clk_io + MLXBF_GIGE_MDIO_PLL_I1CLK_REG1); in calculate_i1clk()
94 core_f = (reg1 & MLXBF_GIGE_MDIO_CORE_F_MASK) >> in calculate_i1clk()
96 core_r = (reg1 & MLXBF_GIGE_MDIO_CORE_R_MASK) >> in calculate_i1clk()
/drivers/hwmon/
Dnct7904.c392 unsigned int reg1, reg2, reg3; in nct7904_read_temp() local
465 reg1 = LTD_HV_LL_REG; in nct7904_read_temp()
470 reg1 = LTD_LV_LL_REG; in nct7904_read_temp()
475 reg1 = LTD_HV_HL_REG; in nct7904_read_temp()
480 reg1 = LTD_LV_HL_REG; in nct7904_read_temp()
489 ret = nct7904_read_reg(data, BANK_1, reg1); in nct7904_read_temp()
569 unsigned int reg1, reg2, reg3; in nct7904_write_temp() local
575 reg1 = LTD_HV_LL_REG; in nct7904_write_temp()
580 reg1 = LTD_LV_LL_REG; in nct7904_write_temp()
585 reg1 = LTD_HV_HL_REG; in nct7904_write_temp()
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/drivers/pci/controller/
Dpcie-altera.c122 u32 reg1; member
173 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); in tlp_write_tx()
204 u32 reg0, reg1; in tlp_read_packet() local
215 reg1 = cra_readl(pcie, RP_RXCPL_REG1); in tlp_read_packet()
219 comp_status = TLP_COMP_STATUS(reg1); in tlp_read_packet()
291 tlp_rp_regdata.reg1 = headers[1]; in tlp_write_packet()
297 tlp_rp_regdata.reg1 = 0; in tlp_write_packet()
302 tlp_rp_regdata.reg1 = 0; in tlp_write_packet()
305 tlp_rp_regdata.reg1 = data; in tlp_write_packet()
/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
143 if (reg1 <= 0x405c) { in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
175 if (ret || !(reg1 = pll_lim.reg)) in nouveau_hw_get_pllvals()
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
179 if (reg1 <= 0x405c) in nouveau_hw_get_pllvals()
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
182 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); in nouveau_hw_get_pllvals()
187 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { in nouveau_hw_get_pllvals()
191 if (reg1 == NV_PRAMDAC_VPLL_COEFF) { in nouveau_hw_get_pllvals()
[all …]
/drivers/gpu/ipu-v3/
Dipu-dc.c123 u32 reg1, reg2; in dc_write_tmpl() local
126 reg1 = (operand << 20) & 0xfff00000; in dc_write_tmpl()
129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); in dc_write_tmpl()
132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); in dc_write_tmpl()
135 writel(reg1, priv->dc_tmpl_reg + word * 8); in dc_write_tmpl()

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