1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "include/logger_interface.h"
31
32 #include "../dce110/irq_service_dce110.h"
33
34 #include "dcn/dcn_1_0_offset.h"
35 #include "dcn/dcn_1_0_sh_mask.h"
36 #include "soc15_hw_ip.h"
37 #include "vega10_ip_offset.h"
38
39 #include "irq_service_dcn10.h"
40
41 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
42
to_dal_irq_source_dcn10(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)43 enum dc_irq_source to_dal_irq_source_dcn10(
44 struct irq_service *irq_service,
45 uint32_t src_id,
46 uint32_t ext_id)
47 {
48 switch (src_id) {
49 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
50 return DC_IRQ_SOURCE_VBLANK1;
51 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
52 return DC_IRQ_SOURCE_VBLANK2;
53 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
54 return DC_IRQ_SOURCE_VBLANK3;
55 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
56 return DC_IRQ_SOURCE_VBLANK4;
57 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
58 return DC_IRQ_SOURCE_VBLANK5;
59 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
60 return DC_IRQ_SOURCE_VBLANK6;
61 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
62 return DC_IRQ_SOURCE_DC1_VLINE0;
63 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
64 return DC_IRQ_SOURCE_DC2_VLINE0;
65 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
66 return DC_IRQ_SOURCE_DC3_VLINE0;
67 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
68 return DC_IRQ_SOURCE_DC4_VLINE0;
69 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
70 return DC_IRQ_SOURCE_DC5_VLINE0;
71 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
72 return DC_IRQ_SOURCE_DC6_VLINE0;
73 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
74 return DC_IRQ_SOURCE_VUPDATE1;
75 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
76 return DC_IRQ_SOURCE_VUPDATE2;
77 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
78 return DC_IRQ_SOURCE_VUPDATE3;
79 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
80 return DC_IRQ_SOURCE_VUPDATE4;
81 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
82 return DC_IRQ_SOURCE_VUPDATE5;
83 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
84 return DC_IRQ_SOURCE_VUPDATE6;
85 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
86 return DC_IRQ_SOURCE_PFLIP1;
87 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
88 return DC_IRQ_SOURCE_PFLIP2;
89 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
90 return DC_IRQ_SOURCE_PFLIP3;
91 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
92 return DC_IRQ_SOURCE_PFLIP4;
93 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
94 return DC_IRQ_SOURCE_PFLIP5;
95 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
96 return DC_IRQ_SOURCE_PFLIP6;
97
98 case DCN_1_0__SRCID__DC_HPD1_INT:
99 /* generic src_id for all HPD and HPDRX interrupts */
100 switch (ext_id) {
101 case DCN_1_0__CTXID__DC_HPD1_INT:
102 return DC_IRQ_SOURCE_HPD1;
103 case DCN_1_0__CTXID__DC_HPD2_INT:
104 return DC_IRQ_SOURCE_HPD2;
105 case DCN_1_0__CTXID__DC_HPD3_INT:
106 return DC_IRQ_SOURCE_HPD3;
107 case DCN_1_0__CTXID__DC_HPD4_INT:
108 return DC_IRQ_SOURCE_HPD4;
109 case DCN_1_0__CTXID__DC_HPD5_INT:
110 return DC_IRQ_SOURCE_HPD5;
111 case DCN_1_0__CTXID__DC_HPD6_INT:
112 return DC_IRQ_SOURCE_HPD6;
113 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
114 return DC_IRQ_SOURCE_HPD1RX;
115 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
116 return DC_IRQ_SOURCE_HPD2RX;
117 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
118 return DC_IRQ_SOURCE_HPD3RX;
119 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
120 return DC_IRQ_SOURCE_HPD4RX;
121 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
122 return DC_IRQ_SOURCE_HPD5RX;
123 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
124 return DC_IRQ_SOURCE_HPD6RX;
125 default:
126 return DC_IRQ_SOURCE_INVALID;
127 }
128 break;
129
130 default:
131 return DC_IRQ_SOURCE_INVALID;
132 }
133 }
134
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)135 static bool hpd_ack(
136 struct irq_service *irq_service,
137 const struct irq_source_info *info)
138 {
139 uint32_t addr = info->status_reg;
140 uint32_t value = dm_read_reg(irq_service->ctx, addr);
141 uint32_t current_status =
142 get_reg_field_value(
143 value,
144 HPD0_DC_HPD_INT_STATUS,
145 DC_HPD_SENSE_DELAYED);
146
147 dal_irq_service_ack_generic(irq_service, info);
148
149 value = dm_read_reg(irq_service->ctx, info->enable_reg);
150
151 set_reg_field_value(
152 value,
153 current_status ? 0 : 1,
154 HPD0_DC_HPD_INT_CONTROL,
155 DC_HPD_INT_POLARITY);
156
157 dm_write_reg(irq_service->ctx, info->enable_reg, value);
158
159 return true;
160 }
161
162 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
163 .set = NULL,
164 .ack = hpd_ack
165 };
166
167 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
168 .set = NULL,
169 .ack = NULL
170 };
171
172 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
173 .set = NULL,
174 .ack = NULL
175 };
176
177 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
178 .set = NULL,
179 .ack = NULL
180 };
181
182 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
183 .set = NULL,
184 .ack = NULL
185 };
186
187 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
188 .set = NULL,
189 .ack = NULL
190 };
191
192 #define BASE_INNER(seg) \
193 DCE_BASE__INST0_SEG ## seg
194
195 #define BASE(seg) \
196 BASE_INNER(seg)
197
198 #define SRI(reg_name, block, id)\
199 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
200 mm ## block ## id ## _ ## reg_name
201
202
203 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
204 .enable_reg = SRI(reg1, block, reg_num),\
205 .enable_mask = \
206 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
207 .enable_value = {\
208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
209 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
210 },\
211 .ack_reg = SRI(reg2, block, reg_num),\
212 .ack_mask = \
213 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
214 .ack_value = \
215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
216
217 #define hpd_int_entry(reg_num)\
218 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
219 IRQ_REG_ENTRY(HPD, reg_num,\
220 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
221 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
222 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
223 .funcs = &hpd_irq_info_funcs\
224 }
225
226 #define hpd_rx_int_entry(reg_num)\
227 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
228 IRQ_REG_ENTRY(HPD, reg_num,\
229 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
230 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
231 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
232 .funcs = &hpd_rx_irq_info_funcs\
233 }
234 #define pflip_int_entry(reg_num)\
235 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
236 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
237 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
238 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
239 .funcs = &pflip_irq_info_funcs\
240 }
241
242 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
243 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
244 */
245 #define vupdate_no_lock_int_entry(reg_num)\
246 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
247 IRQ_REG_ENTRY(OTG, reg_num,\
248 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
249 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
250 .funcs = &vupdate_no_lock_irq_info_funcs\
251 }
252
253 #define vblank_int_entry(reg_num)\
254 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
255 IRQ_REG_ENTRY(OTG, reg_num,\
256 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
257 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
258 .funcs = &vblank_irq_info_funcs\
259 }
260
261 #define vline0_int_entry(reg_num)\
262 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
263 IRQ_REG_ENTRY(OTG, reg_num,\
264 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
265 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
266 .funcs = &vline0_irq_info_funcs\
267 }
268
269 #define dummy_irq_entry() \
270 {\
271 .funcs = &dummy_irq_info_funcs\
272 }
273
274 #define i2c_int_entry(reg_num) \
275 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
276
277 #define dp_sink_int_entry(reg_num) \
278 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
279
280 #define gpio_pad_int_entry(reg_num) \
281 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
282
283 #define dc_underflow_int_entry(reg_num) \
284 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
285
286 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
287 .set = dal_irq_service_dummy_set,
288 .ack = dal_irq_service_dummy_ack
289 };
290
291 static const struct irq_source_info
292 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
293 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
294 hpd_int_entry(0),
295 hpd_int_entry(1),
296 hpd_int_entry(2),
297 hpd_int_entry(3),
298 hpd_int_entry(4),
299 hpd_int_entry(5),
300 hpd_rx_int_entry(0),
301 hpd_rx_int_entry(1),
302 hpd_rx_int_entry(2),
303 hpd_rx_int_entry(3),
304 hpd_rx_int_entry(4),
305 hpd_rx_int_entry(5),
306 i2c_int_entry(1),
307 i2c_int_entry(2),
308 i2c_int_entry(3),
309 i2c_int_entry(4),
310 i2c_int_entry(5),
311 i2c_int_entry(6),
312 dp_sink_int_entry(1),
313 dp_sink_int_entry(2),
314 dp_sink_int_entry(3),
315 dp_sink_int_entry(4),
316 dp_sink_int_entry(5),
317 dp_sink_int_entry(6),
318 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
319 pflip_int_entry(0),
320 pflip_int_entry(1),
321 pflip_int_entry(2),
322 pflip_int_entry(3),
323 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
324 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
325 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
326 gpio_pad_int_entry(0),
327 gpio_pad_int_entry(1),
328 gpio_pad_int_entry(2),
329 gpio_pad_int_entry(3),
330 gpio_pad_int_entry(4),
331 gpio_pad_int_entry(5),
332 gpio_pad_int_entry(6),
333 gpio_pad_int_entry(7),
334 gpio_pad_int_entry(8),
335 gpio_pad_int_entry(9),
336 gpio_pad_int_entry(10),
337 gpio_pad_int_entry(11),
338 gpio_pad_int_entry(12),
339 gpio_pad_int_entry(13),
340 gpio_pad_int_entry(14),
341 gpio_pad_int_entry(15),
342 gpio_pad_int_entry(16),
343 gpio_pad_int_entry(17),
344 gpio_pad_int_entry(18),
345 gpio_pad_int_entry(19),
346 gpio_pad_int_entry(20),
347 gpio_pad_int_entry(21),
348 gpio_pad_int_entry(22),
349 gpio_pad_int_entry(23),
350 gpio_pad_int_entry(24),
351 gpio_pad_int_entry(25),
352 gpio_pad_int_entry(26),
353 gpio_pad_int_entry(27),
354 gpio_pad_int_entry(28),
355 gpio_pad_int_entry(29),
356 gpio_pad_int_entry(30),
357 dc_underflow_int_entry(1),
358 dc_underflow_int_entry(2),
359 dc_underflow_int_entry(3),
360 dc_underflow_int_entry(4),
361 dc_underflow_int_entry(5),
362 dc_underflow_int_entry(6),
363 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
364 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
365 vupdate_no_lock_int_entry(0),
366 vupdate_no_lock_int_entry(1),
367 vupdate_no_lock_int_entry(2),
368 vupdate_no_lock_int_entry(3),
369 vupdate_no_lock_int_entry(4),
370 vupdate_no_lock_int_entry(5),
371 vblank_int_entry(0),
372 vblank_int_entry(1),
373 vblank_int_entry(2),
374 vblank_int_entry(3),
375 vblank_int_entry(4),
376 vblank_int_entry(5),
377 vline0_int_entry(0),
378 vline0_int_entry(1),
379 vline0_int_entry(2),
380 vline0_int_entry(3),
381 vline0_int_entry(4),
382 vline0_int_entry(5),
383 };
384
385 static const struct irq_service_funcs irq_service_funcs_dcn10 = {
386 .to_dal_irq_source = to_dal_irq_source_dcn10
387 };
388
dcn10_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)389 static void dcn10_irq_construct(
390 struct irq_service *irq_service,
391 struct irq_service_init_data *init_data)
392 {
393 dal_irq_service_construct(irq_service, init_data);
394
395 irq_service->info = irq_source_info_dcn10;
396 irq_service->funcs = &irq_service_funcs_dcn10;
397 }
398
dal_irq_service_dcn10_create(struct irq_service_init_data * init_data)399 struct irq_service *dal_irq_service_dcn10_create(
400 struct irq_service_init_data *init_data)
401 {
402 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
403 GFP_KERNEL);
404
405 if (!irq_service)
406 return NULL;
407
408 dcn10_irq_construct(irq_service, init_data);
409 return irq_service;
410 }
411