| /drivers/gpu/drm/msm/dsi/ |
| D | dsi_cfg.c | 14 .reg_cfg = {
34 .reg_cfg = {
54 .reg_cfg = {
73 .reg_cfg = {
88 .reg_cfg = {
111 .reg_cfg = {
131 .reg_cfg = {
150 .reg_cfg = {
172 .reg_cfg = {
186 .reg_cfg = {
[all …]
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| D | dsi_cfg.h | 35 struct dsi_reg_config reg_cfg; member
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| D | dsi_host.c | 254 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; in dsi_host_regulator_disable()
255 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; in dsi_host_regulator_disable()
270 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; in dsi_host_regulator_enable()
271 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; in dsi_host_regulator_enable()
304 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; in dsi_regulator_init()
305 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; in dsi_regulator_init()
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| /drivers/dma/ |
| D | ste_dma40_ll.c | 136 u32 reg_cfg, in d40_phy_fill_lli() argument
171 lli->reg_cfg = reg_cfg; in d40_phy_fill_lli()
181 lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS); in d40_phy_fill_lli()
183 lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS); in d40_phy_fill_lli()
213 dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg, in d40_phy_buf_to_lli() argument
249 reg_cfg, info, flags); in d40_phy_buf_to_lli()
270 u32 reg_cfg, in d40_phy_sg_to_lli() argument
298 reg_cfg, info, otherinfo, flags); in d40_phy_sg_to_lli()
363 u32 reg_cfg, in d40_log_fill_lli() argument
369 lli->lcsp13 = reg_cfg; in d40_log_fill_lli()
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| D | ste_dma40_ll.h | 345 u32 reg_cfg; member
446 u32 reg_cfg,
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| D | ste_dma40.c | 812 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); in d40_phy_lli_load()
817 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); in d40_phy_lli_load()
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| /drivers/gpu/drm/bridge/ |
| D | lontium-lt9611.c | 115 const struct reg_sequence reg_cfg[] = { in lt9611_mipi_input_analog() local
127 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
133 struct reg_sequence reg_cfg[] = { in lt9611_mipi_input_digital() local
143 reg_cfg[1].def = 0x03; in lt9611_mipi_input_digital()
145 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_digital()
196 const struct reg_sequence reg_cfg[] = { in lt9611_pcr_setup() local
236 regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_pcr_setup()
248 const struct reg_sequence reg_cfg[] = { in lt9611_pll_setup() local
262 regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_pll_setup()
370 struct reg_sequence reg_cfg[] = { in lt9611_hdmi_tx_phy() local
[all …]
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| /drivers/regulator/ |
| D | rtq6752-regulator.c | 222 struct regulator_config reg_cfg = {}; in rtq6752_probe() local
255 reg_cfg.dev = &i2c->dev; in rtq6752_probe()
256 reg_cfg.regmap = priv->regmap; in rtq6752_probe()
257 reg_cfg.driver_data = priv; in rtq6752_probe()
262 ®_cfg); in rtq6752_probe()
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| /drivers/ata/ |
| D | pata_octeon_cf.c | 90 union cvmx_mio_boot_reg_cfgx reg_cfg; in octeon_cf_set_boot_reg_cfg() local
108 reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); in octeon_cf_set_boot_reg_cfg()
109 reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ in octeon_cf_set_boot_reg_cfg()
110 reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */ in octeon_cf_set_boot_reg_cfg()
111 reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ in octeon_cf_set_boot_reg_cfg()
112 reg_cfg.s.sam = 0; /* Don't combine write and output enable */ in octeon_cf_set_boot_reg_cfg()
113 reg_cfg.s.we_ext = 0; /* No write enable extension */ in octeon_cf_set_boot_reg_cfg()
114 reg_cfg.s.oe_ext = 0; /* No read enable extension */ in octeon_cf_set_boot_reg_cfg()
115 reg_cfg.s.en = 1; /* Enable this region */ in octeon_cf_set_boot_reg_cfg()
116 reg_cfg.s.orbit = 0; /* Don't combine with previous region */ in octeon_cf_set_boot_reg_cfg()
[all …]
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| /drivers/iommu/ |
| D | sprd-iommu.c | 214 unsigned int reg_cfg; in sprd_iommu_hw_en() local
218 reg_cfg = SPRD_EX_CFG; in sprd_iommu_hw_en()
220 reg_cfg = SPRD_VAU_CFG; in sprd_iommu_hw_en()
224 sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val); in sprd_iommu_hw_en()
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| /drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy.c | 513 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; in dsi_phy_regulator_init()
515 int num = phy->cfg->reg_cfg.num; in dsi_phy_regulator_init()
538 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; in dsi_phy_regulator_disable()
539 int num = phy->cfg->reg_cfg.num; in dsi_phy_regulator_disable()
553 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs; in dsi_phy_regulator_enable()
555 int num = phy->cfg->reg_cfg.num; in dsi_phy_regulator_enable()
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| D | dsi_phy.h | 31 struct dsi_reg_config reg_cfg; member
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| D | dsi_phy_28nm.c | 774 .reg_cfg = {
795 .reg_cfg = {
816 .reg_cfg = {
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| D | dsi_phy_20nm.c | 134 .reg_cfg = {
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| D | dsi_phy_7nm.c | 1045 .reg_cfg = {
1072 .reg_cfg = {
1094 .reg_cfg = {
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| D | dsi_phy_10nm.c | 929 .reg_cfg = {
950 .reg_cfg = {
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| D | dsi_phy_14nm.c | 1034 .reg_cfg = {
1055 .reg_cfg = {
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| D | dsi_phy_28nm_8960.c | 653 .reg_cfg = {
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| /drivers/clk/sprd/ |
| D | pll.h | 13 struct reg_cfg { struct
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| D | pll.c | 151 struct reg_cfg *cfg; in _sprd_pll_set_rate()
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| /drivers/net/wireless/marvell/mwifiex/ |
| D | sta_cmdresp.c | 1117 struct host_cmd_ds_chan_region_cfg *reg = &resp->params.reg_cfg; in mwifiex_ret_chan_region_cfg()
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| D | fw.h | 2385 struct host_cmd_ds_chan_region_cfg reg_cfg; member
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| D | sta_cmd.c | 1614 struct host_cmd_ds_chan_region_cfg *reg = &cmd->params.reg_cfg; in mwifiex_cmd_chan_region_cfg()
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