1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Unisoc IOMMU driver
4 *
5 * Copyright (C) 2020 Unisoc, Inc.
6 * Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/errno.h>
13 #include <linux/iommu.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of_platform.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19
20 #define SPRD_IOMMU_PAGE_SHIFT 12
21 #define SPRD_IOMMU_PAGE_SIZE SZ_4K
22
23 #define SPRD_EX_CFG 0x0
24 #define SPRD_IOMMU_VAOR_BYPASS BIT(4)
25 #define SPRD_IOMMU_GATE_EN BIT(1)
26 #define SPRD_IOMMU_EN BIT(0)
27 #define SPRD_EX_UPDATE 0x4
28 #define SPRD_EX_FIRST_VPN 0x8
29 #define SPRD_EX_VPN_RANGE 0xc
30 #define SPRD_EX_FIRST_PPN 0x10
31 #define SPRD_EX_DEFAULT_PPN 0x14
32
33 #define SPRD_IOMMU_VERSION 0x0
34 #define SPRD_VERSION_MASK GENMASK(15, 8)
35 #define SPRD_VERSION_SHIFT 0x8
36 #define SPRD_VAU_CFG 0x4
37 #define SPRD_VAU_UPDATE 0x8
38 #define SPRD_VAU_AUTH_CFG 0xc
39 #define SPRD_VAU_FIRST_PPN 0x10
40 #define SPRD_VAU_DEFAULT_PPN_RD 0x14
41 #define SPRD_VAU_DEFAULT_PPN_WR 0x18
42 #define SPRD_VAU_FIRST_VPN 0x1c
43 #define SPRD_VAU_VPN_RANGE 0x20
44
45 enum sprd_iommu_version {
46 SPRD_IOMMU_EX,
47 SPRD_IOMMU_VAU,
48 };
49
50 /*
51 * struct sprd_iommu_device - high-level sprd IOMMU device representation,
52 * including hardware information and configuration, also driver data, etc
53 *
54 * @ver: sprd IOMMU IP version
55 * @prot_page_va: protect page base virtual address
56 * @prot_page_pa: protect page base physical address, data would be
57 * written to here while translation fault
58 * @base: mapped base address for accessing registers
59 * @dev: pointer to basic device structure
60 * @iommu: IOMMU core representation
61 * @group: IOMMU group
62 * @eb: gate clock which controls IOMMU access
63 */
64 struct sprd_iommu_device {
65 enum sprd_iommu_version ver;
66 u32 *prot_page_va;
67 dma_addr_t prot_page_pa;
68 void __iomem *base;
69 struct device *dev;
70 struct iommu_device iommu;
71 struct iommu_group *group;
72 struct clk *eb;
73 };
74
75 struct sprd_iommu_domain {
76 spinlock_t pgtlock; /* lock for page table */
77 struct iommu_domain domain;
78 u32 *pgt_va; /* page table virtual address base */
79 dma_addr_t pgt_pa; /* page table physical address base */
80 struct sprd_iommu_device *sdev;
81 };
82
83 static const struct iommu_ops sprd_iommu_ops;
84
to_sprd_domain(struct iommu_domain * dom)85 static struct sprd_iommu_domain *to_sprd_domain(struct iommu_domain *dom)
86 {
87 return container_of(dom, struct sprd_iommu_domain, domain);
88 }
89
90 static inline void
sprd_iommu_write(struct sprd_iommu_device * sdev,unsigned int reg,u32 val)91 sprd_iommu_write(struct sprd_iommu_device *sdev, unsigned int reg, u32 val)
92 {
93 writel_relaxed(val, sdev->base + reg);
94 }
95
96 static inline u32
sprd_iommu_read(struct sprd_iommu_device * sdev,unsigned int reg)97 sprd_iommu_read(struct sprd_iommu_device *sdev, unsigned int reg)
98 {
99 return readl_relaxed(sdev->base + reg);
100 }
101
102 static inline void
sprd_iommu_update_bits(struct sprd_iommu_device * sdev,unsigned int reg,u32 mask,u32 shift,u32 val)103 sprd_iommu_update_bits(struct sprd_iommu_device *sdev, unsigned int reg,
104 u32 mask, u32 shift, u32 val)
105 {
106 u32 t = sprd_iommu_read(sdev, reg);
107
108 t = (t & (~(mask << shift))) | ((val & mask) << shift);
109 sprd_iommu_write(sdev, reg, t);
110 }
111
112 static inline int
sprd_iommu_get_version(struct sprd_iommu_device * sdev)113 sprd_iommu_get_version(struct sprd_iommu_device *sdev)
114 {
115 int ver = (sprd_iommu_read(sdev, SPRD_IOMMU_VERSION) &
116 SPRD_VERSION_MASK) >> SPRD_VERSION_SHIFT;
117
118 switch (ver) {
119 case SPRD_IOMMU_EX:
120 case SPRD_IOMMU_VAU:
121 return ver;
122 default:
123 return -EINVAL;
124 }
125 }
126
127 static size_t
sprd_iommu_pgt_size(struct iommu_domain * domain)128 sprd_iommu_pgt_size(struct iommu_domain *domain)
129 {
130 return ((domain->geometry.aperture_end -
131 domain->geometry.aperture_start + 1) >>
132 SPRD_IOMMU_PAGE_SHIFT) * sizeof(u32);
133 }
134
sprd_iommu_domain_alloc(unsigned int domain_type)135 static struct iommu_domain *sprd_iommu_domain_alloc(unsigned int domain_type)
136 {
137 struct sprd_iommu_domain *dom;
138
139 if (domain_type != IOMMU_DOMAIN_DMA && domain_type != IOMMU_DOMAIN_UNMANAGED)
140 return NULL;
141
142 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
143 if (!dom)
144 return NULL;
145
146 spin_lock_init(&dom->pgtlock);
147
148 dom->domain.geometry.aperture_start = 0;
149 dom->domain.geometry.aperture_end = SZ_256M - 1;
150 dom->domain.geometry.force_aperture = true;
151
152 return &dom->domain;
153 }
154
sprd_iommu_first_vpn(struct sprd_iommu_domain * dom)155 static void sprd_iommu_first_vpn(struct sprd_iommu_domain *dom)
156 {
157 struct sprd_iommu_device *sdev = dom->sdev;
158 u32 val;
159 unsigned int reg;
160
161 if (sdev->ver == SPRD_IOMMU_EX)
162 reg = SPRD_EX_FIRST_VPN;
163 else
164 reg = SPRD_VAU_FIRST_VPN;
165
166 val = dom->domain.geometry.aperture_start >> SPRD_IOMMU_PAGE_SHIFT;
167 sprd_iommu_write(sdev, reg, val);
168 }
169
sprd_iommu_vpn_range(struct sprd_iommu_domain * dom)170 static void sprd_iommu_vpn_range(struct sprd_iommu_domain *dom)
171 {
172 struct sprd_iommu_device *sdev = dom->sdev;
173 u32 val;
174 unsigned int reg;
175
176 if (sdev->ver == SPRD_IOMMU_EX)
177 reg = SPRD_EX_VPN_RANGE;
178 else
179 reg = SPRD_VAU_VPN_RANGE;
180
181 val = (dom->domain.geometry.aperture_end -
182 dom->domain.geometry.aperture_start) >> SPRD_IOMMU_PAGE_SHIFT;
183 sprd_iommu_write(sdev, reg, val);
184 }
185
sprd_iommu_first_ppn(struct sprd_iommu_domain * dom)186 static void sprd_iommu_first_ppn(struct sprd_iommu_domain *dom)
187 {
188 u32 val = dom->pgt_pa >> SPRD_IOMMU_PAGE_SHIFT;
189 struct sprd_iommu_device *sdev = dom->sdev;
190 unsigned int reg;
191
192 if (sdev->ver == SPRD_IOMMU_EX)
193 reg = SPRD_EX_FIRST_PPN;
194 else
195 reg = SPRD_VAU_FIRST_PPN;
196
197 sprd_iommu_write(sdev, reg, val);
198 }
199
sprd_iommu_default_ppn(struct sprd_iommu_device * sdev)200 static void sprd_iommu_default_ppn(struct sprd_iommu_device *sdev)
201 {
202 u32 val = sdev->prot_page_pa >> SPRD_IOMMU_PAGE_SHIFT;
203
204 if (sdev->ver == SPRD_IOMMU_EX) {
205 sprd_iommu_write(sdev, SPRD_EX_DEFAULT_PPN, val);
206 } else if (sdev->ver == SPRD_IOMMU_VAU) {
207 sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_RD, val);
208 sprd_iommu_write(sdev, SPRD_VAU_DEFAULT_PPN_WR, val);
209 }
210 }
211
sprd_iommu_hw_en(struct sprd_iommu_device * sdev,bool en)212 static void sprd_iommu_hw_en(struct sprd_iommu_device *sdev, bool en)
213 {
214 unsigned int reg_cfg;
215 u32 mask, val;
216
217 if (sdev->ver == SPRD_IOMMU_EX)
218 reg_cfg = SPRD_EX_CFG;
219 else
220 reg_cfg = SPRD_VAU_CFG;
221
222 mask = SPRD_IOMMU_EN | SPRD_IOMMU_GATE_EN;
223 val = en ? mask : 0;
224 sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val);
225 }
226
sprd_iommu_cleanup(struct sprd_iommu_domain * dom)227 static void sprd_iommu_cleanup(struct sprd_iommu_domain *dom)
228 {
229 size_t pgt_size;
230
231 /* Nothing need to do if the domain hasn't been attached */
232 if (!dom->sdev)
233 return;
234
235 pgt_size = sprd_iommu_pgt_size(&dom->domain);
236 dma_free_coherent(dom->sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa);
237 dom->sdev = NULL;
238 sprd_iommu_hw_en(dom->sdev, false);
239 }
240
sprd_iommu_domain_free(struct iommu_domain * domain)241 static void sprd_iommu_domain_free(struct iommu_domain *domain)
242 {
243 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
244
245 sprd_iommu_cleanup(dom);
246 kfree(dom);
247 }
248
sprd_iommu_attach_device(struct iommu_domain * domain,struct device * dev)249 static int sprd_iommu_attach_device(struct iommu_domain *domain,
250 struct device *dev)
251 {
252 struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
253 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
254 size_t pgt_size = sprd_iommu_pgt_size(domain);
255
256 if (dom->sdev) {
257 pr_err("There's already a device attached to this domain.\n");
258 return -EINVAL;
259 }
260
261 dom->pgt_va = dma_alloc_coherent(sdev->dev, pgt_size, &dom->pgt_pa, GFP_KERNEL);
262 if (!dom->pgt_va)
263 return -ENOMEM;
264
265 dom->sdev = sdev;
266
267 sprd_iommu_first_ppn(dom);
268 sprd_iommu_first_vpn(dom);
269 sprd_iommu_vpn_range(dom);
270 sprd_iommu_default_ppn(sdev);
271 sprd_iommu_hw_en(sdev, true);
272
273 return 0;
274 }
275
sprd_iommu_detach_device(struct iommu_domain * domain,struct device * dev)276 static void sprd_iommu_detach_device(struct iommu_domain *domain,
277 struct device *dev)
278 {
279 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
280 struct sprd_iommu_device *sdev = dom->sdev;
281 size_t pgt_size = sprd_iommu_pgt_size(domain);
282
283 if (!sdev)
284 return;
285
286 dma_free_coherent(sdev->dev, pgt_size, dom->pgt_va, dom->pgt_pa);
287 sprd_iommu_hw_en(sdev, false);
288 dom->sdev = NULL;
289 }
290
sprd_iommu_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t size,int prot,gfp_t gfp)291 static int sprd_iommu_map(struct iommu_domain *domain, unsigned long iova,
292 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
293 {
294 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
295 unsigned int page_num = size >> SPRD_IOMMU_PAGE_SHIFT;
296 unsigned long flags;
297 unsigned int i;
298 u32 *pgt_base_iova;
299 u32 pabase = (u32)paddr;
300 unsigned long start = domain->geometry.aperture_start;
301 unsigned long end = domain->geometry.aperture_end;
302
303 if (!dom->sdev) {
304 pr_err("No sprd_iommu_device attached to the domain\n");
305 return -EINVAL;
306 }
307
308 if (iova < start || (iova + size) > (end + 1)) {
309 dev_err(dom->sdev->dev, "(iova(0x%lx) + size(%zx)) are not in the range!\n",
310 iova, size);
311 return -EINVAL;
312 }
313
314 pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
315
316 spin_lock_irqsave(&dom->pgtlock, flags);
317 for (i = 0; i < page_num; i++) {
318 pgt_base_iova[i] = pabase >> SPRD_IOMMU_PAGE_SHIFT;
319 pabase += SPRD_IOMMU_PAGE_SIZE;
320 }
321 spin_unlock_irqrestore(&dom->pgtlock, flags);
322
323 return 0;
324 }
325
sprd_iommu_unmap(struct iommu_domain * domain,unsigned long iova,size_t size,struct iommu_iotlb_gather * iotlb_gather)326 static size_t sprd_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
327 size_t size, struct iommu_iotlb_gather *iotlb_gather)
328 {
329 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
330 unsigned long flags;
331 u32 *pgt_base_iova;
332 unsigned int page_num = size >> SPRD_IOMMU_PAGE_SHIFT;
333 unsigned long start = domain->geometry.aperture_start;
334 unsigned long end = domain->geometry.aperture_end;
335
336 if (iova < start || (iova + size) > (end + 1))
337 return -EINVAL;
338
339 pgt_base_iova = dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT);
340
341 spin_lock_irqsave(&dom->pgtlock, flags);
342 memset(pgt_base_iova, 0, page_num * sizeof(u32));
343 spin_unlock_irqrestore(&dom->pgtlock, flags);
344
345 return 0;
346 }
347
sprd_iommu_sync_map(struct iommu_domain * domain,unsigned long iova,size_t size)348 static void sprd_iommu_sync_map(struct iommu_domain *domain,
349 unsigned long iova, size_t size)
350 {
351 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
352 unsigned int reg;
353
354 if (dom->sdev->ver == SPRD_IOMMU_EX)
355 reg = SPRD_EX_UPDATE;
356 else
357 reg = SPRD_VAU_UPDATE;
358
359 /* clear IOMMU TLB buffer after page table updated */
360 sprd_iommu_write(dom->sdev, reg, 0xffffffff);
361 }
362
sprd_iommu_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * iotlb_gather)363 static void sprd_iommu_sync(struct iommu_domain *domain,
364 struct iommu_iotlb_gather *iotlb_gather)
365 {
366 sprd_iommu_sync_map(domain, 0, 0);
367 }
368
sprd_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)369 static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain,
370 dma_addr_t iova)
371 {
372 struct sprd_iommu_domain *dom = to_sprd_domain(domain);
373 unsigned long flags;
374 phys_addr_t pa;
375 unsigned long start = domain->geometry.aperture_start;
376 unsigned long end = domain->geometry.aperture_end;
377
378 if (WARN_ON(iova < start || iova > end))
379 return 0;
380
381 spin_lock_irqsave(&dom->pgtlock, flags);
382 pa = *(dom->pgt_va + ((iova - start) >> SPRD_IOMMU_PAGE_SHIFT));
383 pa = (pa << SPRD_IOMMU_PAGE_SHIFT) + ((iova - start) & (SPRD_IOMMU_PAGE_SIZE - 1));
384 spin_unlock_irqrestore(&dom->pgtlock, flags);
385
386 return pa;
387 }
388
sprd_iommu_probe_device(struct device * dev)389 static struct iommu_device *sprd_iommu_probe_device(struct device *dev)
390 {
391 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
392 struct sprd_iommu_device *sdev;
393
394 if (!fwspec || fwspec->ops != &sprd_iommu_ops)
395 return ERR_PTR(-ENODEV);
396
397 sdev = dev_iommu_priv_get(dev);
398
399 return &sdev->iommu;
400 }
401
sprd_iommu_release_device(struct device * dev)402 static void sprd_iommu_release_device(struct device *dev)
403 {
404 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
405
406 if (!fwspec || fwspec->ops != &sprd_iommu_ops)
407 return;
408
409 iommu_fwspec_free(dev);
410 }
411
sprd_iommu_device_group(struct device * dev)412 static struct iommu_group *sprd_iommu_device_group(struct device *dev)
413 {
414 struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev);
415
416 return iommu_group_ref_get(sdev->group);
417 }
418
sprd_iommu_of_xlate(struct device * dev,struct of_phandle_args * args)419 static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
420 {
421 struct platform_device *pdev;
422
423 if (!dev_iommu_priv_get(dev)) {
424 pdev = of_find_device_by_node(args->np);
425 dev_iommu_priv_set(dev, platform_get_drvdata(pdev));
426 platform_device_put(pdev);
427 }
428
429 return 0;
430 }
431
432
433 static const struct iommu_ops sprd_iommu_ops = {
434 .domain_alloc = sprd_iommu_domain_alloc,
435 .domain_free = sprd_iommu_domain_free,
436 .attach_dev = sprd_iommu_attach_device,
437 .detach_dev = sprd_iommu_detach_device,
438 .map = sprd_iommu_map,
439 .unmap = sprd_iommu_unmap,
440 .iotlb_sync_map = sprd_iommu_sync_map,
441 .iotlb_sync = sprd_iommu_sync,
442 .iova_to_phys = sprd_iommu_iova_to_phys,
443 .probe_device = sprd_iommu_probe_device,
444 .release_device = sprd_iommu_release_device,
445 .device_group = sprd_iommu_device_group,
446 .of_xlate = sprd_iommu_of_xlate,
447 .pgsize_bitmap = ~0UL << SPRD_IOMMU_PAGE_SHIFT,
448 .owner = THIS_MODULE,
449 };
450
451 static const struct of_device_id sprd_iommu_of_match[] = {
452 { .compatible = "sprd,iommu-v1" },
453 { },
454 };
455 MODULE_DEVICE_TABLE(of, sprd_iommu_of_match);
456
457 /*
458 * Clock is not required, access to some of IOMMUs is controlled by gate
459 * clk, enabled clocks for that kind of IOMMUs before accessing.
460 * Return 0 for success or no clocks found.
461 */
sprd_iommu_clk_enable(struct sprd_iommu_device * sdev)462 static int sprd_iommu_clk_enable(struct sprd_iommu_device *sdev)
463 {
464 struct clk *eb;
465
466 eb = devm_clk_get_optional(sdev->dev, NULL);
467 if (!eb)
468 return 0;
469
470 if (IS_ERR(eb))
471 return PTR_ERR(eb);
472
473 sdev->eb = eb;
474 return clk_prepare_enable(eb);
475 }
476
sprd_iommu_clk_disable(struct sprd_iommu_device * sdev)477 static void sprd_iommu_clk_disable(struct sprd_iommu_device *sdev)
478 {
479 if (sdev->eb)
480 clk_disable_unprepare(sdev->eb);
481 }
482
sprd_iommu_probe(struct platform_device * pdev)483 static int sprd_iommu_probe(struct platform_device *pdev)
484 {
485 struct sprd_iommu_device *sdev;
486 struct device *dev = &pdev->dev;
487 void __iomem *base;
488 int ret;
489
490 sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL);
491 if (!sdev)
492 return -ENOMEM;
493
494 base = devm_platform_ioremap_resource(pdev, 0);
495 if (IS_ERR(base)) {
496 dev_err(dev, "Failed to get ioremap resource.\n");
497 return PTR_ERR(base);
498 }
499 sdev->base = base;
500
501 sdev->prot_page_va = dma_alloc_coherent(dev, SPRD_IOMMU_PAGE_SIZE,
502 &sdev->prot_page_pa, GFP_KERNEL);
503 if (!sdev->prot_page_va)
504 return -ENOMEM;
505
506 platform_set_drvdata(pdev, sdev);
507 sdev->dev = dev;
508
509 /* All the client devices are in the same iommu-group */
510 sdev->group = iommu_group_alloc();
511 if (IS_ERR(sdev->group)) {
512 ret = PTR_ERR(sdev->group);
513 goto free_page;
514 }
515
516 ret = iommu_device_sysfs_add(&sdev->iommu, dev, NULL, dev_name(dev));
517 if (ret)
518 goto put_group;
519
520 ret = iommu_device_register(&sdev->iommu, &sprd_iommu_ops, dev);
521 if (ret)
522 goto remove_sysfs;
523
524 if (!iommu_present(&platform_bus_type))
525 bus_set_iommu(&platform_bus_type, &sprd_iommu_ops);
526
527 ret = sprd_iommu_clk_enable(sdev);
528 if (ret)
529 goto unregister_iommu;
530
531 ret = sprd_iommu_get_version(sdev);
532 if (ret < 0) {
533 dev_err(dev, "IOMMU version(%d) is invalid.\n", ret);
534 goto disable_clk;
535 }
536 sdev->ver = ret;
537
538 return 0;
539
540 disable_clk:
541 sprd_iommu_clk_disable(sdev);
542 unregister_iommu:
543 iommu_device_unregister(&sdev->iommu);
544 remove_sysfs:
545 iommu_device_sysfs_remove(&sdev->iommu);
546 put_group:
547 iommu_group_put(sdev->group);
548 free_page:
549 dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
550 return ret;
551 }
552
sprd_iommu_remove(struct platform_device * pdev)553 static int sprd_iommu_remove(struct platform_device *pdev)
554 {
555 struct sprd_iommu_device *sdev = platform_get_drvdata(pdev);
556
557 dma_free_coherent(sdev->dev, SPRD_IOMMU_PAGE_SIZE, sdev->prot_page_va, sdev->prot_page_pa);
558
559 iommu_group_put(sdev->group);
560 sdev->group = NULL;
561
562 bus_set_iommu(&platform_bus_type, NULL);
563
564 platform_set_drvdata(pdev, NULL);
565 iommu_device_sysfs_remove(&sdev->iommu);
566 iommu_device_unregister(&sdev->iommu);
567
568 return 0;
569 }
570
571 static struct platform_driver sprd_iommu_driver = {
572 .driver = {
573 .name = "sprd-iommu",
574 .of_match_table = sprd_iommu_of_match,
575 .suppress_bind_attrs = true,
576 },
577 .probe = sprd_iommu_probe,
578 .remove = sprd_iommu_remove,
579 };
580 module_platform_driver(sprd_iommu_driver);
581
582 MODULE_DESCRIPTION("IOMMU driver for Unisoc SoCs");
583 MODULE_ALIAS("platform:sprd-iommu");
584 MODULE_LICENSE("GPL");
585