Home
last modified time | relevance | path

Searched refs:reg_read (Results 1 – 25 of 167) sorted by relevance

1234567

/drivers/base/regmap/
Dregmap-mmio.c26 unsigned int (*reg_read)(struct regmap_mmio_context *ctx, member
236 *val = ctx->reg_read(ctx, reg); in regmap_mmio_read()
259 .reg_read = regmap_mmio_read,
305 ctx->reg_read = regmap_mmio_read8_relaxed; in regmap_mmio_gen_context()
308 ctx->reg_read = regmap_mmio_read8; in regmap_mmio_gen_context()
314 ctx->reg_read = regmap_mmio_read16le_relaxed; in regmap_mmio_gen_context()
317 ctx->reg_read = regmap_mmio_read16le; in regmap_mmio_gen_context()
323 ctx->reg_read = regmap_mmio_read32le_relaxed; in regmap_mmio_gen_context()
326 ctx->reg_read = regmap_mmio_read32le; in regmap_mmio_gen_context()
333 ctx->reg_read = regmap_mmio_read64le_relaxed; in regmap_mmio_gen_context()
[all …]
Dregmap-w1.c176 .reg_read = w1_reg_a8_v8_read,
181 .reg_read = w1_reg_a8_v16_read,
186 .reg_read = w1_reg_a16_v16_read,
Dregmap-mdio.c52 .reg_read = regmap_mdio_c22_read,
77 .reg_read = regmap_mdio_c45_read,
Dregmap-i2c.c48 .reg_read = regmap_smbus_byte_reg_read,
84 .reg_read = regmap_smbus_word_reg_read,
120 .reg_read = regmap_smbus_word_read_swapped,
/drivers/firewire/
Dinit_ohci1394_dma.c45 static inline u32 reg_read(const struct ohci *ohci, int offset) in reg_read() function
61 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000) in get_phy_reg()
65 r = reg_read(ohci, OHCI1394_PhyControl); in get_phy_reg()
78 if (!(reg_read(ohci, OHCI1394_PhyControl) & 0x00004000)) in set_phy_reg()
92 if (!(reg_read(ohci, OHCI1394_HCControlSet) in init_ohci1394_soft_reset()
110 bus_options = reg_read(ohci, OHCI1394_BusOptions); in init_ohci1394_initialize()
183 events = reg_read(ohci, OHCI1394_IntEventSet); in init_ohci1394_wait_for_busresets()
Dohci.c577 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) in reg_read() function
585 reg_read(ohci, OHCI1394_Version); in flush_writes()
601 val = reg_read(ohci, OHCI1394_PhyControl); in read_phy_reg()
628 val = reg_read(ohci, OHCI1394_PhyControl); in write_phy_reg()
738 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { in ar_context_abort()
1309 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); in context_stop()
1616 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { in handle_local_lock()
1617 lock_old = cpu_to_be32(reg_read(ohci, in handle_local_lock()
1698 ctl = reg_read(ohci, CONTROL_SET(regs)); in detect_dead_context()
1764 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); in get_cycle_time()
[all …]
/drivers/i3c/master/mipi-i3c-hci/
Dcore.c30 #define reg_read(r) readl(hci->base_regs + (r)) macro
32 #define reg_set(r, v) reg_write(r, reg_read(r) | (v))
33 #define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v))
156 DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL)); in i3c_hci_bus_init()
176 reg_write(HC_CONTROL, reg_read(HC_CONTROL)); in mipi_i3c_hci_resume()
549 val = reg_read(INTR_STATUS); in i3c_hci_irq_handler()
589 regval = reg_read(HCI_VERSION); in i3c_hci_init()
606 hci->caps = reg_read(HC_CAPABILITIES); in i3c_hci_init()
609 regval = reg_read(DAT_SECTION); in i3c_hci_init()
617 regval = reg_read(DCT_SECTION); in i3c_hci_init()
[all …]
/drivers/media/pci/tw686x/
Dtw686x-core.c95 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); in tw686x_disable_channel()
96 u32 dma_cmd = reg_read(dev, DMA_CMD); in tw686x_disable_channel()
114 u32 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); in tw686x_enable_channel()
115 u32 dma_cmd = reg_read(dev, DMA_CMD); in tw686x_enable_channel()
145 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); in tw686x_reset_channels()
146 dma_cmd = reg_read(dev, DMA_CMD); in tw686x_reset_channels()
173 int_status = reg_read(dev, INT_STATUS); /* cleared on read */ in tw686x_irq()
174 fifo_status = reg_read(dev, VIDEO_FIFO_STATUS); in tw686x_irq()
188 dma_en = reg_read(dev, DMA_CHANNEL_ENABLE); in tw686x_irq()
200 pb_status = reg_read(dev, PB_STATUS); in tw686x_irq()
/drivers/media/i2c/
Dak881x.c35 static int reg_read(struct i2c_client *client, const u8 reg) in reg_read() function
49 int ret = reg_read(client, reg); in reg_set()
70 reg->val = reg_read(client, reg->reg); in ak881x_g_register()
193 reg_read(client, AK881X_STATUS)); in ak881x_s_stream()
198 reg_read(client, AK881X_STATUS)); in ak881x_s_stream()
248 data = reg_read(client, AK881X_DEVICE_ID); in ak881x_probe()
260 ak881x->revision = reg_read(client, AK881X_DEVICE_REVISION); in ak881x_probe()
Dmt9m001.c115 static int reg_read(struct i2c_client *client, const u8 reg) in reg_read() function
131 ret = reg_read(client, reg); in reg_set()
142 ret = reg_read(client, reg); in reg_clear()
428 reg->val = reg_read(client, reg->reg); in mt9m001_g_register()
549 reg_read(client, MT9M001_GLOBAL_GAIN), data); in mt9m001_s_ctrl()
562 reg_read(client, MT9M001_SHUTTER_WIDTH), shutter); in mt9m001_s_ctrl()
596 data = reg_read(client, MT9M001_CHIP_VERSION); in mt9m001_video_probe()
Drj54n1cb0c.c430 static int reg_read(struct i2c_client *client, const u16 reg) in reg_read() function
469 ret = reg_read(client, reg); in reg_set()
887 ret = reg_read(client, RJ54N1_CLK_RST); in rj54n1_set_clock()
944 ret = reg_read(client, RJ54N1_WB_SEL_WEIGHT_I); in rj54n1_reg_init()
1020 ret = reg_read(client, RJ54N1_RESET_STANDBY); in rj54n1_set_fmt()
1139 reg->val = reg_read(client, reg->reg); in rj54n1_g_register()
1275 data1 = reg_read(client, RJ54N1_DEV_CODE); in rj54n1_video_probe()
1276 data2 = reg_read(client, RJ54N1_DEV_CODE2); in rj54n1_video_probe()
/drivers/soundwire/
Dqcom.c153 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); member
256 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in swrm_wait_for_rd_fifo_avail()
281 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in swrm_wait_for_wr_fifo_avail()
371 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
402 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_alert_slave_dev_num()
421 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
439 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); in qcom_swrm_set_slave_dev_num()
469 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); in qcom_swrm_enumerate()
472 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); in qcom_swrm_enumerate()
510 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); in qcom_swrm_irq_handler()
[all …]
/drivers/media/usb/gspca/
Dspca508.c1250 static int reg_read(struct gspca_dev *gspca_dev, in reg_read() function
1297 ret = reg_read(gspca_dev, 0x8803); in ssi_w()
1358 data1 = reg_read(gspca_dev, 0x8104); in sd_config()
1359 data2 = reg_read(gspca_dev, 0x8105); in sd_config()
1363 data1 = reg_read(gspca_dev, 0x8106); in sd_config()
1364 data2 = reg_read(gspca_dev, 0x8107); in sd_config()
1368 data1 = reg_read(gspca_dev, 0x8621); in sd_config()
/drivers/media/dvb-frontends/
Dtc90522.c66 static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len) in reg_read() function
131 ret = reg_read(state, 0xc3, &reg, 1); in tc90522s_read_status()
146 if (reg_read(state, 0xc5, &reg, 1) < 0 || !(reg & 0x03)) in tc90522s_read_status()
159 ret = reg_read(state, 0x96, &reg, 1); in tc90522t_read_status()
170 ret = reg_read(state, 0x80, &reg, 1); in tc90522t_read_status()
210 ret = reg_read(state, 0xe6, val, 5); in tc90522s_get_frontend()
254 ret = reg_read(state, 0xbc, val, 2); in tc90522s_get_frontend()
285 ret = reg_read(state, 0xeb, val, 10); in tc90522s_get_frontend()
344 ret = reg_read(state, 0xb0, val, 1); in tc90522t_get_frontend()
351 ret = reg_read(state, 0xb2, val, 6); in tc90522t_get_frontend()
[all …]
/drivers/media/tuners/
Dmxl301rf.c52 static int reg_read(struct mxl301rf_state *state, u8 reg, u8 *val) in reg_read() function
88 ret = reg_read(state, 0x18, &rf_in1); in mxl301rf_get_rf_strength()
90 ret = reg_read(state, 0x19, &rf_in2); in mxl301rf_get_rf_strength()
92 ret = reg_read(state, 0xd6, &rf_off1); in mxl301rf_get_rf_strength()
94 ret = reg_read(state, 0xd7, &rf_off2); in mxl301rf_get_rf_strength()
/drivers/net/dsa/
Dmv88e6060.c17 static int reg_read(struct mv88e6060_priv *priv, int addr, int reg) in reg_read() function
60 ret = reg_read(priv, REG_PORT(i), PORT_CONTROL); in mv88e6060_switch_reset()
82 ret = reg_read(priv, REG_GLOBAL, GLOBAL_STATUS); in mv88e6060_switch_reset()
234 return reg_read(priv, addr, regnum); in mv88e6060_phy_read()
/drivers/media/pci/sta2x11/
Dsta2x11_vip.c208 static inline u32 reg_read(struct sta2x11_vip *vip, unsigned int reg) in reg_read() function
222 reg_write(vip, DVP_CTL, reg_read(vip, DVP_CTL) | DVP_CTL_ENA); in start_dma()
353 reg_write(vip, DVP_CTL, reg_read(vip, DVP_CTL) & ~DVP_CTL_ENA); in stop_streaming()
777 status = reg_read(vip, DVP_ITS); in vip_irq()
802 reg_write(vip, DVP_CTL, reg_read(vip, DVP_CTL) & ~DVP_CTL_ENA); in vip_irq()
817 reg_read(vip, DVP_ITS); in sta2x11_vip_init_register()
836 reg_read(vip, DVP_ITS); in sta2x11_vip_clear_register()
1186 vip->register_save_area[0] = reg_read(vip, DVP_CTL); in sta2x11_vip_suspend()
1188 vip->register_save_area[SAVE_COUNT] = reg_read(vip, DVP_ITM); in sta2x11_vip_suspend()
1191 vip->register_save_area[i] = reg_read(vip, 4 * i); in sta2x11_vip_suspend()
[all …]
/drivers/gpu/drm/stm/
Dltdc.c242 static inline u32 reg_read(void __iomem *base, u32 reg) in reg_read() function
254 reg_write(base, reg, reg_read(base, reg) | mask); in reg_set()
259 reg_write(base, reg, reg_read(base, reg) & ~mask); in reg_clear()
265 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); in reg_update_bits()
394 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); in ltdc_irq()
687 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; in ltdc_crtc_get_scanout_position()
688 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; in ltdc_crtc_get_scanout_position()
689 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; in ltdc_crtc_get_scanout_position()
690 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; in ltdc_crtc_get_scanout_position()
816 bpcr = reg_read(ldev->regs, LTDC_BPCR); in ltdc_plane_atomic_update()
[all …]
/drivers/nvmem/
Dsunxi_sid.c152 nvmem_cfg->reg_read = sun8i_sid_read_by_reg; in sunxi_sid_probe()
154 nvmem_cfg->reg_read = sunxi_sid_read; in sunxi_sid_probe()
164 nvmem_cfg->reg_read(sid, 0, randomness, size); in sunxi_sid_probe()
Dstm32-romem.c167 priv->cfg.reg_read = stm32_romem_read; in stm32_romem_probe()
170 priv->cfg.reg_read = stm32_bsec_read; in stm32_romem_probe()
/drivers/thunderbolt/
Dnvm.c57 int tb_nvm_add_active(struct tb_nvm *nvm, size_t size, nvmem_reg_read_t reg_read) in tb_nvm_add_active() argument
65 config.reg_read = reg_read; in tb_nvm_add_active()
/drivers/i2c/busses/
Di2c-pasemi.c59 static inline int reg_read(struct pasemi_smbus *smbus, int reg) in reg_read() function
69 #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO)
75 status = reg_read(smbus, REG_SMSTA); in pasemi_smb_clear()
84 status = reg_read(smbus, REG_SMSTA); in pasemi_smb_waitready()
88 status = reg_read(smbus, REG_SMSTA); in pasemi_smb_waitready()
/drivers/iio/adc/
Dad7606_spi.c166 readval = st->bops->reg_read(st, addr); in ad7606_spi_write_mask()
291 .reg_read = ad7606_spi_reg_read,
300 .reg_read = ad7606_spi_reg_read,
/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.c84 reg_val = srv->funcs.reg_read(srv->user_ctx, addr); in dmub_reg_update()
107 uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr); in dmub_reg_get()
/drivers/gpu/drm/i2c/
Dtda998x_drv.c638 reg_read(struct tda998x_priv *priv, u16 reg) in reg_read() function
692 old_val = reg_read(priv, reg); in reg_set()
702 old_val = reg_read(priv, reg); in reg_clear()
798 flag0 = reg_read(priv, REG_INT_FLAGS_0); in tda998x_irq_thread()
799 flag1 = reg_read(priv, REG_INT_FLAGS_1); in tda998x_irq_thread()
800 flag2 = reg_read(priv, REG_INT_FLAGS_2); in tda998x_irq_thread()
1252 ret = reg_read(priv, REG_INT_FLAGS_2); in read_edid_block()
1846 rev_lo = reg_read(priv, REG_VERSION_LSB); in tda998x_create()
1852 rev_hi = reg_read(priv, REG_VERSION_MSB); in tda998x_create()
1899 reg_read(priv, REG_INT_FLAGS_0); in tda998x_create()
[all …]

1234567