1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019, Linaro Limited
3
4 #include <linux/clk.h>
5 #include <linux/completion.h>
6 #include <linux/interrupt.h>
7 #include <linux/io.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_irq.h>
12 #include <linux/of_device.h>
13 #include <linux/regmap.h>
14 #include <linux/slab.h>
15 #include <linux/slimbus.h>
16 #include <linux/soundwire/sdw.h>
17 #include <linux/soundwire/sdw_registers.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc.h>
20 #include "bus.h"
21
22 #define SWRM_COMP_HW_VERSION 0x00
23 #define SWRM_COMP_CFG_ADDR 0x04
24 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
25 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
26 #define SWRM_COMP_PARAMS 0x100
27 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10)
28 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
29 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
30 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
31 #define SWRM_INTERRUPT_STATUS 0x200
32 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
33 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
34 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
35 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
36 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3)
37 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4)
38 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5)
39 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6)
40 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
41 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8)
42 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9)
43 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
44 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13)
45 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14)
46 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16)
47 #define SWRM_INTERRUPT_MAX 17
48 #define SWRM_INTERRUPT_MASK_ADDR 0x204
49 #define SWRM_INTERRUPT_CLEAR 0x208
50 #define SWRM_INTERRUPT_CPU_EN 0x210
51 #define SWRM_CMD_FIFO_WR_CMD 0x300
52 #define SWRM_CMD_FIFO_RD_CMD 0x304
53 #define SWRM_CMD_FIFO_CMD 0x308
54 #define SWRM_CMD_FIFO_FLUSH 0x1
55 #define SWRM_CMD_FIFO_STATUS 0x30C
56 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)
57 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)
58 #define SWRM_CMD_FIFO_CFG_ADDR 0x314
59 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
60 #define SWRM_RD_WR_CMD_RETRIES 0x7
61 #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
62 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
63 #define SWRM_ENUMERATOR_CFG_ADDR 0x500
64 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
65 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
66 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
67 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
68 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
69 #define SWRM_MCP_BUS_CTRL 0x1044
70 #define SWRM_MCP_BUS_CLK_START BIT(1)
71 #define SWRM_MCP_CFG_ADDR 0x1048
72 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
73 #define SWRM_DEF_CMD_NO_PINGS 0x1f
74 #define SWRM_MCP_STATUS 0x104C
75 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
76 #define SWRM_MCP_SLV_STATUS 0x1090
77 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
78 #define SWRM_MCP_SLV_STATUS_SZ 2
79 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
80 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
81 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
82 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
83 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
84 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
85 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
86
87 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
88 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
89 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
90 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
91 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
92 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
93 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
94
95 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \
96 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
97
98 #define SWRM_SPECIAL_CMD_ID 0xF
99 #define MAX_FREQ_NUM 1
100 #define TIMEOUT_MS 100
101 #define QCOM_SWRM_MAX_RD_LEN 0x1
102 #define QCOM_SDW_MAX_PORTS 14
103 #define DEFAULT_CLK_FREQ 9600000
104 #define SWRM_MAX_DAIS 0xF
105 #define SWR_INVALID_PARAM 0xFF
106 #define SWR_HSTOP_MAX_VAL 0xF
107 #define SWR_HSTART_MIN_VAL 0x0
108 #define SWR_BROADCAST_CMD_ID 0x0F
109 #define SWR_MAX_CMD_ID 14
110 #define MAX_FIFO_RD_RETRY 3
111 #define SWR_OVERFLOW_RETRY_COUNT 30
112
113 struct qcom_swrm_port_config {
114 u8 si;
115 u8 off1;
116 u8 off2;
117 u8 bp_mode;
118 u8 hstart;
119 u8 hstop;
120 u8 word_length;
121 u8 blk_group_count;
122 u8 lane_control;
123 };
124
125 struct qcom_swrm_ctrl {
126 struct sdw_bus bus;
127 struct device *dev;
128 struct regmap *regmap;
129 void __iomem *mmio;
130 struct completion broadcast;
131 struct completion enumeration;
132 struct work_struct slave_work;
133 /* Port alloc/free lock */
134 struct mutex port_lock;
135 struct clk *hclk;
136 u8 wr_cmd_id;
137 u8 rd_cmd_id;
138 int irq;
139 unsigned int version;
140 int num_din_ports;
141 int num_dout_ports;
142 int cols_index;
143 int rows_index;
144 unsigned long dout_port_mask;
145 unsigned long din_port_mask;
146 u32 intr_mask;
147 u8 rcmd_id;
148 u8 wcmd_id;
149 /* Port numbers are 1 - 14 */
150 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS + 1];
151 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
152 enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
153 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
154 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
155 u32 slave_status;
156 u32 wr_fifo_depth;
157 u32 rd_fifo_depth;
158 };
159
160 struct qcom_swrm_data {
161 u32 default_cols;
162 u32 default_rows;
163 };
164
165 static struct qcom_swrm_data swrm_v1_3_data = {
166 .default_rows = 48,
167 .default_cols = 16,
168 };
169
170 static struct qcom_swrm_data swrm_v1_5_data = {
171 .default_rows = 50,
172 .default_cols = 16,
173 };
174
175 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
176
qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl * ctrl,int reg,u32 * val)177 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
178 u32 *val)
179 {
180 struct regmap *wcd_regmap = ctrl->regmap;
181 int ret;
182
183 /* pg register + offset */
184 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
185 (u8 *)®, 4);
186 if (ret < 0)
187 return SDW_CMD_FAIL;
188
189 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
190 val, 4);
191 if (ret < 0)
192 return SDW_CMD_FAIL;
193
194 return SDW_CMD_OK;
195 }
196
qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl * ctrl,int reg,int val)197 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
198 int reg, int val)
199 {
200 struct regmap *wcd_regmap = ctrl->regmap;
201 int ret;
202 /* pg register + offset */
203 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
204 (u8 *)&val, 4);
205 if (ret)
206 return SDW_CMD_FAIL;
207
208 /* write address register */
209 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
210 (u8 *)®, 4);
211 if (ret)
212 return SDW_CMD_FAIL;
213
214 return SDW_CMD_OK;
215 }
216
qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl * ctrl,int reg,u32 * val)217 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
218 u32 *val)
219 {
220 *val = readl(ctrl->mmio + reg);
221 return SDW_CMD_OK;
222 }
223
qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl * ctrl,int reg,int val)224 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
225 int val)
226 {
227 writel(val, ctrl->mmio + reg);
228 return SDW_CMD_OK;
229 }
230
swrm_get_packed_reg_val(u8 * cmd_id,u8 cmd_data,u8 dev_addr,u16 reg_addr)231 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
232 u8 dev_addr, u16 reg_addr)
233 {
234 u32 val;
235 u8 id = *cmd_id;
236
237 if (id != SWR_BROADCAST_CMD_ID) {
238 if (id < SWR_MAX_CMD_ID)
239 id += 1;
240 else
241 id = 0;
242 *cmd_id = id;
243 }
244 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
245
246 return val;
247 }
248
swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl * swrm)249 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
250 {
251 u32 fifo_outstanding_data, value;
252 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
253
254 do {
255 /* Check for fifo underflow during read */
256 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
257 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
258
259 /* Check if read data is available in read fifo */
260 if (fifo_outstanding_data > 0)
261 return 0;
262
263 usleep_range(500, 510);
264 } while (fifo_retry_count--);
265
266 if (fifo_outstanding_data == 0) {
267 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
268 return -EIO;
269 }
270
271 return 0;
272 }
273
swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl * swrm)274 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
275 {
276 u32 fifo_outstanding_cmds, value;
277 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
278
279 do {
280 /* Check for fifo overflow during write */
281 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
282 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
283
284 /* Check for space in write fifo before writing */
285 if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
286 return 0;
287
288 usleep_range(500, 510);
289 } while (fifo_retry_count--);
290
291 if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
292 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
293 return -EIO;
294 }
295
296 return 0;
297 }
298
qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl * swrm,u8 cmd_data,u8 dev_addr,u16 reg_addr)299 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
300 u8 dev_addr, u16 reg_addr)
301 {
302
303 u32 val;
304 int ret = 0;
305 u8 cmd_id = 0x0;
306
307 if (dev_addr == SDW_BROADCAST_DEV_NUM) {
308 cmd_id = SWR_BROADCAST_CMD_ID;
309 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
310 dev_addr, reg_addr);
311 } else {
312 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
313 dev_addr, reg_addr);
314 }
315
316 if (swrm_wait_for_wr_fifo_avail(swrm))
317 return SDW_CMD_FAIL_OTHER;
318
319 if (cmd_id == SWR_BROADCAST_CMD_ID)
320 reinit_completion(&swrm->broadcast);
321
322 /* Its assumed that write is okay as we do not get any status back */
323 swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
324
325 /* version 1.3 or less */
326 if (swrm->version <= 0x01030000)
327 usleep_range(150, 155);
328
329 if (cmd_id == SWR_BROADCAST_CMD_ID) {
330 /*
331 * sleep for 10ms for MSM soundwire variant to allow broadcast
332 * command to complete.
333 */
334 ret = wait_for_completion_timeout(&swrm->broadcast,
335 msecs_to_jiffies(TIMEOUT_MS));
336 if (!ret)
337 ret = SDW_CMD_IGNORED;
338 else
339 ret = SDW_CMD_OK;
340
341 } else {
342 ret = SDW_CMD_OK;
343 }
344 return ret;
345 }
346
qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl * swrm,u8 dev_addr,u16 reg_addr,u32 len,u8 * rval)347 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
348 u8 dev_addr, u16 reg_addr,
349 u32 len, u8 *rval)
350 {
351 u32 cmd_data, cmd_id, val, retry_attempt = 0;
352
353 val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
354
355 /*
356 * Check for outstanding cmd wrt. write fifo depth to avoid
357 * overflow as read will also increase write fifo cnt.
358 */
359 swrm_wait_for_wr_fifo_avail(swrm);
360
361 /* wait for FIFO RD to complete to avoid overflow */
362 usleep_range(100, 105);
363 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
364 /* wait for FIFO RD CMD complete to avoid overflow */
365 usleep_range(250, 255);
366
367 if (swrm_wait_for_rd_fifo_avail(swrm))
368 return SDW_CMD_FAIL_OTHER;
369
370 do {
371 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
372 rval[0] = cmd_data & 0xFF;
373 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
374
375 if (cmd_id != swrm->rcmd_id) {
376 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
377 /* wait 500 us before retry on fifo read failure */
378 usleep_range(500, 505);
379 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
380 SWRM_CMD_FIFO_FLUSH);
381 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
382 }
383 retry_attempt++;
384 } else {
385 return SDW_CMD_OK;
386 }
387
388 } while (retry_attempt < MAX_FIFO_RD_RETRY);
389
390 dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
391 dev_num: 0x%x, cmd_data: 0x%x\n",
392 reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
393
394 return SDW_CMD_IGNORED;
395 }
396
qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl * ctrl)397 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
398 {
399 u32 val, status;
400 int dev_num;
401
402 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
403
404 for (dev_num = 0; dev_num <= SDW_MAX_DEVICES; dev_num++) {
405 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
406
407 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
408 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK;
409 return dev_num;
410 }
411 }
412
413 return -EINVAL;
414 }
415
qcom_swrm_get_device_status(struct qcom_swrm_ctrl * ctrl)416 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
417 {
418 u32 val;
419 int i;
420
421 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
422 ctrl->slave_status = val;
423
424 for (i = 0; i <= SDW_MAX_DEVICES; i++) {
425 u32 s;
426
427 s = (val >> (i * 2));
428 s &= SWRM_MCP_SLV_STATUS_MASK;
429 ctrl->status[i] = s;
430 }
431 }
432
qcom_swrm_set_slave_dev_num(struct sdw_bus * bus,struct sdw_slave * slave,int devnum)433 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
434 struct sdw_slave *slave, int devnum)
435 {
436 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
437 u32 status;
438
439 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
440 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
441 status &= SWRM_MCP_SLV_STATUS_MASK;
442
443 if (status == SDW_SLAVE_ATTACHED) {
444 if (slave)
445 slave->dev_num = devnum;
446 mutex_lock(&bus->bus_lock);
447 set_bit(devnum, bus->assigned);
448 mutex_unlock(&bus->bus_lock);
449 }
450 }
451
qcom_swrm_enumerate(struct sdw_bus * bus)452 static int qcom_swrm_enumerate(struct sdw_bus *bus)
453 {
454 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
455 struct sdw_slave *slave, *_s;
456 struct sdw_slave_id id;
457 u32 val1, val2;
458 bool found;
459 u64 addr;
460 int i;
461 char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
462
463 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
464 /* do not continue if the status is Not Present */
465 if (!ctrl->status[i])
466 continue;
467
468 /*SCP_Devid5 - Devid 4*/
469 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
470
471 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
472 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
473
474 if (!val1 && !val2)
475 break;
476
477 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
478 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
479 ((u64)buf1[0] << 40);
480
481 sdw_extract_slave_id(bus, addr, &id);
482 found = false;
483 /* Now compare with entries */
484 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
485 if (sdw_compare_devid(slave, id) == 0) {
486 qcom_swrm_set_slave_dev_num(bus, slave, i);
487 found = true;
488 break;
489 }
490 }
491
492 if (!found) {
493 qcom_swrm_set_slave_dev_num(bus, NULL, i);
494 sdw_slave_add(bus, &id, NULL);
495 }
496 }
497
498 complete(&ctrl->enumeration);
499 return 0;
500 }
501
qcom_swrm_irq_handler(int irq,void * dev_id)502 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
503 {
504 struct qcom_swrm_ctrl *swrm = dev_id;
505 u32 value, intr_sts, intr_sts_masked, slave_status;
506 u32 i;
507 int devnum;
508 int ret = IRQ_HANDLED;
509
510 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
511 intr_sts_masked = intr_sts & swrm->intr_mask;
512
513 do {
514 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
515 value = intr_sts_masked & BIT(i);
516 if (!value)
517 continue;
518
519 switch (value) {
520 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
521 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
522 if (devnum < 0) {
523 dev_err_ratelimited(swrm->dev,
524 "no slave alert found.spurious interrupt\n");
525 } else {
526 sdw_handle_slave_status(&swrm->bus, swrm->status);
527 }
528
529 break;
530 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
531 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
532 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n",
533 __func__);
534 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
535 if (swrm->slave_status == slave_status) {
536 dev_err(swrm->dev, "Slave status not changed %x\n",
537 slave_status);
538 } else {
539 qcom_swrm_get_device_status(swrm);
540 qcom_swrm_enumerate(&swrm->bus);
541 sdw_handle_slave_status(&swrm->bus, swrm->status);
542 }
543 break;
544 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
545 dev_err_ratelimited(swrm->dev,
546 "%s: SWR bus clsh detected\n",
547 __func__);
548 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
549 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
550 break;
551 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
552 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
553 dev_err_ratelimited(swrm->dev,
554 "%s: SWR read FIFO overflow fifo status 0x%x\n",
555 __func__, value);
556 break;
557 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
558 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
559 dev_err_ratelimited(swrm->dev,
560 "%s: SWR read FIFO underflow fifo status 0x%x\n",
561 __func__, value);
562 break;
563 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
564 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
565 dev_err(swrm->dev,
566 "%s: SWR write FIFO overflow fifo status %x\n",
567 __func__, value);
568 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
569 break;
570 case SWRM_INTERRUPT_STATUS_CMD_ERROR:
571 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
572 dev_err_ratelimited(swrm->dev,
573 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
574 __func__, value);
575 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
576 break;
577 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
578 dev_err_ratelimited(swrm->dev,
579 "%s: SWR Port collision detected\n",
580 __func__);
581 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
582 swrm->reg_write(swrm,
583 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
584 break;
585 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
586 dev_err_ratelimited(swrm->dev,
587 "%s: SWR read enable valid mismatch\n",
588 __func__);
589 swrm->intr_mask &=
590 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
591 swrm->reg_write(swrm,
592 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
593 break;
594 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
595 complete(&swrm->broadcast);
596 break;
597 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
598 break;
599 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
600 break;
601 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
602 break;
603 default:
604 dev_err_ratelimited(swrm->dev,
605 "%s: SWR unknown interrupt value: %d\n",
606 __func__, value);
607 ret = IRQ_NONE;
608 break;
609 }
610 }
611 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
612 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
613 intr_sts_masked = intr_sts & swrm->intr_mask;
614 } while (intr_sts_masked);
615
616 return ret;
617 }
618
qcom_swrm_init(struct qcom_swrm_ctrl * ctrl)619 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
620 {
621 u32 val;
622
623 /* Clear Rows and Cols */
624 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
625 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
626
627 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
628
629 /* Enable Auto enumeration */
630 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
631
632 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
633 /* Mask soundwire interrupts */
634 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
635 SWRM_INTERRUPT_STATUS_RMSK);
636
637 /* Configure No pings */
638 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
639 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
640 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
641
642 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
643 /* Configure number of retries of a read/write cmd */
644 if (ctrl->version >= 0x01050001) {
645 /* Only for versions >= 1.5.1 */
646 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
647 SWRM_RD_WR_CMD_RETRIES |
648 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
649 } else {
650 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
651 SWRM_RD_WR_CMD_RETRIES);
652 }
653
654 /* Set IRQ to PULSE */
655 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
656 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
657 SWRM_COMP_CFG_ENABLE_MSK);
658
659 /* enable CPU IRQs */
660 if (ctrl->mmio) {
661 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
662 SWRM_INTERRUPT_STATUS_RMSK);
663 }
664 ctrl->slave_status = 0;
665 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
666 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
667 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
668
669 return 0;
670 }
671
qcom_swrm_xfer_msg(struct sdw_bus * bus,struct sdw_msg * msg)672 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
673 struct sdw_msg *msg)
674 {
675 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
676 int ret, i, len;
677
678 if (msg->flags == SDW_MSG_FLAG_READ) {
679 for (i = 0; i < msg->len;) {
680 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
681 len = msg->len - i;
682 else
683 len = QCOM_SWRM_MAX_RD_LEN;
684
685 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
686 msg->addr + i, len,
687 &msg->buf[i]);
688 if (ret)
689 return ret;
690
691 i = i + len;
692 }
693 } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
694 for (i = 0; i < msg->len; i++) {
695 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
696 msg->dev_num,
697 msg->addr + i);
698 if (ret)
699 return SDW_CMD_IGNORED;
700 }
701 }
702
703 return SDW_CMD_OK;
704 }
705
qcom_swrm_pre_bank_switch(struct sdw_bus * bus)706 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
707 {
708 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
709 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
710 u32 val;
711
712 ctrl->reg_read(ctrl, reg, &val);
713
714 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
715 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
716
717 return ctrl->reg_write(ctrl, reg, val);
718 }
719
qcom_swrm_port_params(struct sdw_bus * bus,struct sdw_port_params * p_params,unsigned int bank)720 static int qcom_swrm_port_params(struct sdw_bus *bus,
721 struct sdw_port_params *p_params,
722 unsigned int bank)
723 {
724 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
725
726 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
727 p_params->bps - 1);
728
729 }
730
qcom_swrm_transport_params(struct sdw_bus * bus,struct sdw_transport_params * params,enum sdw_reg_bank bank)731 static int qcom_swrm_transport_params(struct sdw_bus *bus,
732 struct sdw_transport_params *params,
733 enum sdw_reg_bank bank)
734 {
735 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
736 struct qcom_swrm_port_config *pcfg;
737 u32 value;
738 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
739 int ret;
740
741 pcfg = &ctrl->pconfig[params->port_num];
742
743 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
744 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
745 value |= pcfg->si;
746
747 ret = ctrl->reg_write(ctrl, reg, value);
748 if (ret)
749 goto err;
750
751 if (pcfg->lane_control != SWR_INVALID_PARAM) {
752 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
753 value = pcfg->lane_control;
754 ret = ctrl->reg_write(ctrl, reg, value);
755 if (ret)
756 goto err;
757 }
758
759 if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
760 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
761 value = pcfg->blk_group_count;
762 ret = ctrl->reg_write(ctrl, reg, value);
763 if (ret)
764 goto err;
765 }
766
767 if (pcfg->hstart != SWR_INVALID_PARAM
768 && pcfg->hstop != SWR_INVALID_PARAM) {
769 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
770 value = (pcfg->hstop << 4) | pcfg->hstart;
771 ret = ctrl->reg_write(ctrl, reg, value);
772 } else {
773 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
774 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
775 ret = ctrl->reg_write(ctrl, reg, value);
776 }
777
778 if (ret)
779 goto err;
780
781 if (pcfg->bp_mode != SWR_INVALID_PARAM) {
782 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
783 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
784 }
785
786 err:
787 return ret;
788 }
789
qcom_swrm_port_enable(struct sdw_bus * bus,struct sdw_enable_ch * enable_ch,unsigned int bank)790 static int qcom_swrm_port_enable(struct sdw_bus *bus,
791 struct sdw_enable_ch *enable_ch,
792 unsigned int bank)
793 {
794 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
795 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
796 u32 val;
797
798 ctrl->reg_read(ctrl, reg, &val);
799
800 if (enable_ch->enable)
801 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
802 else
803 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
804
805 return ctrl->reg_write(ctrl, reg, val);
806 }
807
808 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
809 .dpn_set_port_params = qcom_swrm_port_params,
810 .dpn_set_port_transport_params = qcom_swrm_transport_params,
811 .dpn_port_enable_ch = qcom_swrm_port_enable,
812 };
813
814 static const struct sdw_master_ops qcom_swrm_ops = {
815 .xfer_msg = qcom_swrm_xfer_msg,
816 .pre_bank_switch = qcom_swrm_pre_bank_switch,
817 };
818
qcom_swrm_compute_params(struct sdw_bus * bus)819 static int qcom_swrm_compute_params(struct sdw_bus *bus)
820 {
821 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
822 struct sdw_master_runtime *m_rt;
823 struct sdw_slave_runtime *s_rt;
824 struct sdw_port_runtime *p_rt;
825 struct qcom_swrm_port_config *pcfg;
826 struct sdw_slave *slave;
827 unsigned int m_port;
828 int i = 1;
829
830 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
831 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
832 pcfg = &ctrl->pconfig[p_rt->num];
833 p_rt->transport_params.port_num = p_rt->num;
834 if (pcfg->word_length != SWR_INVALID_PARAM) {
835 sdw_fill_port_params(&p_rt->port_params,
836 p_rt->num, pcfg->word_length + 1,
837 SDW_PORT_FLOW_MODE_ISOCH,
838 SDW_PORT_DATA_MODE_NORMAL);
839 }
840
841 }
842
843 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
844 slave = s_rt->slave;
845 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
846 m_port = slave->m_port_map[p_rt->num];
847 /* port config starts at offset 0 so -1 from actual port number */
848 if (m_port)
849 pcfg = &ctrl->pconfig[m_port];
850 else
851 pcfg = &ctrl->pconfig[i];
852 p_rt->transport_params.port_num = p_rt->num;
853 p_rt->transport_params.sample_interval =
854 pcfg->si + 1;
855 p_rt->transport_params.offset1 = pcfg->off1;
856 p_rt->transport_params.offset2 = pcfg->off2;
857 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
858 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
859
860 p_rt->transport_params.hstart = pcfg->hstart;
861 p_rt->transport_params.hstop = pcfg->hstop;
862 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
863 if (pcfg->word_length != SWR_INVALID_PARAM) {
864 sdw_fill_port_params(&p_rt->port_params,
865 p_rt->num,
866 pcfg->word_length + 1,
867 SDW_PORT_FLOW_MODE_ISOCH,
868 SDW_PORT_DATA_MODE_NORMAL);
869 }
870 i++;
871 }
872 }
873 }
874
875 return 0;
876 }
877
878 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
879 DEFAULT_CLK_FREQ,
880 };
881
qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl * ctrl,struct sdw_stream_runtime * stream)882 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
883 struct sdw_stream_runtime *stream)
884 {
885 struct sdw_master_runtime *m_rt;
886 struct sdw_port_runtime *p_rt;
887 unsigned long *port_mask;
888
889 mutex_lock(&ctrl->port_lock);
890
891 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
892 if (m_rt->direction == SDW_DATA_DIR_RX)
893 port_mask = &ctrl->dout_port_mask;
894 else
895 port_mask = &ctrl->din_port_mask;
896
897 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
898 clear_bit(p_rt->num, port_mask);
899 }
900
901 mutex_unlock(&ctrl->port_lock);
902 }
903
qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl * ctrl,struct sdw_stream_runtime * stream,struct snd_pcm_hw_params * params,int direction)904 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
905 struct sdw_stream_runtime *stream,
906 struct snd_pcm_hw_params *params,
907 int direction)
908 {
909 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
910 struct sdw_stream_config sconfig;
911 struct sdw_master_runtime *m_rt;
912 struct sdw_slave_runtime *s_rt;
913 struct sdw_port_runtime *p_rt;
914 struct sdw_slave *slave;
915 unsigned long *port_mask;
916 int i, maxport, pn, nports = 0, ret = 0;
917 unsigned int m_port;
918
919 mutex_lock(&ctrl->port_lock);
920 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
921 if (m_rt->direction == SDW_DATA_DIR_RX) {
922 maxport = ctrl->num_dout_ports;
923 port_mask = &ctrl->dout_port_mask;
924 } else {
925 maxport = ctrl->num_din_ports;
926 port_mask = &ctrl->din_port_mask;
927 }
928
929 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
930 slave = s_rt->slave;
931 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
932 m_port = slave->m_port_map[p_rt->num];
933 /* Port numbers start from 1 - 14*/
934 if (m_port)
935 pn = m_port;
936 else
937 pn = find_first_zero_bit(port_mask, maxport);
938
939 if (pn > maxport) {
940 dev_err(ctrl->dev, "All ports busy\n");
941 ret = -EBUSY;
942 goto err;
943 }
944 set_bit(pn, port_mask);
945 pconfig[nports].num = pn;
946 pconfig[nports].ch_mask = p_rt->ch_mask;
947 nports++;
948 }
949 }
950 }
951
952 if (direction == SNDRV_PCM_STREAM_CAPTURE)
953 sconfig.direction = SDW_DATA_DIR_TX;
954 else
955 sconfig.direction = SDW_DATA_DIR_RX;
956
957 /* hw parameters wil be ignored as we only support PDM */
958 sconfig.ch_count = 1;
959 sconfig.frame_rate = params_rate(params);
960 sconfig.type = stream->type;
961 sconfig.bps = 1;
962 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
963 nports, stream);
964 err:
965 if (ret) {
966 for (i = 0; i < nports; i++)
967 clear_bit(pconfig[i].num, port_mask);
968 }
969
970 mutex_unlock(&ctrl->port_lock);
971
972 return ret;
973 }
974
qcom_swrm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)975 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
976 struct snd_pcm_hw_params *params,
977 struct snd_soc_dai *dai)
978 {
979 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
980 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
981 int ret;
982
983 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
984 substream->stream);
985 if (ret)
986 qcom_swrm_stream_free_ports(ctrl, sruntime);
987
988 return ret;
989 }
990
qcom_swrm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)991 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
992 struct snd_soc_dai *dai)
993 {
994 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
995 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
996
997 qcom_swrm_stream_free_ports(ctrl, sruntime);
998 sdw_stream_remove_master(&ctrl->bus, sruntime);
999
1000 return 0;
1001 }
1002
qcom_swrm_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)1003 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1004 void *stream, int direction)
1005 {
1006 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1007
1008 ctrl->sruntime[dai->id] = stream;
1009
1010 return 0;
1011 }
1012
qcom_swrm_get_sdw_stream(struct snd_soc_dai * dai,int direction)1013 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1014 {
1015 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1016
1017 return ctrl->sruntime[dai->id];
1018 }
1019
qcom_swrm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1020 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1021 struct snd_soc_dai *dai)
1022 {
1023 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1024 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1025 struct sdw_stream_runtime *sruntime;
1026 struct snd_soc_dai *codec_dai;
1027 int ret, i;
1028
1029 sruntime = sdw_alloc_stream(dai->name);
1030 if (!sruntime)
1031 return -ENOMEM;
1032
1033 ctrl->sruntime[dai->id] = sruntime;
1034
1035 for_each_rtd_codec_dais(rtd, i, codec_dai) {
1036 ret = snd_soc_dai_set_sdw_stream(codec_dai, sruntime,
1037 substream->stream);
1038 if (ret < 0 && ret != -ENOTSUPP) {
1039 dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1040 codec_dai->name);
1041 sdw_release_stream(sruntime);
1042 return ret;
1043 }
1044 }
1045
1046 return 0;
1047 }
1048
qcom_swrm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1049 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1050 struct snd_soc_dai *dai)
1051 {
1052 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1053
1054 sdw_release_stream(ctrl->sruntime[dai->id]);
1055 ctrl->sruntime[dai->id] = NULL;
1056 }
1057
1058 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1059 .hw_params = qcom_swrm_hw_params,
1060 .hw_free = qcom_swrm_hw_free,
1061 .startup = qcom_swrm_startup,
1062 .shutdown = qcom_swrm_shutdown,
1063 .set_sdw_stream = qcom_swrm_set_sdw_stream,
1064 .get_sdw_stream = qcom_swrm_get_sdw_stream,
1065 };
1066
1067 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1068 .name = "soundwire",
1069 };
1070
qcom_swrm_register_dais(struct qcom_swrm_ctrl * ctrl)1071 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1072 {
1073 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1074 struct snd_soc_dai_driver *dais;
1075 struct snd_soc_pcm_stream *stream;
1076 struct device *dev = ctrl->dev;
1077 int i;
1078
1079 /* PDM dais are only tested for now */
1080 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1081 if (!dais)
1082 return -ENOMEM;
1083
1084 for (i = 0; i < num_dais; i++) {
1085 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1086 if (!dais[i].name)
1087 return -ENOMEM;
1088
1089 if (i < ctrl->num_dout_ports)
1090 stream = &dais[i].playback;
1091 else
1092 stream = &dais[i].capture;
1093
1094 stream->channels_min = 1;
1095 stream->channels_max = 1;
1096 stream->rates = SNDRV_PCM_RATE_48000;
1097 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1098
1099 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1100 dais[i].id = i;
1101 }
1102
1103 return devm_snd_soc_register_component(ctrl->dev,
1104 &qcom_swrm_dai_component,
1105 dais, num_dais);
1106 }
1107
qcom_swrm_get_port_config(struct qcom_swrm_ctrl * ctrl)1108 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1109 {
1110 struct device_node *np = ctrl->dev->of_node;
1111 u8 off1[QCOM_SDW_MAX_PORTS];
1112 u8 off2[QCOM_SDW_MAX_PORTS];
1113 u8 si[QCOM_SDW_MAX_PORTS];
1114 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1115 u8 hstart[QCOM_SDW_MAX_PORTS];
1116 u8 hstop[QCOM_SDW_MAX_PORTS];
1117 u8 word_length[QCOM_SDW_MAX_PORTS];
1118 u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1119 u8 lane_control[QCOM_SDW_MAX_PORTS];
1120 int i, ret, nports, val;
1121
1122 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1123
1124 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1125 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1126
1127 ret = of_property_read_u32(np, "qcom,din-ports", &val);
1128 if (ret)
1129 return ret;
1130
1131 if (val > ctrl->num_din_ports)
1132 return -EINVAL;
1133
1134 ctrl->num_din_ports = val;
1135
1136 ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1137 if (ret)
1138 return ret;
1139
1140 if (val > ctrl->num_dout_ports)
1141 return -EINVAL;
1142
1143 ctrl->num_dout_ports = val;
1144
1145 nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1146 if (nports > QCOM_SDW_MAX_PORTS)
1147 return -EINVAL;
1148
1149 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1150 set_bit(0, &ctrl->dout_port_mask);
1151 set_bit(0, &ctrl->din_port_mask);
1152
1153 ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1154 off1, nports);
1155 if (ret)
1156 return ret;
1157
1158 ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1159 off2, nports);
1160 if (ret)
1161 return ret;
1162
1163 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1164 si, nports);
1165 if (ret)
1166 return ret;
1167
1168 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1169 bp_mode, nports);
1170 if (ret) {
1171 u32 version;
1172
1173 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &version);
1174
1175 if (version <= 0x01030000)
1176 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1177 else
1178 return ret;
1179 }
1180
1181 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1182 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1183
1184 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1185 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1186
1187 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1188 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1189
1190 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1191 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1192
1193 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1194 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1195
1196 for (i = 0; i < nports; i++) {
1197 /* Valid port number range is from 1-14 */
1198 ctrl->pconfig[i + 1].si = si[i];
1199 ctrl->pconfig[i + 1].off1 = off1[i];
1200 ctrl->pconfig[i + 1].off2 = off2[i];
1201 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1202 ctrl->pconfig[i + 1].hstart = hstart[i];
1203 ctrl->pconfig[i + 1].hstop = hstop[i];
1204 ctrl->pconfig[i + 1].word_length = word_length[i];
1205 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1206 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1207 }
1208
1209 return 0;
1210 }
1211
qcom_swrm_probe(struct platform_device * pdev)1212 static int qcom_swrm_probe(struct platform_device *pdev)
1213 {
1214 struct device *dev = &pdev->dev;
1215 struct sdw_master_prop *prop;
1216 struct sdw_bus_params *params;
1217 struct qcom_swrm_ctrl *ctrl;
1218 const struct qcom_swrm_data *data;
1219 int ret;
1220 u32 val;
1221
1222 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1223 if (!ctrl)
1224 return -ENOMEM;
1225
1226 data = of_device_get_match_data(dev);
1227 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1228 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1229 #if IS_REACHABLE(CONFIG_SLIMBUS)
1230 if (dev->parent->bus == &slimbus_bus) {
1231 #else
1232 if (false) {
1233 #endif
1234 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1235 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1236 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1237 if (!ctrl->regmap)
1238 return -EINVAL;
1239 } else {
1240 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1241 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1242 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1243 if (IS_ERR(ctrl->mmio))
1244 return PTR_ERR(ctrl->mmio);
1245 }
1246
1247 ctrl->irq = of_irq_get(dev->of_node, 0);
1248 if (ctrl->irq < 0) {
1249 ret = ctrl->irq;
1250 goto err_init;
1251 }
1252
1253 ctrl->hclk = devm_clk_get(dev, "iface");
1254 if (IS_ERR(ctrl->hclk)) {
1255 ret = PTR_ERR(ctrl->hclk);
1256 goto err_init;
1257 }
1258
1259 clk_prepare_enable(ctrl->hclk);
1260
1261 ctrl->dev = dev;
1262 dev_set_drvdata(&pdev->dev, ctrl);
1263 mutex_init(&ctrl->port_lock);
1264 init_completion(&ctrl->broadcast);
1265 init_completion(&ctrl->enumeration);
1266
1267 ctrl->bus.ops = &qcom_swrm_ops;
1268 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1269 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1270
1271 ret = qcom_swrm_get_port_config(ctrl);
1272 if (ret)
1273 goto err_clk;
1274
1275 params = &ctrl->bus.params;
1276 params->max_dr_freq = DEFAULT_CLK_FREQ;
1277 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1278 params->col = data->default_cols;
1279 params->row = data->default_rows;
1280 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1281 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1282 params->next_bank = !params->curr_bank;
1283
1284 prop = &ctrl->bus.prop;
1285 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1286 prop->num_clk_gears = 0;
1287 prop->num_clk_freq = MAX_FREQ_NUM;
1288 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1289 prop->default_col = data->default_cols;
1290 prop->default_row = data->default_rows;
1291
1292 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1293
1294 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1295 qcom_swrm_irq_handler,
1296 IRQF_TRIGGER_RISING |
1297 IRQF_ONESHOT,
1298 "soundwire", ctrl);
1299 if (ret) {
1300 dev_err(dev, "Failed to request soundwire irq\n");
1301 goto err_clk;
1302 }
1303
1304 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1305 if (ret) {
1306 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1307 ret);
1308 goto err_clk;
1309 }
1310
1311 qcom_swrm_init(ctrl);
1312 wait_for_completion_timeout(&ctrl->enumeration,
1313 msecs_to_jiffies(TIMEOUT_MS));
1314 ret = qcom_swrm_register_dais(ctrl);
1315 if (ret)
1316 goto err_master_add;
1317
1318 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1319 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1320 ctrl->version & 0xffff);
1321
1322 return 0;
1323
1324 err_master_add:
1325 sdw_bus_master_delete(&ctrl->bus);
1326 err_clk:
1327 clk_disable_unprepare(ctrl->hclk);
1328 err_init:
1329 return ret;
1330 }
1331
1332 static int qcom_swrm_remove(struct platform_device *pdev)
1333 {
1334 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1335
1336 sdw_bus_master_delete(&ctrl->bus);
1337 clk_disable_unprepare(ctrl->hclk);
1338
1339 return 0;
1340 }
1341
1342 static const struct of_device_id qcom_swrm_of_match[] = {
1343 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1344 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1345 {/* sentinel */},
1346 };
1347
1348 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1349
1350 static struct platform_driver qcom_swrm_driver = {
1351 .probe = &qcom_swrm_probe,
1352 .remove = &qcom_swrm_remove,
1353 .driver = {
1354 .name = "qcom-soundwire",
1355 .of_match_table = qcom_swrm_of_match,
1356 }
1357 };
1358 module_platform_driver(qcom_swrm_driver);
1359
1360 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1361 MODULE_LICENSE("GPL v2");
1362