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Searched refs:ro (Results 1 – 25 of 57) sorted by relevance

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/drivers/pci/
Dpci-bridge-emul.c41 u32 ro; member
52 [PCI_VENDOR_ID / 4] = { .ro = ~0 },
57 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
64 [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
82 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
88 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
89 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
95 .ro = GENMASK(31, 24),
103 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
115 .ro = GENMASK(19, 16) | GENMASK(3, 0),
[all …]
/drivers/usb/gadget/function/
Dstorage_common.c180 int ro; in fsg_lun_open() local
191 ro = curlun->initially_ro; in fsg_lun_open()
192 if (!ro) { in fsg_lun_open()
195 ro = 1; in fsg_lun_open()
197 if (ro) in fsg_lun_open()
205 ro = 1; in fsg_lun_open()
222 ro = 1; in fsg_lun_open()
264 curlun->ro = ro; in fsg_lun_open()
288 if (curlun->ro || !filp) in fsg_lun_fsync_sub()
321 ? curlun->ro in fsg_show_ro()
[all …]
Df_mass_storage.h10 bool ro[FSG_MAX_LUNS]; member
35 _FSG_MODULE_PARAM_ARRAY(prefix, params, ro, bool, \
89 char ro; member
Df_mass_storage.c744 if (curlun->ro) { in do_write()
1275 buf[2] = (curlun->ro ? 0x80 : 0x00); /* WP, DPOFUA */ in do_mode_sense()
1279 buf[3] = (curlun->ro ? 0x80 : 0x00); /* WP, DPOFUA */ in do_mode_sense()
2598 static DEVICE_ATTR(ro, 0, ro_show, ro_store);
2805 lun->ro = cfg->cdrom || cfg->ro; in fsg_common_create_lun()
2806 lun->initially_ro = lun->ro; in fsg_common_create_lun()
2848 lun->ro ? "read only " : "", in fsg_common_create_lun()
3106 CONFIGFS_ATTR(fsg_lun_opts_, ro);
3498 lun->ro = !!params->ro[i]; in fsg_config_from_params()
/drivers/gpu/drm/
Ddrm_crtc_helper.c526 int count = 0, ro, fail = 0; in drm_crtc_helper_set_config() local
628 for (ro = 0; ro < set->num_connectors; ro++) { in drm_crtc_helper_set_config()
629 if (set->connectors[ro]->encoder) in drm_crtc_helper_set_config()
631 drm_connector_get(set->connectors[ro]); in drm_crtc_helper_set_config()
641 for (ro = 0; ro < set->num_connectors; ro++) { in drm_crtc_helper_set_config()
642 if (set->connectors[ro] == connector) { in drm_crtc_helper_set_config()
692 for (ro = 0; ro < set->num_connectors; ro++) { in drm_crtc_helper_set_config()
693 if (set->connectors[ro] == connector) in drm_crtc_helper_set_config()
781 for (ro = 0; ro < set->num_connectors; ro++) { in drm_crtc_helper_set_config()
782 if (set->connectors[ro]->encoder) in drm_crtc_helper_set_config()
[all …]
/drivers/mtd/nand/raw/atmel/
Dpmecc.c505 int ro; in atmel_pmecc_get_sigma() local
573 ro = 0; in atmel_pmecc_get_sigma()
579 ro = j; in atmel_pmecc_get_sigma()
584 diff = (mu[i] - mu[ro]); in atmel_pmecc_get_sigma()
587 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff)) in atmel_pmecc_get_sigma()
590 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2; in atmel_pmecc_get_sigma()
597 for (k = 0; k <= lmu[ro] >> 1; k++) { in atmel_pmecc_get_sigma()
600 if (!(smu[ro * num + k] && dmu[i])) in atmel_pmecc_get_sigma()
604 b = index_of[dmu[ro]]; in atmel_pmecc_get_sigma()
605 c = index_of[smu[ro * num + k]]; in atmel_pmecc_get_sigma()
/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dvmmnv50.c237 u8 aper, kind, kind_inv, comp, priv, ro; in nv50_vmm_valid() local
245 ro = !!args->v0.ro; in nv50_vmm_valid()
251 ro = 0; in nv50_vmm_valid()
316 map->type |= (u64)ro << 3; in nv50_vmm_valid()
Dvmmgf100.c249 u8 kind, kind_inv, priv, ro, vol; in gf100_vmm_valid() local
258 ro = !!args->v0.ro; in gf100_vmm_valid()
264 ro = 0; in gf100_vmm_valid()
314 map->type |= (u64) ro << 2; in gf100_vmm_valid()
Dmemgf100.c47 uvmm.ro = args->v0.ro; in gf100_mem_map()
Dmemnv50.c48 uvmm.ro = args->v0.ro; in nv50_mem_map()
Dvmmgp100.c416 u8 kind, kind_inv, priv, ro, vol; in gp100_vmm_valid() local
425 ro = !!args->v0.ro; in gp100_vmm_valid()
431 ro = 0; in gp100_vmm_valid()
478 map->type |= (u64) ro << 6; in gp100_vmm_valid()
/drivers/nvdimm/
Dregion_devs.c518 return sprintf(buf, "%d\n", nd_region->ro); in read_only_show()
530 bool ro; in read_only_store() local
531 int rc = strtobool(buf, &ro); in read_only_store()
537 nd_region->ro = ro; in read_only_store()
1047 int ro = 0; in nd_region_create() local
1061 ro = 1; in nd_region_create()
1128 nd_region->ro = ro; in nd_region_create()
Dbus.c629 if (disk_ro == nd_region->ro) in nvdimm_check_and_set_ro()
633 dev_name(&nd_region->dev), nd_region->ro ? "only" : "write", in nvdimm_check_and_set_ro()
634 disk->disk_name, nd_region->ro ? "only" : "write"); in nvdimm_check_and_set_ro()
635 set_disk_ro(disk, nd_region->ro); in nvdimm_check_and_set_ro()
1228 int rc, ro; in nd_ioctl() local
1230 ro = ((file->f_flags & O_ACCMODE) == O_RDONLY); in nd_ioctl()
1257 rc = __nd_ioctl(nvdimm_bus, nvdimm, ro, cmd, arg); in nd_ioctl()
/drivers/gpu/drm/nouveau/include/nvif/
Dif500d.h16 __u8 ro; member
Dif900d.h17 __u8 ro; member
Dif900b.h20 __u8 ro; member
Difb00d.h23 __u8 ro; member
Dif500b.h21 __u8 ro; member
Difc00d.h23 __u8 ro; member
/drivers/gpu/drm/nouveau/
Dnouveau_mem.c50 args.nv50.ro = 0; in nouveau_mem_map()
64 args.gf100.ro = 0; in nouveau_mem_map()
/drivers/hwmon/
Dibmaem.c913 const struct aem_ro_sensor_template *ro, in aem_register_sensors() argument
921 while (ro->label) { in aem_register_sensors()
923 sensors->dev_attr.attr.name = ro->label; in aem_register_sensors()
925 sensors->dev_attr.show = ro->show; in aem_register_sensors()
926 sensors->index = ro->index; in aem_register_sensors()
934 ro++; in aem_register_sensors()
/drivers/staging/android/
DKconfig26 - BUILD_INFO(ro.build.fingerprint)
/drivers/s390/block/
Ddasd_ioctl.c533 int dasd_set_read_only(struct block_device *bdev, bool ro) in dasd_set_read_only() argument
545 if (!ro && test_bit(DASD_FLAG_DEVICE_RO, &base->flags)) in dasd_set_read_only()
548 rc = dasd_set_feature(base->cdev, DASD_FEATURE_READONLY, ro); in dasd_set_read_only()
/drivers/mmc/core/
Dsd.c906 int ro; in mmc_sd_get_ro() local
919 ro = host->ops->get_ro(host); in mmc_sd_get_ro()
921 return ro; in mmc_sd_get_ro()
976 int ro = mmc_sd_get_ro(host); in mmc_sd_setup_card() local
978 if (ro < 0) { in mmc_sd_setup_card()
981 } else if (ro > 0) { in mmc_sd_setup_card()
/drivers/gpu/drm/etnaviv/
Detnaviv_gem.h20 bool ro; member

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