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Searched refs:rptr (Results 1 – 25 of 85) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c52 ih->rptr = 0; in amdgpu_ih_ring_init()
161 if (wptr != READ_ONCE(ih->rptr)) { in amdgpu_ih_ring_write()
173 uint32_t cur_rptr = ih->rptr | (*prev_rptr & ~ih->ptr_mask); in amdgpu_ih_has_checkpoint_processed()
196 uint32_t checkpoint_wptr, rptr; in amdgpu_ih_wait_on_checkpoint_process() local
204 rptr = READ_ONCE(ih->rptr); in amdgpu_ih_wait_on_checkpoint_process()
207 if (rptr > checkpoint_wptr) in amdgpu_ih_wait_on_checkpoint_process()
212 checkpoint_wptr, &rptr)); in amdgpu_ih_wait_on_checkpoint_process()
236 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); in amdgpu_ih_process()
241 while (ih->rptr != wptr && --count) { in amdgpu_ih_process()
243 ih->rptr &= ih->ptr_mask; in amdgpu_ih_process()
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Dtonga_ih.c88 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
216 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
217 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
241 u32 ring_index = ih->rptr >> 2; in tonga_ih_decode_iv()
257 ih->rptr += 16; in tonga_ih_decode_iv()
273 *ih->rptr_cpu = ih->rptr; in tonga_ih_set_rptr()
274 WDOORBELL32(ih->doorbell_index, ih->rptr); in tonga_ih_set_rptr()
276 WREG32(mmIH_RB_RPTR, ih->rptr); in tonga_ih_set_rptr()
Dsi_ih.c59 adev->irq.ih.rptr = 0; in si_ih_disable_interrupts()
117 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
118 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
130 u32 ring_index = ih->rptr >> 2; in si_ih_decode_iv()
144 ih->rptr += 16; in si_ih_decode_iv()
150 WREG32(IH_RB_RPTR, ih->rptr); in si_ih_set_rptr()
Dcik_ih.c92 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
202 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
203 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
247 u32 ring_index = ih->rptr >> 2; in cik_ih_decode_iv()
263 ih->rptr += 16; in cik_ih_decode_iv()
277 WREG32(mmIH_RB_RPTR, ih->rptr); in cik_ih_set_rptr()
Diceland_ih.c92 adev->irq.ih.rptr = 0; in iceland_ih_disable_interrupts()
212 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
213 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
238 u32 ring_index = ih->rptr >> 2; in iceland_ih_decode_iv()
254 ih->rptr += 16; in iceland_ih_decode_iv()
268 WREG32(mmIH_RB_RPTR, ih->rptr); in iceland_ih_set_rptr()
Dcz_ih.c92 adev->irq.ih.rptr = 0; in cz_ih_disable_interrupts()
213 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
214 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
239 u32 ring_index = ih->rptr >> 2; in cz_ih_decode_iv()
255 ih->rptr += 16; in cz_ih_decode_iv()
269 WREG32(mmIH_RB_RPTR, ih->rptr); in cz_ih_set_rptr()
Dvega10_ih.c127 ih->rptr = 0; in vega10_ih_toggle_ring_interrupts()
367 wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
368 ih->rptr = tmp; in vega10_ih_get_wptr()
396 if ((v < ih->ring_size) && (v != ih->rptr)) in vega10_ih_irq_rearm()
397 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega10_ih_irq_rearm()
418 *ih->rptr_cpu = ih->rptr; in vega10_ih_set_rptr()
419 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega10_ih_set_rptr()
425 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in vega10_ih_set_rptr()
Dnavi10_ih.c181 ih->rptr = 0; in navi10_ih_toggle_ring_interrupts()
444 wptr, ih->rptr, tmp); in navi10_ih_get_wptr()
445 ih->rptr = tmp; in navi10_ih_get_wptr()
473 if ((v < ih->ring_size) && (v != ih->rptr)) in navi10_ih_irq_rearm()
474 WDOORBELL32(ih->doorbell_index, ih->rptr); in navi10_ih_irq_rearm()
495 *ih->rptr_cpu = ih->rptr; in navi10_ih_set_rptr()
496 WDOORBELL32(ih->doorbell_index, ih->rptr); in navi10_ih_set_rptr()
502 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in navi10_ih_set_rptr()
Dvega20_ih.c131 ih->rptr = 0; in vega20_ih_toggle_ring_interrupts()
418 wptr, ih->rptr, tmp); in vega20_ih_get_wptr()
419 ih->rptr = tmp; in vega20_ih_get_wptr()
448 if ((v < ih->ring_size) && (v != ih->rptr)) in vega20_ih_irq_rearm()
449 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega20_ih_irq_rearm()
470 *ih->rptr_cpu = ih->rptr; in vega20_ih_set_rptr()
471 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega20_ih_set_rptr()
477 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in vega20_ih_set_rptr()
/drivers/gpu/drm/amd/display/dmub/inc/
Ddmub_cmd.h2437 uint32_t rptr; /**< Read pointer for consumer in bytes */ member
2454 return (rb->wrpt == rb->rptr); in dmub_rb_empty()
2468 if (rb->wrpt >= rb->rptr) in dmub_rb_full()
2469 data_count = rb->wrpt - rb->rptr; in dmub_rb_full()
2471 data_count = rb->capacity - (rb->rptr - rb->wrpt); in dmub_rb_full()
2542 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; in dmub_rb_front()
2563 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; in dmub_rb_get_rptr_with_offset()
2580 uint32_t rptr) in dmub_rb_peek_offset() argument
2582 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; in dmub_rb_peek_offset()
2603 const uint8_t *src = (const uint8_t *)(rb->base_address) + rb->rptr; in dmub_rb_out_front()
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/drivers/gpu/drm/radeon/
Dradeon_ring.c83 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); in radeon_ring_free_size() local
86 ring->ring_free_dw = rptr + (ring->ring_size / 4); in radeon_ring_free_size()
254 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); in radeon_ring_test_lockup() local
258 if (rptr != atomic_read(&ring->last_rptr)) { in radeon_ring_test_lockup()
470 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info_show() local
480 rptr = radeon_ring_get_rptr(rdev, ring); in radeon_debugfs_ring_info_show()
482 rptr, rptr); in radeon_debugfs_ring_info_show()
506 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; in radeon_debugfs_ring_info_show()
509 if (rptr == i) in radeon_debugfs_ring_info_show()
Dr600_dma.c53 u32 rptr; in r600_dma_get_rptr() local
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
58 rptr = RREG32(DMA_RB_RPTR); in r600_dma_get_rptr()
60 return (rptr & 0x3fffc) >> 2; in r600_dma_get_rptr()
Dni_dma.c55 u32 rptr, reg; in cayman_dma_get_rptr() local
58 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_dma_get_rptr()
65 rptr = RREG32(reg); in cayman_dma_get_rptr()
68 return (rptr & 0x3fffc) >> 2; in cayman_dma_get_rptr()
/drivers/net/ethernet/tehuti/
Dtehuti.c170 f->rptr = 0; in bdx_fifo_init()
1208 size = f->m.wptr - f->m.rptr; in bdx_rx_receive()
1214 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr); in bdx_rx_receive()
1229 f->m.rptr += tmp_len; in bdx_rx_receive()
1231 tmp_len = f->m.rptr - f->m.memsz; in bdx_rx_receive()
1233 f->m.rptr = tmp_len; in bdx_rx_receive()
1236 f->m.rptr, tmp_len); in bdx_rx_receive()
1289 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); in bdx_rx_receive()
1368 BDX_ASSERT(*pptr != db->rptr && /* expect either read */ in __bdx_tx_db_ptr_next()
1385 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */ in bdx_tx_db_inc_rptr()
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/drivers/crypto/ccp/
Dtee-dev.c249 u32 rptr; in tee_submit_cmd() local
261 rptr = ioread32(tee->io_regs + tee->vdata->ring_rptr_reg); in tee_submit_cmd()
266 if (!(tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
271 rptr, tee->rb_mgr.wptr); in tee_submit_cmd()
281 (tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
284 rptr, tee->rb_mgr.wptr, cmd->flag); in tee_submit_cmd()
/drivers/video/fbdev/
Dmaxinefb.c77 unsigned char *rptr; in maxinefb_ims332_read_register() local
80 rptr = regs + 0x80000 + (regno << 4); in maxinefb_ims332_read_register()
81 j = *((volatile unsigned short *) rptr); in maxinefb_ims332_read_register()
/drivers/net/ppp/
Dppp_deflate.c46 static int z_compress(void *state, unsigned char *rptr,
185 static int z_compress(void *arg, unsigned char *rptr, unsigned char *obuf, in z_compress() argument
195 proto = PPP_PROTOCOL(rptr); in z_compress()
209 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
210 wptr[1] = PPP_CONTROL(rptr); in z_compress()
221 rptr += off; in z_compress()
222 state->strm.next_in = rptr; in z_compress()
Dbsd_comp.c184 static int bsd_compress (void *state, unsigned char *rptr,
563 static int bsd_compress (void *state, unsigned char *rptr, unsigned char *obuf, in bsd_compress() argument
615 ent = PPP_PROTOCOL(rptr); in bsd_compress()
641 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress()
642 *wptr++ = PPP_CONTROL(rptr); in bsd_compress()
650 rptr += PPP_HDRLEN; in bsd_compress()
656 c = *rptr++; in bsd_compress()
/drivers/gpu/drm/qxl/
Dqxl_object.c210 void *rptr; in qxl_bo_kmap_atomic_page() local
226 rptr = bo->kptr + (page_offset * PAGE_SIZE); in qxl_bo_kmap_atomic_page()
227 return rptr; in qxl_bo_kmap_atomic_page()
233 rptr = bo_map.vaddr; /* TODO: Use mapping abstraction properly */ in qxl_bo_kmap_atomic_page()
235 rptr += page_offset * PAGE_SIZE; in qxl_bo_kmap_atomic_page()
236 return rptr; in qxl_bo_kmap_atomic_page()
/drivers/i2c/busses/
Di2c-cpm.c305 int rptr; in cpm_i2c_xfer() local
317 rptr = 0; in cpm_i2c_xfer()
329 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr); in cpm_i2c_xfer()
331 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr); in cpm_i2c_xfer()
333 rptr++; in cpm_i2c_xfer()
346 rptr = 0; in cpm_i2c_xfer()
355 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY), in cpm_i2c_xfer()
368 ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr); in cpm_i2c_xfer()
371 rptr++; in cpm_i2c_xfer()
/drivers/gpu/drm/amd/amdkfd/
Dkfd_kernel_queue.c233 uint32_t wptr, rptr; in kq_acquire_packet_buffer() local
242 rptr = *kq->rptr_kernel; in kq_acquire_packet_buffer()
248 pr_debug("rptr: %d\n", rptr); in kq_acquire_packet_buffer()
252 available_size = (rptr + queue_size_dwords - 1 - wptr) % in kq_acquire_packet_buffer()
267 if (packet_size_in_dwords >= rptr) in kq_acquire_packet_buffer()
/drivers/net/ethernet/cavium/liquidio/
Docteon_iq.h195 u64 rptr; member
226 u64 rptr; member
253 u64 rptr; member
Docteon_nic.c74 sc->cmd.cmd3.rptr = sc->dmarptr; in octeon_alloc_soft_command_resp()
76 sc->cmd.cmd2.rptr = sc->dmarptr; in octeon_alloc_soft_command_resp()
/drivers/tty/
Dmoxa.c270 u16 rptr, wptr, mask, len; in moxa_low_water_check() local
273 rptr = readw(ofsAddr + RXrptr); in moxa_low_water_check()
276 len = (wptr - rptr) & mask; in moxa_low_water_check()
1987 u16 rptr, wptr, mask; in MoxaPortTxQueue() local
1989 rptr = readw(ofsAddr + TXrptr); in MoxaPortTxQueue()
1992 return (wptr - rptr) & mask; in MoxaPortTxQueue()
1998 u16 rptr, wptr, mask; in MoxaPortTxFree() local
2000 rptr = readw(ofsAddr + TXrptr); in MoxaPortTxFree()
2003 return mask - ((wptr - rptr) & mask); in MoxaPortTxFree()
2009 u16 rptr, wptr, mask; in MoxaPortRxQueue() local
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/drivers/infiniband/hw/cxgb4/
Dcq.c315 u32 rptr = wq->sq.oldest_read - wq->sq.sw_sq + 1; in advance_oldest_read() local
317 if (rptr == wq->sq.size) in advance_oldest_read()
318 rptr = 0; in advance_oldest_read()
319 while (rptr != wq->sq.pidx) { in advance_oldest_read()
320 wq->sq.oldest_read = &wq->sq.sw_sq[rptr]; in advance_oldest_read()
324 if (++rptr == wq->sq.size) in advance_oldest_read()
325 rptr = 0; in advance_oldest_read()

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